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5962-8700208UA中文资料

?2008 Integrated Device Technology, Inc.

OCTOBER 2008

HIGH SPEED

2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA IDT7142SA/LA

Functional Block Diagram

Features

◆

High-speed access

–Commercial: 20/25/35/55/100ns (max.)–Industrial: 25ns (max.)

–Military: 25/35/55/100ns (max.)◆

Low-power operation – IDT7132/42SA

Active: 325mW (typ.)Standby: 5mW (typ.)–IDT7132/42LA

Active: 325mW (typ.)Standby: 1mW (typ.)

NOTES:

1.IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270?.IDT7142 (SLAVE): BUSY is input.

2.Open drain output: requires pullup resistor of 270?.

◆

MASTER IDT7132 easily expands data bus width to 16-or-more bits using SLAVE IDT7142

◆On-chip port arbitration logic (IDT7132 only)

◆BUSY output flag on IDT7132; BUSY input on IDT7142◆Battery backup operation —2V data retention (LA only)◆TTL-compatible, single 5V ±10% power supply

◆

Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC packages

◆Military product compliant to MIL-PRF-38535 QML

◆

Industrial temperature range (–40°C to +85°C) is available for

selected speeds

OE L CE L R/W L

I/O OL-I/O 7L

BUSY L A 10L A 0L

R R W R

OR-I/O 7R

R (1,2)

10R 0R

2692drw 01

◆

Green parts available, see ordering information

Pin Configurations (1,2,3)

NOTES:

1.All V CC pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.P48-1 package body is approximately .55 in x 2.43 in x .18 in.C48-2 package body is approximately .62 in x 2.43 in x .15 in.L48-1 package body is approximately .57 in x .57 in x .68 in.F48-1 package body is approximately .75 in x .75 in x .11 in.

4.This package code is used to reference the package diagram.

5.This text does not indicate orientation of the actual part-marking.

Description

The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs.The I DT7132 i s d esigned t o b e u sed a s a s tand-alone 8-bit D ual-Port R AM or as a “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE”Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

Both devices provide two independent ports with separate control,address, and l/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by C E permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA)versions offer battery backup data retention capability, with each Dual-Port typically consuming 200μW from a 2V battery.

The IDT7132/7142 devices are packaged in a 48-pin sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead https://www.wendangku.net/doc/7218473222.html,itary grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

2692drw 02

GND

I/O 6R I/O 5R I/O 4R I/O 3R I/O 2R I/O 1R I/O 0R

I/O 7L I/O 6L I/O 5L I/O 4L CE R CE L OE L A 0L BUSY L R/W L R/W R BUSY R V CC

OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O 7R I/O 3L A 1L A 2L A 3L

A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L A 10L A 10R INDEX

2692drw 03

G N D R

A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O 7R I /O 3L

S Y L

S Y R

I/O 6R

I /O 5R

I /O 4R

I /O 3R

I /O 2R

I /O 1R

I /O 0R

I /O 7L

I /O 6L

I /O 5L

I /O 4L

Capacitance (1) (T A = +25°C,f = 1.0MHz)

NOTES:

1.This parameter is determined by device characterization but is not production tested.

2.3dV represents the interpolated capacitance when the input and output signals switch from 3V to 0V.

Symbol Parameter

Conditions (2)Max.Unit C IN Input Capacitance V IN = 3dV 11pF C OUT

Output Capacitance

V OUT = 3dV

2692 tbl 00

INDEX

N /C G N D OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R N/C I/O 7R

drw 04

I /O 6R

E L

C L

C S Y L

W L

W R

S Y R

I /O 5R

I /O 4R

I /O 3R

I /O 2R

I /O 1R

I /O 0R

I /O 7L

I /O 6L

I /O 5L

I /O 4L

Absolute Maximum Ratings (1)

Recommended DC Operating Conditions

Recommended Operating

(1,2)

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V TERM > Vcc + 10%.

NOTES:

1.This is the parameter T A . This is the "instant on" case temperature.

2.Industrial temperature: for specific speeds, packages and powers contact your

sales office.

NOTES:

1.V IL (min.) = -1.5V for pulse width less than 10ns.

2.V TERM must not exceed Vcc + 10%.

NOTES:

1.All V CC pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.Package body is approximately .75 in x .75 in x .17 in.

4.This package code is used to reference the package diagram.

5.This text does not indicate orientation of the actual part-marking.

Pin Configurations (1,2,3) (con't.)

Symbol Rating Commercial & Industrial Military Unit V TERM (2)

T erminal Voltage with Respect to GND -0.5 to +7.0

-0.5 to +7.0

T BIAS T emperature Under Bias -55 to +125-65 to +135o

C T STG Storage T emperature -65 to +150

-65 to +150

I OUT

DC Output Current

2692 tbl 01

2692 tbl 02

Symbol Parameter

Min.Typ.Max.Unit V CC Supply Voltage 4.5 5.0 5.5V GND Ground

0V V IH Input High Voltage 2.2____ 6.0(2)V V IL

Input Low Voltage

-0.5(1)

____

0.8

2692 tbl 03

(1,5,8)NOTES:

1.'X' in part numbers indicates power rating (SA or LA).

2.PLCC Package only

3.At f = f Max , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC , and using “AC TEST CONDITIONS” of input levels

of GND to 3V.

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

5.Vcc = 5V, T A =+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)

6.Port "A" may be either left or right port. Port "B" is opposite from port "A".

7.Not available in DIP packages.

8.Industrial temperature: for specific speeds, packages and powers contact your sales office.

2692 tbl 04b

NOTES:

1.V CC = 2V, T A = +25°C, and is not production tested.

2.t RC = Read Cycle Time

3.This parameter is guaranteed but not production tested.

NOTE:

1.At Vcc <

2.0V leakages are undefined.

Temperature Supply Voltage Range (V CC = 5.0V ± 10%)

Data Retention Waveform

V CC

C E

2692drw 05

Symbol Parameter

Test Conditions

7132SA 7142SA

7132LA 7142LA Unit Min.

Max.Min.

Max.|I LI |Input Leakage Current (1)V CC = 5.5V,V IN = 0V to V CC

___

10___

5μA

|I LO |Output Leakage Current V CC = 5.5V,

CE = V IH , V OUT = 0V to V CC ___10___

5μA V OL Output Low Voltage I OL = 4mA ___0.4___0.4V V OL Open Drain Output Low Voltage (BUSY )I OL = 16mA ___

0.5

___

0.5

V V OH

Output High Voltage

I OH = -4mA

2.4___

2.4

___

2692 tbl 05

2692 tbl 06

775?

DATA OUT

2692drw 06

BUSY

for 55and 100ns versions

Figure 2. Output Test Load

(for t HZ , t LZ , t WZ , and t OW )* Including scope and jig

Figure 1. AC Output Test Load

Figure 3. BUSY AC Output Test Load

AC Test Conditions

Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load

GND to 3.0V 3ns Max.1.5V 1.5V Figures 1, 2, and 3

2692 tbl 07

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(3,5)

NOTES:

1.Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).

2.PLCC package only.

3.'X' in part numbers indicates power rating (SA or LA).

4.This parameter is guaranteed by device characterization, but is not production tested.

5.Industrial temperature: for specific speeds, packages and powers contact your sales office.7132X20(2)

7142X20(2)

Com'l Only

7132X25(2)

7142X25(2)

Com'l, Ind

& Military

7132X35

7142X35

Com'l &

Military

Unit

Symbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

t RC Read Cycle Time20____25____35____ns t AA Address Access Time____20____25____35ns t ACE Chip Enable Access Time____20____25____35ns t AOE Output Enable Access Time____11____12____20ns t OH Output Hold from Address Change3____3____3____ns t LZ Output Low-Z Time(1,4)0____0____0____ns t HZ Output High-Z Time(1,4)____10____10____15ns t PU Chip Enable to Power Up Time(4)0____0____0____ns t PD Chip Disable to Power Down Time(4)____20____25____35ns

2692 tbl 08a

7132X55 7142X55 Com'l & Military 7132X100

7142X100

Com'l &

Military

Unit

Symbol Parameter Min.Max.Min.Max.

READ CYCLE

t RC Read Cycle Time55____100____ns t AA Address Access Time____55____100ns t ACE Chip Enable Access Time____55____100ns t AOE Output Enable Access Time____25____40ns t OH Output Hold from Address Change3____10____ns t LZ Output Low-Z Time(1,4)5____5____ns t HZ Output High-Z Time(1,4)____25____40ns t PU Chip Enable to Power Up Time(4)0____0____ns t PD Chip Disable to Power Down Time(4)____50____50ns

2692 tbl 08b

Timing Waveform of Read Cycle No. 2, Either Side (1)

NOTES:

1.R/W = V IH, CE = V IL, and is OE = V IL. Address is valid prior to the coincidental with CE transition LOW.

2.t BDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has

no relationship to valid output data.

3.Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA , and t BDD .

4.Timing depends on which signal is asserted last, OE or CE .

5.Timing depends on which signal is de-asserted first, OE or CE .

Timing Waveform of Read Cycle No. 1, Either Side (1)

ADDRESS

DATA OUT

BUSY OUT

DATA OUT

CURRENT

I CC

I SS

2692drw 08

AC Electrical Characteristics Over the

Operating Temperature Supply Voltage Range (5,6)

NOTES:

1.Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization

but is not production tested.2.PLCC package only.

3.For Master/Slave combination, t WC = t BAA + t WP , since R/W = V IL must occur after t BAA .

4.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the

bus for the required t DW . If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .5.'X' in part numbers indicates power rating (SA or LA).

6.Industrial temperature: for specific speeds, packages and powers contact your sales office.

Symbol Parameter 7132X20(2)7142X20(2)Com'l Only

7132X25(2)7142X25(2)Com'l, Ind & Military 7132X357142X35Com'l &Military Unit

Min.Max.

Min.

Max.

Min.

Max.

WRITE CYCLE

t WC Write Cycle Time (3)

20____25____35____ns t EW Chip Enable to End-of-Write 15____20____30____ns t AW Address Valid to End-of-Write 15____20____30____ns t AS Address Set-up Time 0____0____0____ns t WP Write Pulse Width (4)15____15____25____ns t WR Write Recovery Time 0____0____0____ns t DW Data Valid to End-of-Write 10

____

ns t HZ Output High-Z Time (1)____

____

ns t DH Data Hold Time

____

ns t WZ Write Enable to Output in High-Z (1)____

____

ns t OW

Output Active from End-of-Write (1)

0____

____

2692 tbl 09

Symbol Parameter 7132X557142X55Com'l &Military

7132X1007142X100Com'l &Military Unit

Min.Max.

Min.

Max.

WRITE CYCLE

t WC Write Cycle Time (3)

55____100____ns t EW Chip Enable to End-of-Write 40____90____ns t AW Address Valid to End-of-Write 40____90____ns t AS Address Set-up Time 0____0____ns t WP Write Pulse Width (4)30____55____ns t WR Write Recovery Time 0____0____ns t DW Data Valid to End-of-Write 20

____

ns t HZ Output High-Z Time (1)____

____

ns t DH Data Hold Time

____

ns t WZ Write Enable to Output in High-Z (1)____

____

ns t OW

Output Active from End-of-Write (1)

0____

____

2692 tbl 10

ADDRESS

R/W

DATA IN

2692drw 10Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)

Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)

NOTES:

1.R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t EW or t WP ) of CE = V IL and R/W = V IL .

3.t WR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4.During this period, the l/O pins are in the output state and input signals must not be applied.

5.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6.Timing depends on which enable signal (CE or R/W) is asserted last.

7.This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the bus for the required t DW . If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .

ADDRESS

R/W

DATA OUT

DATA IN

2692drw 09

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range (7,8)

NOTES:

1.PLCC package only.

2.Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”

3.To ensure that the earlier of the two ports wins.

4.t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).

5.To ensure that a write cycle is inhibited on port "B" during contention on port "A".

6.To ensure that a write cycle is completed on port "B" after contention on port "A".

7.'X' in part numbers indicates power rating (SA or LA).

8.Industrial temperature: for specific speeds, packages and powers contact your sales office.

7132X20(1)7142X20(1)Com'l Only

7132X25(2)7142X25(2)Com'l, Ind & Military 7132X357142X35Com'l &Military Symbol

Parameter Min.Max.

Min.

Max.

Min.

Max.

Unit

BUSY Timing (For Master IDT7132 Only)t BAA BUSY Access Time from Address ____20____20____20ns t BDA BUSY Disable Time from Address ____20____20____20ns t BAC BUSY Access Time from Chip Enable ____20____20____20ns t BDC BUSY Disable Time from Chip Enable ____20____20____20ns t WDD Write Pulse to Data Delay (2)____

____

ns t WH Write Hold After BUSY (6)

____

ns t DDD Write Data Valid to Read Data Delay (2)____

____

ns t APS Arbitration Priority Set-up Time (3)5

____

ns t BDD

BUSY Disable to Valid Data (4)

____

25____

35____

BUSY Timing (For Slave IDT7142 Only)t WB Write to BUSY Input (5)0____0____0____ns t WH Write Hold After BUSY (6)12

____

ns t WDD Write Pulse to Data Delay (2)

____40____50____60ns t DDD

Write Data Valid to Read Data Delay (2)

____

2692 tbl 11a

7132X557142X55Com'l &Military

7132X1007142X100Com'l &Military Symbol

Parameter Min.Max.

Min.

Max.

Unit

BUSY Timing (For Master IDT7132 Only)t BAA BUSY Access Time from Address ____30____50ns t BDA BUSY Disable Time from Address ____30____50ns t BAC BUSY Access Time from Chip Enable ____30____50ns t BDC BUSY Disable Time from Chip Enable ____30____50ns t WDD Write Pulse to Data Delay (2)____

____

120

ns t WH Write Hold After BUSY (6)

____

ns t DDD Write Data Valid to Read Data Delay (2)____

____

100

ns t APS Arbitration Priority Set-up Time (3)5

____

ns t BDD

BUSY Disable to Valid Data (4)

____

50____

BUSY Timing (For Slave IDT7142 Only)t WB Write to BUSY Input (5)0____0____ns t WH Write Hold After BUSY (6)20

____

ns t WDD Write Pulse to Data Delay (2)

____80____120ns t DDD

Write Data Valid to Read Data Delay (2)

____

100

2692 tbl 11b

Timing Waveform of Write with BUSY (4)

NOTES:

1.t WH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).

2.BUSY is asserted on port "B" blocking R/W "B", until BUSY "B" goes HIGH.

3.t WB applies only to the slave version (IDT7142).

4.All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

Timing Waveform of Write with Port-to-Port Read and BUSY (2,3,4)

BUSY "B"

R/W "A"

R/W "B"

ADDR "B"

DATA OUT"B"

DATA IN"A"

ADDR "A"

R/W "A"

BUSY "B"

2692drw 11

NOTES:

1.To ensure that the earlier of the two ports wins. t APS is ignored for Slave (IDT7142).

2.CE L = CE R = V IL

3.OE = V IL for the reading port.

4.All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

Timing Waveform of BUSY Arbitration Controlled by CE Timing (1)

Timing Waveform of BUSY Arbitration Controlled by Address Match Timing (1)

Truth Tables

Table I. Non-Contention Read/Write Control (4)

NOTES:

1.A 0L - A 10L ≠ A 0R - A 10R

2.If BUSY = L, data is not written.

3.If BUSY = L, data may not be valid, see t WDD and t DDD timing.

4.'H' = V IH , 'L' = V IL , 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE

ADDR

"A"

and "B"CE "B"

CE "A"

BUSY "A"

2692drw 13

BUSY "B"

ADDR "A"

ADDR "B"

2692drw 14

NOTES:

1.All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2.If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).

Left or Right Port (1)

R/W CE OE D 0-7Function

X H X Z Port Disabled and in Power-Down Mode, I SB2 or I SB4X H X Z CE R = CE L = V IH, Power-Down Mode, I SB1 or I SB3L L X DATA IN Data on Port Written into Memory (2)H L L DAT A OUT

Data in Memory Output on Port (3)X

High Impedance Outputs

2692 tbl 12

The B USY outputs on the IDT7132 RAM master are totem-pole type outputs and do not require pull-up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate.

Width Expansion with Busy Logic Master/Slave Arrays

When expanding an SRAM array in width while using BUSY logic,one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master,use the BUSY signal as a write inhibit signal. Thus on the IDT7132/IDT7142 S RAMs t he B USY p in i s a n o utput i f t he p art i s M aster (IDT7132),and the BUSY pin is an input if the part is a Slave (IDT7142) as shown in Figure 3.

If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write.In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.

Table II — Address BUSY

Arbitration

NOTES:

1.Pins BUSY L and BUSY R are both outputs for IDT7132 (master). Both are inputs for IDT7142 (slave). BUSY X outputs on the IDT7132 are open drain, not push-pull outputs. On slaves the BUSY X input internally inhibits writes.

2.'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs can not be LOW simultaneously.

3.Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSY R outputs are driving LOW regardless of actual logic level on the pin.

Functional Description

The IDT7132/IDT7142 provides two ports with separate control,address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7132/IDT7142 has an automatic power down feature controlled by CE . The CE controls on-chip power down circuitry that permits the respective port to go into a

standby mode when not selected (CE = V IH ). When a port is enabled,access to the entire memory array is permitted.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding.

The use of BUSY Logic is not required or desirable for all applica-tions. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation.

Figure 4. Busy and chip enable routing for both width and depth expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.

2692drw 15

270?

Inputs

Outputs Function

CE L CE R A OL -A 10L A OR -A 10R BUSY L (1)

BUSY R (1)

X X NO

MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L

MATCH

(2)

Write Inhibit (3)

2692 tbl 13

Ordering Information

XXXX A999A A Device TypePower Speed Package Process/

Temperature

Range

BLANK I(1)

B Commercial(0°

C to+70°C)

Industrial(-40°C to+85°C)

Military(-55°C to+125°C)

Compliant to MIL-PRF-38535QML

P C J

L48 F 48-pin Plastic DIP(P48-1)

48-pin Sidebraze DIP(C48-2) 52-pin PLCC(J52-1)

48-pin LCC(L48-1)

48-pin Ceramic Flatpack(F48-1)

20 25 35 55 100Commercial PLCC Only Commercial,Industrial&Military Commercial&Military Commercial&Military Commercial&Military

LA SA Low Power Standard Power

7132 714216K(2K x8-Bit)MASTER Dual-Port RAM

16K(2K x8-Bit)SLAVE Dual-Port RAM

Speed in nanoseconds

2692drw16

G(2)Green

NOTES:

1.Industrial temperature range is available.For specific speeds, packages and powers contact your sales office.

2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History

03/24/99:Initiated d atasheet d ocument h istory

Converted to new format

Cosmetic and typographical corrections

Pages 2 and 3Added additional notes to pin configurations

06/08/99:Changed drawing format

08/26/99:Page 14Changed Busy Logic and Width Expansion copy

11/10/99:Replaced IDT logo

01/12/00:Pages 1 and 2Moved full "Description" to page 2 and adjusted page layouts

Page 1Added "(LAonly)" to paragraph

Page 2Fixed P48-1 body package description

Page 3Increased storage temperature parameters

Clarified T A parameter

Page 4DC Electrical parameters–changed wording from "open" to "disabled"

Page 6Added asteriks to Figures 1 and 3 in drw 06

Page 14Corrected part numbers

Changed ±500mV to 0mV in notes

Datasheet Document History continued on page 16

Datasheet Document History (cont'd)

06/11/04:Page 6Corrected errors in Figure 3 by changing1250?to 270? and removing "or Int" and Int Page 4, 7, 9,Clarified Industrial temp offering for 25ns

11 & 15

Page 5Removed I NT from V OL p arameter in DC Electrical Characteristics table

Page 6Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns 01/17/06:Page 1Added green availability to features

Page 15Added green indicator to ordering information

Page 16Replaced IDT address with new

10/21/08:Page 15Removed "IDT" from orderable part number