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USBLC6-2P6

?1/11USBLC6-2

VERY LOW CAPACITANCE ESD PROTECTION REV. 2

June 2005MAIN APPLICATIONS

■USB2.0 ports at 480Mbps (high speed) and USB OTG ports

■Backwards Compatible with USB1.1 Low and full speed

■Ethernet port: 10/100Mb/s ■SIM card protection ■Video line protection ■Portable and mobile electronics

DESCRIPTION

The USBLC6-2P6 and USBLC6-2SC6 are two

monolithic Application Specific Devices dedicated

to ESD protection of high speed interfaces such as

USB2.0, Ethernet links and Video lines.

The very low line capacitance secures a high level

of signal integrity without compromising in

protection sensitive chips against the most

stringent characterized ESD strikes.

FEATURES

■ 2 data lines protection

■Protects V BUS ■Very low capacitance: 3.5pF max

■Very low leakage current: 1μA max

■SOT-666 and SOT23-6L packages

■RoHS compliant

BENEFITS

■Very low capacitance between lines to GND for optimized data integrity and speed

■Ultra low PCB space consuming: 2.9mm2 max for SOT-666 package and 9mm2 max for SOT23-6L package

■Enhanced ESD protection: IEC61000-4-2 level 4 compliance guaranteed at device level,hence greater immunity at system level

■ESD protection of V BUS . Allows ESD current

flowing to Ground when ESD event occurs on data line

■High reliability offered by monolithic integration

■Very low leakage current for longer operation of battery powered devices

■Fast response time

■Consistant D+/D- signal balance - Best capacitance matching tolerance I/O to GND of 0.04pF - Compliance with USB2.0 requirement (<1pF)Table 1: Order Codes Part Number Marking USBLC6-2SC6UL26USBLC6-2P6F

Figure 1: Functional Diagram

COMPLIES WITH THE FOLLOWING STANDARDS:■IEC61000-4-2 level 4:15kV (air discharge) 8kV (contact discharge)

ASD

(Application Specific Devices)

USBLC6-22/11

Table 2: Absolute Ratings

Table 3: Electrical Characteristics (T

amb = 25°C)

Symbol

Parameter Value Unit V PP

Peak pulse voltage At device level:IEC61000-4-2 air discharge IEC61000-4-2 contact discharge MIL STD883C-Method 3015-6151525kV T stg

Storage temperature range -55 to +150°C T j

Maximum junction temperature 125°C T L Lead solder temperature (10 seconds duration)260°C Symbol

Parameter Test Conditions Value Unit Min.Typ.Max.V RM

Reverse stand-off voltage 5V I RM

Leakage current V RM = 5V 1μA V BR

Breakdown voltage between V BUS and GND I F = 1mA 6V V F Forward voltage I F = 10mA 1.1

V V CL Clamping voltage I PP = 1A, t p = 8/20μs Any I/O pin to GND 12

V I PP = 5A, t p = 8/20μs Any I/O pin to GND 17

V C i/o-GND Capacitance between I/O and GND V = 0V F = 1MHz any I/O pin to GND 2.5 3.5

pF ?C i/o-GND 0.04

C i/o-i/o Capacitance between I/O V = 0V F = 1MHz between I/O, GN

D not connected 1.2 1.7

?C i/o-i/o 0.04

USBLC6-23/11

Figure 2: Capacitance versus line voltage

(typical values)

Figure 3: Line capacitance versus frequency (typical values)Figure 4: Relative variation of leakage current

versus junction temperature (typical values)

Figure 5: Frequency response

USBLC6-24/11

TECHNICAL INFORMATION

1. SURGE PROTECTION

The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.The clamping voltage V CL can be calculated as follow :

V CL + = V BUS + V F for positive surge

V CL - = - V F for negative surge

with: V F = V T + R d .I p (V F forward drop voltage) / (V T threshold voltage)

We assume that the value of the dynamic resistance of the clamping diode is typically:

R d = 0.5? and V T = 1.2V.

For an IEC61000-4-2 surge Level 4 (Contact Discharge: V g =8kV, R g =330?), V BUS = +5V, and if in first approximation, we assume that : I p = V g / R g = 24A.

So, we find:

V CL + = +17V

V CL - = -12V

Note: the calculations do not take into account phenomena due to parasitic inductances.

2. SURGE PROTECTION APPLICATION EXAMPLE

If we consider that the connections from the pin V BUS to V CC and from GND to PCB GND are done by two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the voltage V CL has an extra value equal to Lw.dI/dt.

The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns

The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be :

V CL + = +17 + 144 = 161V

V CL - = -12 - 144 = -156V

We can reduce as much as possible these phenomena with simple layout optimization.

It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good ESD protection”).

USBLC6-25/11

3. HOW TO ENSURE A GOOD ESD PROTECTION

While the USBLC6-2 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from the V BUS pin to the power supply +V CC and from the GND pin to GND must be as short as possible to avoid overvoltages due to parasitic phenomena (see figure 6).

It’s often harder to connect the power supply near to the USBLC6-2 unlike the ground thanks to the ground plane that allows a short connection.

To ensure the same efficiency for positive surges when the connections can’t be short enough, we recommend to put close to the USBLC6-2, between V BUS and ground, a capacitance of 100nF to prevent from these kinds of overvoltage disturbances (see figure 7).

The add of this capacitance will allow a better protection by providing during surge a constant voltage.The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations described above.

IMPORTANT:

A main precaution to take is to put the protection device closer to the disturbance source (generally the connector).

Note: The measurements have been done with the USBLC6-2 in open circuit.

Figure 7: ESD behavior: optimized layout and

Figure 8: ESD behavior: measurements

Figure 9: Remaining voltage after the

USBLC6-2 during positive ESD surge Figure 10: Remaining voltage after the

USBLC6-2 during negative ESD surge Vin

Vout

Vin

Vout

USBLC6-26/11

4. CROSSTALK BEHAVIOR

4.1. Crosstalk phenomena

The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β21)increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load R L2 is α2V G2, in fact the real voltage at this point has got an extra value β21V G1.This part of the V G1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k ?).

Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).

As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmis-sion of operating signals. The frequency response (figure 5) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900MHz)

frequencies, for instance.

USBLC6-27/11

5. APPLICATION EXAMPLES

Figure 14: USB2.0 port application diagram using USBLC6-2

USBLC6-28/11

6. PSPICE MODEL

Figure 16 shows the PSPICE model of one USBLC6-2 cell. In this model, the diodes are defined by the PSPICE parameters given in figure 17.

Note: This simulation model is available only for an ambient temperature of 27°C.

Figure 16: PSPICE model

Figure 17: PSPICE parameters Figure 18:

USBLC6-2 PCB layout

USBLC6-29/11

Figure 20: SOT-666 Package Mechanical Data

Figure 19: Ordering Information Scheme

Figure 21: Foot Print Dimensions (in millimeters)

USBLC6-210/11

Figure 22: SOT23-6L Package Mechanical Data

Figure 23: Foot Print Dimensions (in millimeters)

Table 4: Ordering Information

Ordering code

Marking Package Weight Base qty Delivery mode USBLC6-2SC6

UL26SOT23-6L 16.7 mg 3000Tape & reel USBLC6-2P6F SOT-666 2.9 mg 3000Tape & reel Table 5: Revision History

Date

Revision Description of Changes

14-Mar-2005

1First issue.07-Jun-20052Format change to figure 3; no content changed.

USBLC6-211/11

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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