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VHDL源代码-计数器

十五计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY fiveteencout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END fiveteencout;

ARCHITECTURE counter OF fiveteencout IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1110") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

十四计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY fourteencout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END fourteencout;

ARCHITECTURE counter OF fourteencout IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1101") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1');

-- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

十三计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY thireteencout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END thireteencout;

ARCHITECTURE counter OF thireteencout IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1100") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

十二计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY twelvecout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END twelvecout;

ARCHITECTURE counter OF twelvecout IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1011") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

十一计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY elevencout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END elevencout;

ARCHITECTURE counter OF elevencout IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1010") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

十计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY count IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END count;

ARCHITECTURE counter OF count IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1001") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

END counter;

九计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY ninecout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END ninecout;

ARCHITECTURE counter OF ninecout IS

SIGNAL count_int:std_logic_vector(0 to 3);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="1000") THEN

count_int<="0000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

八计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY eightcout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0)); END eightcout;

ARCHITECTURE counter OF eightcout IS

SIGNAL count_int:std_logic_vector(0 to 2);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="111") THEN

count_int<="000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1');

-- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

六计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY sixcout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0));

END sixcout;

ARCHITECTURE counter OF sixcout IS SIGNAL count_int:std_logic_vector(0 to 2); BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="101") THEN

count_int<="000";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1');

-- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

--WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;

四计数器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY fourcout IS

PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(1 downto 0)); END fourcout;

ARCHITECTURE counter OF fourcout IS

SIGNAL count_int:std_logic_vector(0 to 1);

BEGIN

PROCESS(clk,reset)

BEGIN

WAIT UNTIL rising_edge(clk);

IF reset = '1' THEN

count_int <= (OTHERS => '0');

ELSIF enable = '1' THEN

IF(count_int="11") THEN

count_int<="00";

ELSE

count_int <= count_int 1;

--ELSE

-- NULL ;

--IF (count_int="1001") THEN

--count_int<="0000";

END IF;

END PROCESS;

count <= count_int;

-- IF (reset='0') then

--q<="0000";

---ELSIF(clk'event and clk='1') THEN

--q<=q 1;

--IF (q<="1001") then

--q<="0000";

---END IF;

--IF (reset<='1')THEN

--q<="00";

--ELSIF

--wait until (clk'event and clk='1');

--WAIT UNTIL (clk'EVENT AND clk = '1');

--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';

--end if;

--count<=q;

-- WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--clock'event and clock='1';

--count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';

--if (clock'event and clock='1') then

--WAIT UNTIL rising_edge(clock);

--count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';

--if (clock'event and clock='1')then

--WAIT UNTIL rising_edge(clock);

--count <= 2;

--end if;

-- END PROCESS;

END counter;