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MSM518205中文资料

DESCRIPTION

The MSM518205 is a 4,194,304-word ￥ 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM518205 achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM518205 is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP.

FEATURES

?4,194,304-word ￥ 2-bit configuration

?Single 5 V power supply, ±10% tolerance ?Input : TTL compatible, low input capacitance ?Output : TTL compatible, 3-state ?Refresh : 4096 cycles/64 ms

?Fast page mode with EDO, read modify write capability

?CAS before RAS refresh, hidden refresh, RAS -only refresh capability ?Multi-bit test mode capability ?Package options:

26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27)(Product : MSM518205-xxSJ)26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K)(Product : MSM518205-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

MSM518205

4,194,304-Word ￥ 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

MSM518205-7070 ns 130 ns 150 ns

358 mW 330 mW

Family

Access Time (Max.)Cycle Time (Min.)Standby (Max.)Power Dissipation MSM518205-80

t RAC

80 ns 35 ns t AA

40 ns 20 ns t CAC

20 ns 20 ns t OEA

20 ns

MSM518205-6060 ns 110 ns 385 mW 30 ns 15 ns 15 ns Operating (Max.) 5.5 mW

E2G0030-17-41

? Semiconductor MSM518205

PIN CONFIGURATION (TOP VIEW)

Note :

The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every V SS pin.

26/24-Pin Plastic SOJ

26/24-Pin Plastic TSOP

(K Type)

Pin Name Function A0 - A9,Address Input RAS Row Address Strobe CAS1, CAS2Column Address Strobe DQ1, DQ2Data Input/Data Output OE Output Enable WE Write Enable V CC Power Supply (5 V)NC

No Connection

A10R, A11R

345910111213

DQ2A0A1A2A3V CC 2423221817161514CAS1A7A6A5A4V SS

2DQ125NC 1V CC 26V SS 345910111213

24232218171615142251266A11R 21A9218A10R 19A81968DQ2A0A1A2A3V CC DQ1V CC A11R A10R CAS1A7A6A5A4V SS

NC V SS A9A8WE CAS2WE CAS2RAS OE RAS OE V SS Ground (0 V)

? Semiconductor MSM518205

BLOCK DIAGRAM

V CC

V SS

DQ1, DQ2

A0 - A9

FUNCTION TABLE

Function Mode

RAS H L Input Pin

CAS1*H L CAS2H WE H H H L L OE L L L H L L L L L H L L H L L H L *****H DQ1 Read DQ2 Read DQ1, DQ2 Read Refresh Standby DQ1 Write DQ Pin

DQ1High-Z High-Z D OUT D IN DQ2High-Z High-Z High-Z D OUT Don't Care High-Z D OUT D OUT Don't Care D IN

DQ2 Write L L L L H D IN D IN DQ1, DQ2 Write

High-Z

—

H *: "H" or "L"

? Semiconductor MSM518205

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

Capacitance

*: Ta = 25°C

Voltage on Any Pin Relative to V SS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature

V T Symbol I OS P D *T opr T stg

–1.0 to 7.0

5010 to 70–55 to 150

Rating mA W °C °C

Parameter

V Unit Power Supply Voltage Input High Voltage Input Low Voltage

V CC Symbol V SS V IH V IL

5.00——

Typ.Parameter

4.502.4–1.0

Min. 5.506.50.8

Max.(Ta = 0°C to 70°C)

V Unit V V V

Input Capacitance

(A0 - A9, A10R, A11R) Input Capacitance

Output Capacitance (DQ1, DQ2)

C IN1Symbol C IN2C I/O

6710

Max.pF Unit pF pF

Parameter

(V CC = 5 V ±10%, Ta = 25°C, f = 1 MHz)

———

Typ.(RAS , CAS1, CAS2, WE , OE )

? Semiconductor MSM518205

DC Characteristics

Notes : 1.I CC Max. is specified as I CC for output open condition.

2.The address can be changed once or less while RAS = V IL .

3.The address can be changed once or less while CAS1, CAS2 = V IH .

Parameter Symbol

Condition

MSM518205-60MSM518205-70MSM518205

-80(V CC = 5 V ±10%, Ta = 0°C to 70°C)

I OH = –5.0 mA Output High Voltage I OL = 4.2 mA

Output Low Voltage 0 V ￡ V I ￡ 6.5 V;All other pins not Input Leakage Current

under test = 0 V DQ disable Output Leakage Current 0 V ￡ V O ￡ 5.5 V RAS , CAS1, CAS2Average Power t RC = Min.Supply Current (Operating)RAS , CAS1, CAS2 = V IH

Power Supply RAS , CAS1, CAS2

Current (Standby)RAS cycling,Average Power CAS1, CAS2 = V IH ,

Supply Current t RC = Min.(RAS -only Refresh)RAS = V IH ,Power Supply CAS1, CAS2 = V IL ,

Current (Standby)DQ = enable Average Power CAS1, CAS2

Supply Current (CAS before RAS Refresh)RAS = V IL ,Average Power CAS1, CAS2 cycling,

Supply Current t HPC = Min.

(Fast Page Mode)

V OH V OL I LI

I LO I CC1I CC2I CC3I CC5I CC6I CC7≥ V CC –0.2 V Min.

2.40

–10

–10—

——

—

Max.V CC 0.4

1070

Min.2.40

–10

–10—

——

—

Max.V CC 0.4

1065

Min.2.40

–10

–10—

——

—

Max.V CC 0.4

1060

Unit V V

m A

mA mA

mA mA Note 1, 2

1, 2

1, 3

RAS cycling,cycling,

before RAS

? Semiconductor MSM518205

AC Characteristics (1/2)

Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time

Fast Page Mode Read Modify Write Cycle Time

Access Time from RAS Access Time from CAS

Access Time from Column Address Access Time from CAS Precharge CAS to Data Output Buffer Turn-off Delay Time Transition Time RAS Precharge Time RAS Pulse Width

RAS Pulse Width (Fast Page Mode with EDO)RAS Hold Time

CAS Pulse Width CAS Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time

Column Address Hold Time from RAS Column Address to RAS Lead Time

Access Time from OE

OE to Data Output Buffer Turn-off Delay Time Refresh Period RAS Hold Time referenced to OE

RAS Hold Time from CAS Precharge t RC t RWC t HPC t HPRWC t RAC t CAC t AA

t CPA t CEZ t T t RP t RAS t RASP t RSH t CAS t CSH t RCD t RAD t CRP t ASR t RAH t ASC t CAH t RAL

t OEA t OEZ t REF t ROH t RHCP Output Low Impedance Time from CAS t CLZ CAS Precharge Time (Fast Page Mode with EDO)t CP t AR Parameter

MSM518205-60MSM518205-70MSM518205

-80(V CC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13

Symbol Note

4, 5, 64, 54, 64, 157, 81756151414474

3Max.————60153035—1550—10,000

100,000

——10,000—4530———————

151564—Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

ns ns ms ns ns Min.150********————002608080201015502015100100155040

—0—1045Max.————80204045—1550—10,000

100,000

——10,000—6040———————

201564——Min.130********————002507070201010452015100100154535

—0—1040Max.————70203540—1550—10,000

100,000

——10,000—5035———————

201564——Min.1101552585————002406060151010402015100100104030

—0—1035—Data Output Hold After CAS Low WE to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time t DOH t WEZ t REZ

7, 87—1515ns ns ns 500—1515500—1515500OE Hold Time from CAS (DQ Disable)RAS to Second CAS Delay Time t CHO t RSCD ——ns ns 1080——1070——560

? Semiconductor MSM518205

AC Characteristics (2/2)

Write Command Pulse Width Write Command to CAS Lead Time Write Command to RAS Lead Time Data-in Set-up Time Data-in Hold Time from RAS CAS to WE Delay Time

RAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Hold Time (CAS before RAS )CAS Active Delay Time from RAS Precharge Data-in Hold Time

Write Command Hold Time

Write Command Hold Time from RAS OE Command Hold Time OE to Data-in Delay Time Write Command Set-up Time RAS to CAS Set-up Time (CAS before RAS )WE to RAS Precharge Time (CAS before RAS )WE Hold Time from RAS (CAS before RAS )RAS to WE Set-up Time (Test Mode)CAS Precharge WE Delay Time

RAS to WE Hold Time (Test Mode)

t WP t CWL t RWL t DS t DHR t CWD t RWD t AWD t CSR t CHR t RPC t DH t WCH

t WCR t OEH t OED t WCS t WRP t WRH t WTS t CPWD t WTH

MSM518205-60MSM518205-70MSM518205

-80(V CC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13

Parameter

Symbol

ns ns ns 101010Note 1611, 1410101014151411, 1414

10, 1410, 15ns

Min.

Max.ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns Min.10202004550100651020101515502020070Read Command Set-up Time Read Command Hold Time

Read Command Hold Time referenced to RAS t RCS t RCH t RRH 149, 149ns ns ns 000WE Pulse Width (DQ Disable)t WPE ns 10OE Command Hold Time

OE Precharge Time

t OCH t OEP 10101020

101515040408555102010151045151506000051010ns ns 10101020

Min.102020050501107010201015155520200750001010101010—————————————————————

———————Max.—————————————————————

———————

? Semiconductor MSM518205 Notes: 1. A start-up delay of 200 μs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device

operation is achieved.

2.The AC characteristics assume t T = 5 ns.

3.V IH (Min.) and V IL (Max.) are reference levels for measuring input timing signals.

Transition times (t T) are measured between V IH and V IL.

4.This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

5.Operation within the t RCD (Max.) limit ensures that t RAC (Max.) can be met.

t RCD (Max.) is specified as a reference point only. If t RCD is greater than the specified

t RCD (Max.) limit, then the access time is controlled by t CAC.

6.Operation within the t RAD (Max.) limit ensures that t RAC (Max.) can be met.

t RAD (Max.) is specified as a reference point only. If t RAD is greater than the specified

t RAD (Max.) limit, then the access time is controlled by t AA.

7.t CEZ (Max.), t REZ (Max.), t WEZ (Max.) and t OEZ (Max.) define the time at which the

output achieves the open circuit condition and are not referenced to output voltage

levels.

8.t CEZ and t REZ must be satisfied for open circuit condition.

9.t RCH or t RRH must be satisfied for a read cycle.

10.t WCS, t CWD, t RWD, t AWD and t CPWD are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (Min.), then

the cycle is an early write cycle and the data out will remain open circuit (high

impedance) throughout the entire cycle. If t CWD ≥ t CWD (Min.) , t RWD ≥ t RWD (Min.),

t AWD ≥ t AWD (Min.) and t CPWD ≥ t CPWD (Min.), then the cycle is a read modify write

cycle and data out will contain data read from the selected cell; if neither of the above

sets of conditions is satisfied, then the condition of the data out (at access time) is

indeterminate.

11.These parameters are referenced to the CAS leading edge in an early write cycle, and

to the WE leading edge in an OE control write cycle, or a read modify write cycle.

12.The test mode is initiated by performing a WE and CAS before RAS refresh cycle.

This mode is latched and remains in effect until the exit cycle is generated. In a test mode

CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 2 DQ

pins are used, a total of 8 data bits can be written in parallel into the memory array. In

a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data

bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the

memory device returned to its normal operating state by performing a RAS-only

refresh cycle or a CAS before RAS refresh cycle.

13.In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the

specified value. These parameters should be specified in test mode cycle by adding the

above value to the specified value in this data sheet.

14.These parameters are determined by the falling edge of either CAS1 or CAS2,

whichever is earlier.

15.These parameters are determined by the rising edge of either CAS1 or CAS2,

whichever is later.

16.t CWL should be satisfied by both CAS1 and CAS2.

17.t CP is determined by the time both CAS1 and CAS2 are high.

? Semiconductor

MSM518205

Notes concerning CAS1 and CAS2 control

Overlap the active-low timings of CAS1 and CAS2. Skew between CAS1 and CAS2 is allowed under the following conditions:

(1)The timing specification for CAS1 and CAS2 should be met individually.

(2)Different operation modes for CAS1/CAS2

are not allowed (as shown below).

RAS

CAS1CAS2WE

Delayed write

Early write

(3)Closely separated CAS1/CAS2 control is not allowed. However, when the condition

(t CP ≤ t UL

) is satisfied, fast page mode can be performed.

RAS

CAS1

CAS2

? Semiconductor

MSM518205

RAS

CAS

V IH V IL ––

V IH V

IL ––

V OH V OL ––

Address

V IH V IL ––WE

V IH V IL ––OE

V IH V IL ––

TIMING WAVEFORM

Read Cycle

"H" or "L"

RAS

CAS

V IH V IL ––

Address

V IH V IL ––WE

V IH V IL ––

E2G0099-17-41L

? Semiconductor MSM518205

Read Modify Write Cycle

RAS

CAS

V IH V IL ––

V I/OH V I/OL ––

Address

V IH V IL ––WE V IH V IL ––OE

V IH V IL ––

? Semiconductor

MSM518205

Fast Page Mode Read Cycle (Part-1)

Fast Page Mode Read Cycle (Part-2)

––

––––V IH RAS

Address

CAS

––––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL

V IH RAS

Address

CAS

V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL "H" or "L"

* : Same Data,

? Semiconductor

MSM518205

Fast Page Mode Write Cycle (Early Write)

Fast Page Mode Read Modify Write Cycle

––

––––––V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL

"H" or "L"

–

––

V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V I/OH V I/OL

? Semiconductor MSM518205

RAS -Only Refresh Cycle

CAS before RAS

Refresh Cycle

V IH V IL RAS

CAS

V IH V

IL V IH V IL WE

V V "H" or "L"

OL OH DQ

Note: OE

, Address = "H" or "L"

V IH V IL RAS

CAS

V IH V IL V IH V IL Address

"H" or "L"

Note: WE , OE = "H" or "L"V OH V OL DQ

? Semiconductor MSM518205

Hidden Refresh Read Cycle

Hidden Refresh Write Cycle

––

––––––V IH RAS

Address

CAS

––––V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL

RAS

CAS

Address

V IH V IL ––V IH V IL ––V IH V IL ––V IH V IL –

–

"H" or "L"

V IH V IL ––

V OH V OL –

–

? Semiconductor MSM518205

Test Mode Initiate Cycle

V IH V IL RAS

CAS

V IH V IL

"H" or "L"

V OH V OL V IH V IL Note: OE , Address = "H" or "L"

? Semiconductor MSM518205

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

SOJ26/24-P-300-1.27

Package material Lead frame material Pin treatment

Solder plate thickness Package weight (g)Epoxy resin 42 alloy

Solder plating 5 m m or more 0.80 TYP.

Mirror finish

? Semiconductor MSM518205

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Package material Lead frame material Pin treatment

Solder plate thickness Package weight (g)Epoxy resin 42 alloy

Solder plating 5 m m or more 0.29 TYP.

TSOP II 26/24-P-300-1.27-K

Mirror finish