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KK74ACT174中文资料

TECHNICAL DATA

KK 74ACT174

Hex D Flip-Flop with

Common Clock and Reset

High-Speed Silicon-Gate CMOS

The KK HC/HCT174. The KK 74ACT174 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. ? TTL/NMOS Compatible Input Levels

? Outputs Directly Interface to CMOS, NMOS, and TTL

? Operating Voltage Range: 4.5 to 5.5 V

? Low Input Current: 1.0 μA; 0.1 μA @ 25°C

? Outputs Source/Sink 24 mA

X = Don’t care

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16=V CC PIN 8 = GND

MAXIMUM RATINGS*

Symbol Parameter Value

Unit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

V IN DC Input Voltage (Referenced to GND) -0.5 to V CC +0.5 V

V OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 V

I IN DC Input Current, per Pin ±20 mA

I OUT DC Output Sink/Source Current, per Pin ±50 mA

I CC DC Supply Current, V CC and GND Pins ±50 mA

P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750

500

Tstg Storage Temperature -65 to +150 °C

T L Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min

Max

Unit V CC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V

T J Junction Temperature (PDIP) 140 °C

T A Operating Temperature, All Package Types -40 +85 °C

I OH Output Current - High -24 mA

I OL Output Current - Low 24 mA

t r, t f Input Rise and Fall Time *

(except Schmitt Inputs) V CC =4.5 V

V CC =5.5 V

8.0

ns/V

* V

from 0.8 V to 2.0 V

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or V OUT)≤V CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

V CC Guaranteed Limits Symbol Parameter Test

Conditions V

25 °C -40°C to

85°C

Unit

V IH Minimum High-

Level Input Voltage V OUT=0.1 V or V CC-0.1 V 4.5

5.5

2.0

V IL Maximum Low -

Level Input Voltage V OUT=0.1 V or V CC-0.1 V 4.5

5.5

0.8

V OH Minimum High-

Level Output Voltage I OUT≤ -50 μA 4.5

5.5

4.4

5.4

4.4

5.4

=V IH or V IL

I OH=-24 mA

4.5

5.5

3.86

4.86

3.76

4.76

V OL Maximum Low-

Level Output Voltage I OUT≤ 50 μA 4.5

5.5

0.1

=V IH or V IL

I OL=24 mA

4.5

5.5

0.36

0.44

I IN Maximum Input

Leakage Current

V IN=V CC or GND 5.5±0.1 ±1.0 μA

?I CCT Additional Max.

I CC/Input

V IN=V CC - 2.1 V 5.5 1.5 mA

I OLD+Minimum Dynamic

Output Current

V OLD=1.65 V Max 5.575 mA

I OHD+Minimum Dynamic

Output Current

V OHD=3.85 V Min 5.5-75 mA

I CC Maximum Quiescent

Supply Current

(per Package)

V IN=V CC or GND 5.58.0 80 μA

* All outputs loaded; thresholds on input associated with output under test.

+Maximum test duration 2.0 ms, one output loaded at a time.

AC ELECTRICAL CHARACTERISTICS (V CC=5.0 V ± 10%, C L=50pF,Input t r=t f=3.0 ns)

Limits

Guaranteed Symbol Parameter 25 °C -40°C to

Unit

85°C

Max

Min Max Min

f max Maximum Clock Frequency (Figure 1) 165140 ns

t PLH Propagation Delay, Clock to Q (Figure 1) 1.5 10.5 1.5 11.5 ns

t PHL Propagation Delay, Clock to Q (Figure 1) 1.5 10.5 1.5 11.5 ns

t PHL Propagation Delay, Reset to Q (Figure 2) 1.5 9.5 1.5 11.0 ns

C IN Maximum Input Capacitance 4.5 4.5 pF

Typical @25°C,V CC=5.0 V

C P

D Power Dissipation Capacitance 85 pF

TIMING REQUIREMENTS(V CC=5.0 V ± 10%, C L=50pF,Input t r=t f=3.0 ns)

Guaranteed

Limits Symbol Parameter 25 °C -40°C to 85°C Unit t su Minimum Setup Time, Data to Clock (Figure 3) 1.5 1.5 ns

t h Minimum Hold Time, Clock to Data (Figure 3) 2.0 2.0 ns

t w Minimum Pulse Width, Reset (Figure 2) 3.0 3.5 ns

t w Minimum Pulse Width, Clock (Figure 1) 3.0 3.5 ns

t rec Minimum Recovery Time, Reset to Clock

0.5 0.5 ns

(Figure 2)

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

EXPANDED LOGIC DIAGRAM