Jz4755_ds
Jz4755
Multimedia Application Processor Data Sheet
Release Date: Jul. 07, 2009
Jz4755 Multimedia Application Processor
Data Sheet
Copyright ? Ingenic Semiconductor Co., Ltd. 2009. All rights reserved.
Release history
Date Revision Change
Mar. 2009 0.1 First version
May 2009 0.2 CODEC add cap-less
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the usage, or intellectual property right infringement except as provided for by Ingenic Terms and Conditions of Sale.
Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment.
All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice. Anyone relying on this documentation should contact Ingenicfor the current documentation and errata.
Ingenic Semiconductor Co., Ltd.
Room 108, Building A, Information Center, Zhongguancun Software Park
8 Dongbeiwang West Road, Haidian District, Beijing, China,
Tel: 86-10-82826661
Fax: 86-10-82825845
Http: //https://www.wendangku.net/doc/808205243.html,
Content Content
1Overview (1)
1.1Block Diagram (2)
1.2Features (3)
1.2.1CPU core (3)
1.2.2VPU core (3)
1.2.3Memory sub-system (3)
1.2.4Clock generation and power management (4)
1.2.5Audio/Video Interface (4)
1.2.6On-chip peripherals (5)
1.3Characteristic (8)
2Packaging and Pinout Information (9)
2.1Overview (9)
2.2Jz4755 Package (10)
2.3Pin Description [1][2] (12)
2.3.1Pin for parallel interfaces (12)
2.3.2Pin for serial interfaces (17)
2.3.3Pin for system (18)
2.3.4Pin for analog interfaces and corresponding power/ground (19)
2.3.5Pin for IO and core power/ground (21)
3Electrical Specifications (22)
3.1Absolute Maximum Ratings (22)
3.2Recommended operating conditions (23)
3.3DC Specifications (25)
3.4Power On, Reset and BOOT (27)
3.4.1Power-On Timing (27)
3.4.2Reset procedure (28)
3.4.3BOOT (29)
Content
Overview 1 Overview
Jz4755 is a multimedia application processor targeting for multimedia rich and mobile devices like PMP, mobile digital TV, and GPS. This SOC introduces innovative dual-core architecture to fulfill both high performance mobile computing and high quality video decoding requirements addressed by mobile multimedia devices.
The CPU (Central Processing Unit) core, equipped with 16K instruction cache and 16K data cache operating at 400MHz, and full feature MMU function performs OS related tasks. At the heart of the CPU core is XBurst processor engine. XBurst is an industry leading microprocessor core which delivers superior high performance and best-in-class low power consumption.
The VPU (Video Processing Unit) core is powered with another XBurst processor engine. The SIMD instruction set implemented by XBurst engine, in together with the on chip video accelerating engine and post processing unit, delivers doubled video performance comparing with the single core implementation.
The memory interface supports a variety of memory types that allow flexible design requirements, including glueless connection to SLC NAND flash memory or 4-bit/8-bit/12-bit ECC MLC NAND flash memory for cost sensitive applications.
On-chip modules such as LCD controller, audio CODEC, multi-channel SAR-ADC, AC97/I2S controller and camera interface offer designers a rich suite of peripherals for multimedia application. TV encoder unit and 3 channels 10-bits DACs provide composite/S-video/component TV signal output in PAL or NTSC format. In addition, XVGA output up to 1024x768 is provided. WLAN, Bluetooth and expansion options are supported through high-speed SPI and MMC/SD/SDIO host controllers. The TS (Transport stream) interface provides enough bandwidth to connect to an external mobile digital TV demodulator. Other peripherals such as USB 2.0 device, UART and SPI as well as general system resources provide enough computing and connectivity capability for many applications.
Overview
1.1 Block Diagram Array
Figure 1-1 Jz4755 Diagram
Overview 1.2 Features
1.2.1 CPU core
? XBurst CPU
― XBurst?RISC instruction set to support Linux and WinCE
― XBurst?SIMD instruction set to support multimedia acceleration
― XBurst?8-stage pipeline micro-architecture up to 360MHz
? MMU
―32-entry dual-pages joint-TLB
― 4 entry Instruction TLB
― 4 entry data TLB
? L1 Cache
―16K instruction cache
― 16K data cache
?Hardware debug support
?16kB tight coupled memory
1.2.2 VPU core
?XBurst CPU for video processing
― XBurst?RISC instruction set to support Linux and WinCE
― XBurst?SIMD instruction set to support multimedia acceleration
― XBurst?8-stage pipeline micro-architecture up to 360MHz
?Video acceleration engine
― Motion compensation
― Motion estimation
― De-block
―DCT/IDCT for 4x4 block
?32kB tight coupled memory
1.2.3 Memory sub-system
?NAND Flash interface
―Support 4-bit/8-bit/12-bit MLC NAND as well as SLC NAND
―Support all 8-bit/16-bit NAND Flash devices regardless of density and organization
―Support automatic boot up from NAND Flash devices
? Synchronous DRAM Interface
―Standard SDRAM and Mobile SDRAM
―Programmable size and base address
―32-bit or 16-bit data bus width
― Multiplexes row/column addresses according to SDRAM capacity
―Two-bank or four-bank SDRAM is supported
―Supports auto-refresh and self-refresh functions
―Supports power-down mode to minimize the power consumption of SDRAM
Overview
― Supports page mode
― 1 Chip select
Access Controller
? Direct Memory
―Eight independent DMA channels
― Descriptor supported
―Transfer data units: 8-bit, 16-bit, 32-bit, 16-byte or 32-byte
―Transfer requests can be: auto-request within DMA; and on-chip peripheral module request ―Interrupt on transfer completion or transfer error
―Supports two transfer modes: single mode or block mode
?8kB Boot ROM memory
?The Jz4755 processor system supports little endian only
1.2.4 Clock generation and power management
―On-chip oscillator circuit for an 32768Hz clock and an 24MHz clock
―On-chip phase-locked loops (PLL) with programmable multiple-ratio. Internal counter are used to ensure PLL stabilize time
―PLL on/off is programmable by software
―ICLK, PCLK, HCLK, HHCLK, MCLK and LCLK frequency can be changed separately for software by setting division ratio
―Supports six low-power modes and function: NORMAL mode; DOZE mode; IDLE mode;
SLEEP mode; HIBERNATE mode; and MODULE-STOP function.
1.2.5 Audio/Video Interface
? AC97/I2S controller
―Supports 8, 16, 18, 20 and 24 bit for sample for AC-link and I2S/MSB-Justified format
―DMA transfer mode support
―Support variable sample rate mode for AC-link format
―Power down mode and two wake-up mode support for AC-link format
―Programmable Interrupt function support
―Support the on-chip CODEC
―Support off-chip CODEC
?On-chip audio CODEC
―24-bit DAC, SNR: 90dB
―24-bit ADC, SNR: 85dB
― Sample rate: 8/9.6/11.025/12/16/22.05/24/32/44.1/48/96kHz
―L/R channels line input
― MIC input
―L/R channels headphone output amplifier support up to 16ohm load
―Capacitor-coupled or capacitor-less
?Camera interface module
―Input image size up to 4096×4096 pixels
Overview
―Supports CCIR656 data format
―Bayer RGB, YCbCr 4:2:2 and YCbCr 4:4:4 data format
―32×32 image data receive FIFO with DMA support
? LCD controller
―Single-panel display in active mode, and single- or dual-panel displays in passive mode
―2, 4, 16 grayscales and up to 4096 colors in STN mode
―2, 4, 16, 256, 4K, 32K, 64K, 256K and 16M colors in TFT mode
―24-bit data bus
―Support 1,2,4,8 pins STN panel, 16bit, 18bit and 24bit TFT and 8bit I/F TFT
―Display size up to 1280×1024 pixels
― 256×16 bits internal palette RAM
―Support ITU601/656 data format
―Support smart LCD (SRAM-like interface LCD module)
―Support delta RGB
―One single color background and two foreground OSD
? TV Encoder
―Support NTSC or PAL
―Support CVBS or S-video or Component signals
― 3 channel 10 bits DAC
?Image post processor
― Video frame resize
―Color space conversion: 420/444/422 YUV to RGB convert
1.2.6 On-chip peripherals
?General-Purpose I/O ports
―Total GPIO pin number is 124
―Each pin can be configured as general-purpose input or output or multiplexed with internal chip functions
―Each pin can act as a interrupt source and has configurable rising/falling edge or high/low level detect manner, and can be masked independently
―Each pin can be configured as open-drain when output
―Each pin can be configured as internal resistor pull-up
? RTC (Real Time Clock)
―32-bit second counter
―1Hz from 32768hz
― Alarm interrupt
― Independent power
― A 32-bits scratch register used to indicate whether power down happens for RTC power
? Interrupt controller
―Total 32 maskable interrupt sources from on-chip peripherals and external request through GPIO ports
―Interrupt source and pending registers for software handling
―Unmasked interrupts can wake up the chip in sleep or standby mode
Overview
? OS Timer
― One channel
―32-bit counter and 32-bit compare register
―Support interrupt generation when the counter matches the compare register
―Three clock sources: RTCLK (real time clock), EXCLK (ext ernal clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
?Timer and counter unit with PWM output
―Provide six separate channels
―16-bit A counter and 16-bit B counter with auto-reload function every channel
―Support interrupt generation when the A counter underflows
―Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected ―Four PWM outputs
? Watchdog timer
―16-bit counter in RTC clock with 1, 4, 16, 64, 256 and 1024 clock dividing selected
―Generate power-on reset
?I2C bus interface
―Only supports single master mode
―Supports I2C standard-mode and F/S-mode up to 400 kHz
―Double-buffered for receiver and transmitter
―Supports general call address and START byte format after START condition
? Synchronous serial interface
―Up to 50MHz speed
―Supports three formats: TI’s SSP, National Microwire, and Motorola’s SPI
―Configurable 2 - 17 (or multiples of them) bits data transfer
― Full-duplex/transmit-only/receive-only operation
―Supports normal transfer mode or Interval transfer mode
―Programmable transfer order: MSB first or LSB first
―17-bit width, 128-level deep transmit-FIFO and receive-FIFO
―Programmable divider/prescaler for SSI clock
―Back-to-back character transmission/reception mode
? UART
―5, 6, 7 or 8 data bit operation with 1 or 1.5 or 2 stop bits, programmable parity (even, odd, or none)
―32x8bit FIFO for transmit and 32x11bit FIFO for receive data
―Interrupt support for transmit, receive (data ready or timeout), and line status
―Supports DMA transfer mode
―Provide complete serial port signal for modem control functions
―Support slow infrared asynchronous interface (IrDA)
―IrDA function up to 115200bps baudrate
―UART function up to 3.7Mbps baudrate
―Hardware flow control
?USB 2.0 device interface
Overview
―Compliant with USB protocol revision 2.0
―High speed and full speed supported
―Embedded USB 2.0 PHY
?Two MMC/SD/SDIO controllers (MSC0, MSC1)
―Support automatic boot up from MSC0, which has 4-bit data bus
―MSC1 with 4-bit data bus
―Compliant with “The MultiMediaCard System Specification version 4.2”
―Compliant with “SD Memory Card Specification version 2.0” and “SDIO Card Specification version 1.0” with 1 command channel and 4 data channels
―Up to 320 Mbps data rate in MSC0
―Up to 320 Mbps data rate in MSC1
―Supports up to 10 cards (including one SD card)
―Maskable hardware interrupt for SD I/O interrupt, internal status, and FIFO status
? SADC
―12-bit, 2Mbps, SNR@500kHz is 61dB, THD@500kHz is -71dB
―XP/XN, YP/YN inputs for touch screen
―Battery voltage input
― 1 generic input channel
?Transport stream slave interface
―8-bit or 1-bit data bus selectable
―Support PID filtering
Overview
1.3 Characteristic
Item Characteristic
Process Technology 0.16um CMOS
Power supply voltage I/O: 3.3 ± 0.3V
Core: 1.8 ± 0.2
Package LQFP176, 20mm x 20mm x 1.4mm, 0.4mm pitch Operating frequency 400MHz
Packaging and Pinout Information 2 Packaging and Pinout Information
2.1 Overview
Jz4755’s package is LQFP176, which is 20mm x 20mm x 1.4mm outline, 0.4mm pitch, show in “2.2 Jz4755 Package”.
The detailed pin description is listed in Table 2-1 ~ Table 2-16.
Packaging and Pinout Information 2.2 Jz4755 Package
Packaging and Pinout Information
Packaging and Pinout Information
2.3 Pin Description [1][2]
2.3.1 Pin for parallel interfaces
Table 2-1 EMC SDRAM Pins (57; all GPIO shared)
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
D0 PA0 IO
IO
6
12mA,
pullup-pe
D0: SDRAM data bus bit 0, NAND/NOR/SRAM data bus bit 0
PA0: GPIO group A bit 0
VDDIO
D1 PA1 IO
IO
7
12mA,
pullup-pe
D1: SDRAM data bus bit 1, NAND/NOR/SRAM data bus bit 1
PA1: GPIO group A bit 1
VDDIO
D2 PA2 IO
IO
8
12mA,
pullup-pe
D2: SDRAM data bus bit 2, NAND/NOR/SRAM data bus bit 2
PA2: GPIO group A bit 2
VDDIO
D3 PA3 IO
IO
9
12mA,
pullup-pe
D3: SDRAM data bus bit 3, NAND/NOR/SRAM data bus bit 3
PA3: GPIO group A bit 3
VDDIO
D4 PA4 IO
IO
10
12mA,
pullup-pe
D4: SDRAM data bus bit 4, NAND/NOR/SRAM data bus bit 4
PA4: GPIO group A bit 4
VDDIO
D5 PA5 IO
IO
11
12mA,
pullup-pe
D5: SDRAM data bus bit 5, NAND/NOR/SRAM data bus bit 5
PA5: GPIO group A bit 5
VDDIO
D6 PA6 IO
IO
12
12mA,
pullup-pe
D6: SDRAM data bus bit 6, NAND/NOR/SRAM data bus bit 6
PA6: GPIO group A bit 6
VDDIO
D7 PA7 IO
IO
13
12mA,
pullup-pe
D7: SDRAM data bus bit 7, NAND/NOR/SRAM data bus bit 7
PA7: GPIO group A bit 7
VDDIO
D8 PA8 IO
IO
172
12mA,
pullup-pe
D8: SDRAM data bus bit 8, NAND/NOR/SRAM data bus bit 8
PA8: GPIO group A bit 8
VDDIO
D9 PA9 IO
IO
173
12mA,
pullup-pe
D9: SDRAM data bus bit 9, NAND/NOR/SRAM data bus bit 9
PA9: GPIO group A bit 9
VDDIO
D10 PA10 IO
IO
174
12mA,
pullup-pe
D10: SDRAM data bus bit 10, NAND/NOR/SRAM data bus bit 10
PA10: GPIO group A bit 10
VDDIO
D11 PA11 IO
IO
175
12mA,
pullup-pe
D11: SDRAM data bus bit 11, NAND/NOR/SRAM data bus bit 11
PA11: GPIO group A bit 11
VDDIO
D12 PA12 IO
IO
176
12mA,
pullup-pe
D12: SDRAM data bus bit 12, NAND/NOR/SRAM data bus bit 12
PA12: GPIO group A bit 12
VDDIO
D13 PA13 IO
IO
1
12mA,
pullup-pe
D13: SDRAM data bus bit 13, NAND/NOR/SRAM data bus bit 13
PA13: GPIO group A bit 13
VDDIO
D14 PA14 IO
IO
2
12mA,
pullup-pe
D14: SDRAM data bus bit 14, NAND/NOR/SRAM data bus bit 14
PA14: GPIO group A bit 14
VDDIO
D15 PA15 IO
IO
3
12mA,
pullup-pe
D15: SDRAM data bus bit 15, NAND/NOR/SRAM data bus bit 15
PA15: GPIO group A bit 15
VDDIO
D16 PA16 IO
IO
134
8mA,
pullup-pe
D16: SDRAM data bus bit 16, NAND/NOR/SRAM data bus bit 16
PA16: GPIO group A bit 16
VDDIO
D17 PA17 IO
IO
135
8mA,
pullup-pe
D17: SDRAM data bus bit 17, NAND/NOR/SRAM data bus bit 17
PA17: GPIO group A bit 17
VDDIO
D18 PA18 IO
IO
136
8mA,
pullup-pe
D18: SDRAM data bus bit 18, NAND/NOR/SRAM data bus bit 18
PA18: GPIO group A bit 18
VDDIO
D19 PA19 IO
IO
137
8mA,
pullup-pe
D19: SDRAM data bus bit 19, NAND/NOR/SRAM data bus bit 19
PA19: GPIO group A bit 19
VDDIO
D20 PA20 IO
IO
138
8mA,
pullup-pe
D20: SDRAM data bus bit 20, NAND/NOR/SRAM data bus bit 20
PA20: GPIO group A bit 20
VDDIO
D21 PA21 IO
IO
139
8mA,
pullup-pe
D21: SDRAM data bus bit 21, NAND/NOR/SRAM data bus bit 21
PA21: GPIO group A bit 21
VDDIO
D22 PA22 IO
IO
140
8mA,
pullup-pe
D22: SDRAM data bus bit 22, NAND/NOR/SRAM data bus bit 22
PA22: GPIO group A bit 22
VDDIO
D23 PA23 IO
IO
141
8mA,
pullup-pe
D23: SDRAM data bus bit 23, NAND/NOR/SRAM data bus bit 23
PA23: GPIO group A bit 23
VDDIO
Packaging and Pinout Information
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
D24 PA24 IO
IO
125
8mA,
pullup-pe
D24: SDRAM data bus bit 24, NAND/NOR/SRAM data bus bit 24
PA24: GPIO group A bit 24
VDDIO
D25 PA25 IO
IO
126
8mA,
pullup-pe
D25: SDRAM data bus bit 25, NAND/NOR/SRAM data bus bit 25
PA25: GPIO group A bit 25
VDDIO
D26 PA26 IO
IO
127
8mA,
pullup-pe
D26: SDRAM data bus bit 26, NAND/NOR/SRAM data bus bit 26
PA26: GPIO group A bit 26
VDDIO
D27 PA27 IO
IO
128
8mA,
pullup-pe
D27: SDRAM data bus bit 27, NAND/NOR/SRAM data bus bit 27
PA27: GPIO group A bit 27
VDDIO
D28 PA28 IO
IO
129
8mA,
pullup-pe
D28: SDRAM data bus bit 28, NAND/NOR/SRAM data bus bit 28
PA28: GPIO group A bit 28
VDDIO
D29 PA29 IO
IO
130
8mA,
pullup-pe
D29: SDRAM data bus bit 29, NAND/NOR/SRAM data bus bit 29
PA29: GPIO group A bit 29
VDDIO
D30 PA30 IO
IO
131
8mA,
pullup-pe
D30: SDRAM data bus bit 30, NAND/NOR/SRAM data bus bit 30
PA30: GPIO group A bit 30
VDDIO
D31 PA31 IO
IO
132
8mA,
pullup-pe
D31: SDRAM data bus bit 31, NAND/NOR/SRAM data bus bit 31
PA31: GPIO group A bit 31
VDDIO
A0 PB0 O
IO
151
12mA,
pullup-pe
A0: SDRAM address bus bit 0, NOR/SRAM address bus bit 0
PB0: GPIO group B bit 0
VDDIO
A1 PB1 O
IO
150
12mA,
pullup-pe
A1: SDRAM address bus bit 1, NOR/SRAM address bus bit 1
PB1: GPIO group B bit 1
VDDIO
A2 PB2 O
IO
149
12mA,
pullup-pe
A2: SDRAM address bus bit 2, NOR/SRAM address bus bit 2
PB2: GPIO group B bit 2
VDDIO
A3 PB3 O
IO
148
12mA,
pullup-pe
A3: SDRAM address bus bit 3, NOR/SRAM address bus bit 3
PB3: GPIO group B bit 3
VDDIO
A4 PB4 O
IO
170
12mA,
pullup-pe
A4: SDRAM address bus bit 4, NOR/SRAM address bus bit 4
PB4: GPIO group B bit 4
VDDIO
A5 PB5 O
IO
169
12mA,
pullup-pe
A5: SDRAM address bus bit 5, NOR/SRAM address bus bit 5
PB5: GPIO group B bit 5
VDDIO
A6 PB6 O
IO
168
12mA,
pullup-pe
A6: SDRAM address bus bit 6, NOR/SRAM address bus bit 6
PB6: GPIO group B bit 6
VDDIO
A7 PB7 O
IO
167
12mA,
pullup-pe
A7: SDRAM address bus bit 7, NOR/SRAM address bus bit 7
PB7: GPIO group B bit 7
VDDIO
A8 PB8 O
IO
166
12mA,
pullup-pe
A8: SDRAM address bus bit 8, NOR/SRAM address bus bit 8
PB8: GPIO group B bit 8
VDDIO
A9 PB9 O
IO
165
12mA,
pullup-pe
A9: SDRAM address bus bit 9, NOR/SRAM address bus bit 9
PB9: GPIO group B bit 9
VDDIO
A10 PB10 O
IO
152
12mA,
pullup-pe
A10: SDRAM address bus bit 10, NOR/SRAM address bus bit 10
PB10: GPIO group B bit 10
VDDIO
A11 PB11 O
IO
164
12mA,
pullup-pe
A11: SDRAM address bus bit 11, NOR/SRAM address bus bit 11
PB11: GPIO group B bit 11
VDDIO
A12 PB12 O
IO
163
12mA,
pullup-pe
A12: SDRAM address bus bit 12, NOR/SRAM address bus bit 12
PB12: GPIO group B bit 12
VDDIO
A13 PB13 O
IO
154
12mA,
pullup-pe
A13: SDRAM address bus bit 13, NOR/SRAM address bus bit 13
PB13: GPIO group B bit 13
VDDIO
A14 PB14 O
IO
153
12mA,
pullup-pe
A14: SDRAM address bus bit 14, NOR/SRAM address bus bit 14
PB14: GPIO group B bit 14
VDDIO
DCS0_ PB16 O
IO
155
8mA,
pullup-pe
DCS0_: SDRAM chip select 0
PB16: GPIO group B bit 16
VDDIO
RAS_ PB17 O
IO
156
8mA,
pullup-pe
RAS_: SDRAM row address strobe
PB17: GPIO group B bit 17
VDDIO
CAS_ PB18 O
IO
157
8mA,
pullup-pe
CAS_: SDRAM column address strobe
PB18: GPIO group B bit 18
VDDIO
SDWE_ & BUFD_ PB19 O
IO
158
12mA,
pullup-pe
SDWE_: SDRAM write enable
BUFD_: Select CPU to SRAM chip direction in data bi-direction buffer
PB19: GPIO group B bit 19
VDDIO
WE0_ PB20 O
IO
5
8mA,
pullup-pe
WE0_: SDRAM/NOR/SRAM byte 0 write enable
PB20: GPIO group B bit 20
VDDIO
Packaging and Pinout Information
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
WE1_ PB21 O
IO
171
8mA,
pullup-pe
WE1_: SDRAM/NOR/SRAM byte 1 write enable
PB21: GPIO group B bit 21
VDDIO
WE2_ PB22 O
IO
147
8mA,
pullup-pe
WE2_: SDRAM/NOR/SRAM byte 2 write enable
PB22: GPIO group B bit 22
VDDIO
WE3_ PB23 O
IO
133
8mA,
pullup-pe
WE3_: SDRAM/NOR/SRAM byte 3 write enable
PB23: GPIO group B bit 23
VDDIO
CKO PB24 O
IO
159
12mA,
pullup-pe
CKO: SDRAM clock
PB24: GPIO group B bit 24
VDDIO
CKE PB25
O
IO
162
8mA,
pullup-pe
CKE: SDRAM clock enable
PB25: GPIO group B bit 25
VDDIO Table 2-2 EMC Static Memory, MSC 0 and TSSI data Pins (9; all GPIO shared)
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
A15/CL MSC0_CLK PB15 O
O
IO
15
2mA,
pullup-pe
A15/CL: NOR/SRAM address bit 15, used as NAND flash command
latch
MSC0_CLK: MSC (MMC/SD) 0 clock output
PB15: GPIO group B bit 15
VDDIO
A16/AL MSC0_CMD PC16 O
IO
IO
14
2mA,
pullup-pe
A16/AL: NOR/SRAM address bit 16, used as NAND flash address latch
MSC0_CMD: MSC (MMC/SD) 0 command
PC16: GPIO group C bit 16
VDDIO
A17
MSC0_D3 PC17 O
IO
IO
17
2mA,
pullup-pe
A17: NOR/SRAM address bit 17, used as NAND CS2_
MSC0_D3: MSC (MMC/SD) 0 data bit 3
PC17: GPIO group C bit 17
VDDIO
CS1_ PC21 O
IO
20
2mA,
pullup-pe
CS1_: NAND/NOR/SRAM chip select 1
PC21: GPIO group C bit 21
VDDIO
CS3_ PC23 O
IO
145
4mA,
pullup-pe
CS3_: NAND/NOR/SRAM chip select 3
PC23: GPIO group C bit 23
VDDIO
CS4_ PC24 O
IO
143
4mA,
pullup-pe
CS4_: NAND/NOR/SRAM chip select 4
PC24: GPIO group C bit 24
VDDIO
PC27/FRB MSC0_D2 IO
IO
19
2mA,
pullup-pe
PC27/FRB: GPIO group C bit 27, used for NAND FRB (ready/busy)
MSC0_D2: MSC (MMC/SD) 0 data bit 2
VDDIO
FRE_ MSC0_D0 PC28 O
IO
IO
18
2mA,
pullup-pe
FRE_: NAND read enable
MSC0_D0: MSC (MMC/SD) 0 data bit 0
PC28: GPIO group C bit 28
VDDIO
FWE_ MSC0_D1 PC29 O
IO
IO
16
2mA,
pullup-pe
FWE_: NAND write enable
MSC0_D1: MSC (MMC/SD) 0 data bit 1
PC29: GPIO group C bit 29
VDDIO Table 2-3 LCDC Pins (28; all GPIO shared)
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
LCD_B0 PD26 O
IO
96
4mA,
pullup-pe
LCD_B0: LCD blue data bit 0
PD26: GPIO group D bit 26
VDDIO
LCD_REV LCD_B1 PD25 O
O
IO
99
4mA,
pullup-pe
LCD_REV: LCD REV output for special TFT
LCD_B1: Blue data bit 1, used in 24-bit data bus
PD25: GPIO group D bit 25
VDDIO
LCD_B2 PD0 O
IO
123
4mA,
pullup-pe
LCD_B2: LCD blue data bit 2
PD0: GPIO group D bit 0
VDDIO
LCD_B3 PD1 O
IO
122
4mA,
pullup-pe
LCD_B3: LCD blue data bit 3
PD1: GPIO group D bit 1
VDDIO
LCD_B4 PD2 O
IO
121
4mA,
pullup-pe
LCD_B4: LCD blue data bit 4
PD2: GPIO group D bit 2
VDDIO
Packaging and Pinout Information
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
LCD_B5 PD3 O
IO
120
4mA,
pullup-pe
LCD_B5: LCD blue data bit 5
PD3: GPIO group D bit 3
VDDIO
LCD_B6 PD4 O
IO
119
4mA,
pullup-pe
LCD_B6: LCD blue data bit 6
PD4: GPIO group D bit 4
VDDIO
LCD_B7 PD5 O
IO
118
4mA,
pullup-pe
LCD_B7: LCD blue data bit 7
PD5: GPIO group D bit 5
VDDIO
LCD_SPL LCD_G0 PD23 O
O
IO
97
4mA,
pullup-pe
LCD_SPL: LCD SPL output
LCD_G0: Green data bit 0, used in 24-bit data bus
PD23: GPIO group D bit 23
VDDIO
LCD_PS LCD_G1 PD24 O
O
IO
100
4mA,
pullup-pe
LCD_PS: LCD PS output for special TFT
LCD_G1: Green data bit 1, used in 24-bit data bus
PD24: GPIO group D bit 24
VDDIO
LCD_G2 PD6 O
IO
117
4mA,
pullup-pe
LCD_G2: LCD green data bit 2
PD6: GPIO group D bit 6
VDDIO
LCD_G3 PD7 O
IO
116
4mA,
pullup-pe
LCD_G3: LCD green data bit 3
PD7: GPIO group D bit 7
VDDIO
LCD_G4 PD8 O
IO
115
4mA,
pullup-pe
LCD_G4: LCD green data bit 4
PD8: GPIO group D bit 8
VDDIO
LCD_G5 PD9 O
IO
114
4mA,
pullup-pe
LCD_G5: LCD green data bit 5
PD9: GPIO group D bit 9
VDDIO
LCD_G6 PD10 O
IO
113
4mA,
pullup-pe
LCD_G6: LCD green data bit 6
PD10: GPIO group D bit 10
VDDIO
LCD_G7 PD11 O
IO
112
4mA,
pullup-pe
LCD_G7: LCD green data bit 7
PD11: GPIO group D bit 11
VDDIO
LCD_R0 PD27 O
IO
95
4mA,
pullup-pe
LCD_R0: LCD red data bit 0
PD27: GPIO group D bit 27
VDDIO
LCD_CLS LCD_R1 PD22 O
O
IO
98
4mA,
pullup-pe
LCD_CLS: LCD CLS output
LCD_R1: Red data bit 1, used in 24-bit data bus
PD22: GPIO group D bit 22
VDDIO
LCD_R2 PD12 O
IO
111
4mA,
pullup-pe
LCD_R2: LCD red data bit 2
PD12: GPIO group D bit 12
VDDIO
LCD_R3 PD13 O
IO
110
4mA,
pullup-pe
LCD_R3: LCD red data bit 3
PD13: GPIO group D bit 13
VDDIO
LCD_R4 PD14 O
IO
109
4mA,
pullup-pe
LCD_R4: LCD red data bit 4
PD14: GPIO group D bit 14
VDDIO
LCD_R5 PD15 O
IO
108
4mA,
pullup-pe
LCD_R5: LCD red data bit 5
PD15: GPIO group D bit 15
VDDIO
LCD_R6 PD16 O
IO
107
4mA,
pullup-pe
LCD_R6: LCD red data bit 6
PD16: GPIO group D bit 16
VDDIO
LCD_R7 PD17 O
IO
106
4mA,
pullup-pe
LCD_R7: LCD red data bit 7
PD17: GPIO group D bit 17
VDDIO
LCD_PCLK PD18 IO
IO
124
8mA,
pullup-pe
LCD_PCLK: LCD pixel clock
PD18: GPIO group D bit 18
VDDIO
LCD_HSYN PD19 IO
IO
102
4mA,
pullup-pe
LCD_HSYN: LCD line clock/horizonal sync
PD19: GPIO group D bit 19
VDDIO
LCD_VSYN PD20 IO
IO
101
4mA,
pullup-pe
LCD_VSYN: LCD frame clock/vertical sync
PD20: GPIO group D bit 20
VDDIO
LCD_DE PD21 O
IO
103
4mA,
pullup-pe
LCD_DE: STN AC bias drive/non-STN data enable
PD21: GPIO group D bit 21
VDDIO Table 2-4 CIM and TSSI Pins (12; all GPIO shared)
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
CIM_D0 TSDI0 PE0
I
I
IO
24
2mA,
pullup-pe
CIM_D0: CIM data input bit 0
TSDI0: TS slave interface input data bus
PE0: GPIO group E bit 0
VDDIO
Packaging and Pinout Information
Pin Names IO
Pin
Location
IO Cell
Char.
Pin Description Power
CIM_D1 TSDI1 PE1
I
I
IO
25
2mA,
pullup-pe
CIM_D1: CIM data input bit 1
TSDI1: TS slave interface input data bus
PE1: GPIO group E bit 1
VDDIO
CIM_D2 TSDI2 PE2
I
I
IO
26
2mA,
pullup-pe
CIM_D2: CIM data input bit 2
TSDI2: TS slave interface input data bus
PE2: GPIO group E bit 2
VDDIO
CIM_D3 TSDI3 PE3
I
I
IO
27
2mA,
pullup-pe
CIM_D3: CIM data input bit 3
TSDI3: TS slave interface input data bus
PE3: GPIO group E bit 3
VDDIO
CIM_D4 TSDI4 PE4
I
I
IO
29
2mA,
pullup-pe
CIM_D4: CIM data input bit 4
TSDI4: TS slave interface input data bus
PE4: GPIO group E bit 4
VDDIO
CIM_D5 TSDI5 PE5
I
I
IO
30
2mA,
pullup-pe
CIM_D5: CIM data input bit 5
TSDI5: TS slave interface input data bus
PE5: GPIO group E bit 5
VDDIO
CIM_D6 TSDI6 PE6
I
I
IO
31
2mA,
pullup-pe
CIM_D6: CIM data input bit 6
TSDI6: TS slave interface input data bus
PE6: GPIO group E bit 6
VDDIO
CIM_D7 TSDI7 PE7
I
I
IO
32
2mA,
pullup-pe
CIM_D7: CIM data input bit 7
TSDI7: TS slave interface input data bus
PE7: GPIO group E bit 7
VDDIO
CIM_MCLK TSFAIL
PE8 O
37
4mA,
pullup-pe
CIM_MCLK: CIM master clock output
TSFAIL: TS interface error package indicator input
PE8: GPIO group E bit 8
VDDIO
CIM_PCLK TSCLK
PE9
I
I
IO
34
2mA,
pullup-pe
CIM_PCLK: CIM pixel clock input
TSCLK: TS interface clock input
PE9: GPIO group E bit 9
VDDIO
CIM_VSYN TSSTR
PE10
I
I
IO
35
2mA,
pullup-pe
CIM_VSYN: CIM VSYNC input
TSSTR: TS interface frame start input
PE10: GPIO group E bit 10
VDDIO
CIM_HSYN TSFRM
PE11
I
I
IO
36
2mA,
pullup-pe
CIM_HSYN: CIM HSYNC input
TSFRM: TS interface frame valid input
PE11: GPIO group E bit 11
VDDIO