亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计(论文)
第Z 7卷第5期Z 006年5月
半导体学报
CH I NESE J OURNAL OF SEM I CONDUCTORS
Vol .Z 7No .5
M a y Z 006
T Corr es P ondi n g aut hor .Email :ki n g a PP l e ＠chi naacc .co m
Recei ved 8D ece mber Z 005
r evised manuscri P t r ecei ved 7Januar Y Z 006④Z 006Chi nese I nstit ut e of E
l ectr onics D es i g ni n g Leaka g e-tolerant and Noise-I mmune Enhanced LoW
PoWer W i de OR Do m i nos i n S ub-70n m CMO S technol o g ies
Guo Baozen g 1 Gon g Na 1
T and W an g Ji nhui Z
(1Colle g e o f Elect ronic and I n f or m ation En g ineerin g ~ebei uniuersit $ Bao din g 07100Z China )
(Z Laborat or $o f VLSI S $ste m s Colle g e o f Elect ronic I n f or m ation Cont rol En g ineerin g
Bei j in g uniuersit $o f T ec hnol o g$ Bei j in g 1000Z Z China )
Abstract :TWo ne W circuit t echni ]ues t o su PP ress leaka g e currents and enhance no ise i mmunit Y While decreasi n g t he acti ve P oWer are P r o P osed .E i g ht-i n P ut OR g at e circuits constr uct ed W it h t hese t echni ]ues are si mul at ed u-si n g 45n m BSI M
4SPI CE models i n H SPI CE.The si mul ati on results shoW t hat t he P r o P osed circuits ef f ecti vel Y l oWer t he acti ve P oWer
reduce t he t ot al leaka g e current and enhance s P eed under si m il ar no ise i mmunit Y condi-ti ons .The acti ve P oWer of t he t Wo P r o P osed circuits can be reduced b Y u P t o 8.8%and 11.8%While enhanci n g
t he s P eed b Y 9.5%and 13.7%as co m P ared t o dual V t do m
i no OR g at es W it h no g ati n g st a g e .A t t he sa m e ti m e t he t ot al leaka g e currents are also reduced b Y u P t o 80.8%and 8Z.4% res P ective l Y .B ased on t he si m ulation results t he st ate of t he evaluation node is also d iscussed t o reduce t he t o t al leaka g e currents of dual V t do m i no s .K e y Words :l oW P oWer 3leaka g e current 3OR do m i nos 3no ise i mmunit Y EEACC :1130B 31Z 65
CLC nu mber :TN 4Docu m ent code :A Article I D :0Z 53-4177(Z 006)05-0804-08
l Introducti on
W i de OR do m i nos or si m il ar str uct ures are co mmonl y e m p l o y ed i n re g i st er and cache arra y
bit li ne desi g n [1]
.A s t echnol o gy i s scali n g do Wn su pp l y volt a g es must be reduced t o kee p d y na m i c
p o Wer at acce p t abl e l evel s
[Z 3
].A t t he sa m e ti m e t he t hreshol d volt a g e (V t )and g at e oxi de t hi ck-ness (
t ox )of transi st ors must be reduced t o ac-co m p an y t he reducti on of t he su pp l y volt a g e t o m eet p erf or m ance re C uire m ents .~o Wever t he sub-t hreshol d l eaka g e and g at e l eaka g e currents i ncrease ex p onenti all y W it h t he scali n g of V t and t ox .W orst of all duri n g t he sl ee p mode When t he circuits are not o p erati n g l eaka g e currents still occur .The Z 001int er nati onal T echnol o gy Road-m a p f or Se m i conduct ors (i TRS )[4]
p redi ct ed t hat b y t he 70n m g enerati on l eaka g e m a y constit ut e as much as 50p ercent of t he t ot al p o Wer consu m p -ti on .A t t he sa m e ti m e t he i ncreasi n g of sub-t hreshol d l eaka g e currents and g at e l eaka g e cur-rents W it h t he scali n g of t echnol o gy al so de g rades t he noi se i mmunit y of W i de OR do m i no g at es and t he err or-f ree o p erati on of do m i nos has beco m e a
m a or chall en g e [5]
.
Theref ore t here i s a need t o fi nd a Wa y t o re-duce l eaka g e currents and i m p r ove circuit r obust-ness Whil e decreasi n g t he acti ve p o Wer .pri or cir-cuit-l evel a pp r oaches t o l eaka g e p o Wer reducti on and p erf or m ance enhance m ent i ncl ude :bod y -bi as
contr ol [6] i n p ut vect or contr ol [7]
sl ee p tran-si st ors [8]
vari abl e t hreshol d-volt a g e C MOS t ech-ni C ue (
VTC MOS )[9]
and vari abl e su pp l y volt a g es t echni C ue (VS )[10]
.A rchit ect ure-l evel l eaka g e p o Wer reducti on t echni C ues have f ocused p ri m ari-l y on SRA M S [11 1Z ]
.e ach t echni C ue has its share of stren g t hs and Weaknesses and i n t hi s p a p er We f ocus on t he f or m er .W e p r o p ose t Wo ne W W i de OR do m i no circuit t echni C ues and st ud y t heir i m -p act on t he f oll o W i n g desi g n p ara m et ers :t he sub-t hreshol d l eaka g e current g at e l eaka g e current acti ve p o Wer del a y ti m e DC r obust ness and AC noi se m ar g i ns .
2Pro p osed W i de OR do m i nos
A s descri bed i n Sec .1 l eaka g e currents have beco m e an i m p ort ant i ssue t hreat eni n g t he p er-f or m ance of do m i no circuits es p eci all y f or W i de OR do m i nos .Bot h sub-t hreshol d l eaka g e and g at e
第5期Guo Baozen g et al=D esi g ni n g Leaka g e-T ol erant and Noise-i mmune enhanced Lo W po Wer W i de-
l eaka g e currents i ncrease ex p onenti all y W it h t he scali n g of V t and t ox as sho Wn i n F i g.1.A t t he sa m e ti m e t he ri si n g l eaka g e currents de g enerat e t he p erf or m ance of t he circuits event uall y l eadi n g t o f ail ure[5].F i g ure1sho Ws t he nor m ali zed DC r obust ness and AC noi se m ar g i ns of several diff erent fi n-i n OR g ates i n45n m and65n m CMO S technol o gy.O bvi ousl y bot h t he DC robust ness and AC no ise m ar g i ns de g rade W it h t he scali n g of technol-o gy and t he i ncreasi n g of f an-i n nu m ber.
G ate leaka g e current at V g s= V g d=V g b=V dd;Co m p arison of t he DC r obust ness and AC noise m ar g i ns of several diff erent fi n-i n OR g ates i n 45n m and65n m technol o gy The DC r obust ness and AC noise m ar g i ns are nor m alized t o t hose of Z-i n p ut OR do m i nos i n65n m technol o gy res p ecti vel y.
To su pp ress t he sub-t hreshol d l eaka g e cur-rent Whi ch i ncreases W it h t he scali n g of V t t he dual V t t echni C ue Was p r o p osed i n Ref.[13].The t echni C ue o p ti m i zed t he circuit s p eed and l eaka g e currents b y usi n g l o W V t and hi g h V t transi st ors on t he ti m i n g criti cal p at hs and non-criti cal p at hs res p ecti vel y[see F i g.Z].W it h t hi s t echni C ue it i s necessar y t o g at e all t he i niti al i n p uts of t he do m i no g at es t o p l ace t he sl ee p do m i no g at es i nt o a l o W sub-t hreshol d l eaka g e st at e[1314].
F i g.Z N-i n p ut OR do m i no g atesS tandar d OR do m i nos;Dual V t OR do m i nos The hi g h V t transist ors are s y mbolicall y re p resented b y a t hick li ne i n t he channel re g i on.
Obvi ousl y t he dual V t t echni C ue does not t ake t he eff ect of t he g at e l eaka g e current i nt o ac-count.W hen i n p uts are g at ed and t he eval uati on node i s di schar g ed t he sub-t hreshol d l eaka g e cur-rent i s m i ni m i zed.~o Wever t he g at e l eaka g e cur-rent i s f ast beco m i n g a non-ne g li g i bl e co m p onent
508
半导体学报第Z7卷
as t ox i s g etti n g t hi nner.e s p eci all y i n W i de OR do m i nos t he p ull-do Wn n MOS net Wor k p r oduces a si g nifi cant g at e l eaka g e current.Consi deri n g bot h sub-t hreshol d l eaka g e and g at e l eaka g e cur-rents a char g ed eval uati on node W it h l o W i n p uts Was p r o p osed i n Ref.[15]t o l o Wer t he t ot al l eak-a g e currents i n t he sl ee p do m i nos.
Theref ore t he t Wo dual V t t echni C ues de-scri bed i n Ref s.[13]and[15]bot h re C uire i n p ut si g nal g ati n g of t he first st a g e i n do m i no circuits Whi ch i ncreases t he circuit area and d y na m i c p o W-er Whil e de g radi n g t he circuit p erf or m ance.TWo alt er nati ve dual V t t echni C ues t o su pp ress bot h t he sub-t hreshol d l eaka g e and g at e l eaka g e cur-rents Were p r o p osed b y Kan g et al[16].The t Wo versi ons have t he sa m e circuit str uct ure as sho Wn i n F i g.3.in bot h t echni C ues t he dual V t t ech-ni C ue i s a pp li ed t o su pp ress t he sub-t hreshol d l eaka g e current.in additi on t he i n p uts and out-p uts are all set l o W no m att er What t he i n p uts t o t he first do m i no st a g e are and t hus no g at e l eak-a g e current fl o Ws i n t he p ull-do Wn n MOS net Wor k i n t he sl ee p mode and bot h t he sub-t hreshol d l eaka g e current and g at e l eaka g e current are su p-p ressed g reatl y
F i g.3Do m i no circuits p r o p osed b y Kan g[16];
G ate leaka g e current i n dual V t do m i nos and Kan g s do m i-nos
in t hi s p a p er We p resent t Wo ne W versi ons of W i de OR do m i no g at es.The t Wo versi ons have t he sa m e circuit str uct ure as sho Wn i n F i g.4.in our p r o p osed circuits t he l o W s W i n g circuit t ech-ni C ue i s a pp li ed t o t he hi g h fi n-i n OR do m i no g at es t o decrease p o Wer consu m p ti on.A s an at-tracti ve m et hod t o reduce p o Wer consu m p ti on t he l o W s W i n g circuit t echni C ue has been used i n i/O dri vers l on g i nt erconnects and do m i no l o g i c cir-cuits[17].W it h t he l o W s W i n g t echni C ue t he g at e volt a g e of t he kee p er p MOS s W i n g s bet Ween V t p and V dd
60
8
第5期Guo Baozen g et al D esi g ni n g Leaka g e-T ol erant and Noise-i mmune enhanced Lo W po Wer W i de
F i g.4a pr o p osed circuit1The hi g h V t transist ors are s y mbolicall y re p resented b y a t hick li ne i n t he channel
re g i on b C l ock si g nals i n t he first and t he second p r o p osed circuits
The onl y diff erence bet Ween t he t Wo versi ons li es i n t he cl ock si g nal of CLKZ.in t he second p r o p osed circuit CLKZ i s diff erent f r o m CLK i n bot h t he sl ee p mode and acti ve mode see F i g.4 b.in t he sl ee p mode CLKZ i s set hi g h t o re-duce t he g at e l eaka g e current but i n t he acti ve mode CLKZ i s a short durati on p ul se t hat i s l on g enou g h f or t he eval uati on node t o di schar g e but short enou g h t o f urt her reduce t he sub-t hreshol d l eaka g e current t hr ou g h t he l o W V t devi ces i n t he p ull-do Wn n MOS net Wor k.Theref ore W it h t he short durati on CLKZ t he sub-t hreshol d l eaka g e current and p o Wer consu m p ti on are f urt her de-creased[19].S i mul ati ons i n Ref.[19]sho Wed p o-t enti al avera g e p o Wer savi n g s of u p t o Z0When t he short p ul se i s of t he m i ni mu m durati on t hat all o Ws eval uati on.in additi on t he short durati on CLKZ al so i m p r oves t he AC noi se m ar g i ns of t he W i de OR g at es Whi ch W ill be di scussed l at er.
3S i mul ati on results
W e co m p are t he p erf or m ance and p o Wer con-su m p ti on of fi ve8-i n p ut OR g at es usi n g dual V t do m i nos t Wo Kan g s do m i nos and our p r o p osed circuits res p ecti vel y.e ach do m i no g at e dri ves a ca p aciti ve l oad of8f F.~Spi Ce si mul ati on results Were obt ai ned W it h C MOS45n m BS i M4mod-el s[Z0]W it h a p o Wer su pp l y of0.8V.The p ara m e-t ers of t he devi ces are li st ed i n T abl e1.A ll OR g at es Were t ur ned t o o p erat e at a1G~z cl ock f re-C uenc y.
As descri bed i n Sec.Z f or t he second p r o-
T abl e1para m eters of t he devices
pr ocess
V t val ue of f our diff erent devi ces
~i g h V t
n MOS
~i g h V t
p MOS
Lo W V t
n MOS
Lo W V t
p MOS
T e m p erat ure 45n m0.35V0.35V0.Z Z V0.Z Z V110
p osed circuit We t est ed t he short p ul se t echni C ue b y var y i n g t he durati on of CLKZ.The m i ni mu m durati on extract ed Was0.3ns.The n MOS and p MOS i n t he fi ve diff erent OR g at es are t he sa m e si ze.in t he si mul ati on t he g ati n g st a g e of t he dual V t circuits i s ne g l ect ed.
A s f or t he noi se i mmunit y i ssue DC r obust-ness and AC noi se m ar g i ns of OR do m i no g at es are bot h consi dered i n t hi s p a p er.The sa m e noi se si g nal i s cou p l ed t o all of t he i n p uts of t he OR g at es so t hi s sit uati on re p resents t he Worst noi se conditi on[Z1].For t he g at es W it h a SLeep si g nal t he noi se i s al so assu m ed t o cou p l e t he g at es of t he transi st ors contr oll ed b y t he SLeep si g nal. The DC r obust ness crit eri on used here i s si m il ar t o t he crit eri on descri bed i n Ref.[1].A sl o W ra m p noi se si g nal i s si mul at ed as t he DC noi se si g nal. The DC r obust ness i s t he volt a g e a m p lit ude of t he DC noi se si g nal Whi ch p r oduces a si g nal W it h t he sa m e a m p lit ude at t he out p ut of t he OR do m i nos assu m i n g a1G~z cl ock W it h a50dut y c y cl e.in or der t o C uantif y t he AC noi se m ar g i ns t he noi se si g nal i s assu m ed t o be a s C uare Wave W it h450p s durati on.The m axi mu m t ol erabl e noi se a m p lit ude i s defi ned as t he si g nal
a m p lit ude at t he i n p uts i n-duci n g a10-V dd dr o p i n t he volt a g e at t he out-p ut of t he OR g at e.
The del a y i s cal cul at ed f r o m50of t he si g-
708
半导体学报第Z7卷
nal s W i n g a pp li ed at t he i n p uts of t he8-i n p ut OR g at es t o50of t he si g nal s W i n g obser ved at t he out p ut.
The si mul ati on results of t he fi ve8-OR g at es are sho Wn i n F i g s.5and6.The nor m ali zed acti ve p o Wer!del a y ti m e!and noi se i mmunit y are sho Wn i n F i g.5.The l eaka g e charact eri sti cs are sho Wn i n F i g.6.As di scussed i n Sec.Z!t he cont enti on cur-rent of t he l o W volt a g e s W i n g kee p er p MOSi n our p r o p osed circuits i s reduced as co m p ared t o t hat of t he f ull volt a g e s W i n g kee p er i n ot her circuits. Our p r o p osed circuits t heref ore reduce t he acti ve p o Wer and del a y ti m e as co m p ared t o dual V t do m-i nos and Kan g"s do m i nos.A s sho Wn i n F i g.5!t he acti ve p o Wer i s reduced b y11.3and1Z.9i n our t Wo p r o p osed circuits!co m p ared W it h t hat of dual V t do m i nos W it h t he sa m e transi st or si ze #STS$!res p ecti vel y.A t t he sa m e ti m e!our p r o-p osed circuits sho W bett er l eaka g e and del a y char-act eri sti cs t han ot her circuits!i ncl udi n g Kan g"s do m i nos.~o Wever!due t o t he reducti on of t he cont enti on current of t he kee p er p MOS!our p r o-p osed circuits have l o Wer noi se i mmunit y.As sho Wn i n F i g.6!t he DC r obust ness and AC noi se m ar g i ns of t he first p r o p osed circuit are18.6 and1.6l o Wer t han t hose of t he dual V t do m i-nos!res p ecti vel y.in t he second p r o p osed circuit! t he DC r obust ness i s reduced b y Z.6!but t he AC noi se m ar g i ns ri se b y19.Z!co m p ared W it h t he dual V t do m i nos.
F i g.5Co m p arison of t he acti ve p o Wer!del a y ti m e!DC r obust ness and AC noise m ar g i n of t he fi ve diff erent8 i n p ut OR do m i no g ates A cti ve p o Wer!del a y!DC r obust ness!and AC noise m ar g i n of each do m i no current are nor m alized t o t hose of dual V t do m i no circuits!res p ecti vel y.
The i m p r ove m ents i n noi se i mmunit y i n t he second circuit co m p ared t o t he first circuit are due t o t he str on g er contr ol of t he noi se si g nal eff ect of t he short durati on p ul se of CLKZ co m p ared t o t he nor m al cl ock si g nal.A s co m p ared W it h t he first p r o p osed one!ho Wever!t he advant a g e of t he sec-ond circuit decreases as t he cl ock f re C uenc y i n-creases.W hen t he t Wo p r o p osed circuits reach t heir m axi mu m Wor ki n g f re C uenc y of 1.64G~z! t he short durati on p ul se si g nal CLKZ i n t he sec-ond p r o p osed circuit beco m es t he sa m e as CLK i n t he acti ve mode!and t he advant a g e of t he second circuit di sa pp ears.Consi deri n g so p hi sti cat ed f abri-cati on and i ncreased cost!t he second circuit t ech-ni C ue i s onl y a bett er choi ce f or l o W f re C uenc y cir-cuits.
A s al so sho Wn i n F i g.6!t he sub-t hreshol d l eaka g e and g at e l eaka g e currents bot h de p end str on g l y on t he st at e of eval uati on node i n t he du-al V t do m i nos.A l o W eval uati on node st at e W it h all i n p uts hi g h p r oduces a much l o Wer sub-t hresh-ol d l eaka g e current but g reat er g at e l eaka g e cur-rent co m p ared W it h a hi g h eval uati on node st at e W it h all i n p uts l o W.W hi ch eval uati on node st at e i s bett er t o reduce t he t ot al l eaka g e currents de-p ends on t he rel ati ve m a g nit ude of t he i ndi vi dual l eaka g e co m p onents.For t he t ot al l eaka g e cur-rents i n OR g at es Where t he sub-t hreshol d l eak-
80
8
第5期Guo Baozen g et al=D esi g ni n g Leaka g e-T ol erant and Noise-i mmune enhanced Lo W po Wer W i de-
F i g.6Co m p arison of t he leaka g e currents of t he fi ve
diff erent8-i n p ut OR do m i no g ates The leaka g e cur-
rents of each do m i no are nor m alized t o t he t otal l eaka g e
currents of dual V t do m i nos W it h hi g h i n p uts.
a g e current i s do m i nant,a l o W eval uati on node
st at e W it h hi g h i n p uts i s p ref erred f or p r oduci n g
l ess l eaka g e currents.Fr o m F i g.1,t he sub-
t hreshol d l eaka g e current i s l ar g er t han t he g at e
l eaka g e current i n45n m t echnol o gy at110and
a0.8V volt a g e su pp l y.Corres p ondi n g l y,a l o W e-
val uati on node st at e W it h hi g h i n p uts sho Ws bet-
t er l eaka g e charact eri sti c i n our si mul ati ons.F i g-ure7sho Ws t hat t he g at e l eaka g e current i s do m i nant i n45n m t echnol o gy at Z5and a0.8V volt a g e su pp l y.in t hi s case,a dual V t W it h l o W i n-p ut do m i nos i s p ref erabl e,as p r o p osed i n Ref.
[15].
The o pp osit e results m a y be ex p l ai ned as f ol-l o Ws.The sub-t hreshol d l eaka g e current i ncreases ex p onenti all y W it h t he i ncrease of t e m p erat ure due t o t he reducti on of t he t hreshol d volt a g e and t he i ncreasi n g of t he t her m al volt a g e[1Z,13].The g at e l eaka g e current,unli ke t he sub-t hreshol d l eaka g e current,has a ver y Weak de p endence on t e m p erat ure,as sho Wn i n F i g.7.A t110,t he sub-t hreshol d l eaka g e current m akes a l ar g er con-tri buti on t o t he t ot al l eaka g e current t han t he g at e l eaka g e current
The noi se i mmunit y de p ends not onl y on t he si ze and V t val ue of t he kee p er p MOS but al so on t he rati o bet Ween t he p MOS W i dt h and n MOS
f erent leaka
g e co m p onents W it
h te m p erat ure[1Z]
W i dt h i n t he out p ut i nvert er[14].Theref ore,t he kee p er p MOS and out p ut i nvert er i n Kan g s and our p r o p osed OR do m i nos bot h need t o be si zed t o m ai nt ai n si m il ar noi se i mmunit y t o t hat of dual V t do m i nos.The si mul ati on results sho W t hat t he p r o p osed circuits eff ecti vel y l o Wer t he acti ve p o W-er,reduce t he t ot al l eaka g e current,and enhance s p eed under si m il ar noi se i mmunit y conditi ons.A s sho W i n T abl e Z,t he del a y ti m e i s7.8hi g her f or Kan g s do m i nos,9.5l o Wer f or t he first p r o p osed circuit,and13.7 l o Wer f or t he second p r o p osed circuit as co m p ared t o t he dual V t do m i-nos.A s f or t he l eaka g e charact eri sti c sho Wn i n F i g.8,t he first p r o p osed circuit i s al most t he sa m e as Kan g s do m i nos,but t he second p r o p osed circuit sho Ws a bett er charact eri sti c t han Kan g s do m i nos.The reason m a y be as f oll o Ws.S i nce t he cont enti on current i s si g nifi cantl y reduced W it h t he l o W volt a g e s W i n g t echni C ue,t o achi eve t he sa m e noi se i mmunit y
90
8
半导体学报第Z7卷
i n our p r o p osed circuits i s s m all er resulti n g i n a
short er del a y ti m e and l ess p o Wer consu m p ti on.in
additi on t he a pp li cati on of a short durati on p ul se
si g nal i n t he second p r o p osed circuit bri n g s g reat
i m p r ove m ent t o t he p erf or m ance of t he hi g h fi n-i n
do m i nos i n sub-70n m t echnol o g i es.
T abl e Z S i mulati on results of ei g ht-i n p ut do m i no OR
g ate W it h t he sa m e noise i mmunit y
D iff erent8-i n p ut OR do m i nos
C l ock
f re C uenc y
Nor malized
noi se i mmunit y
Nor malized
acti ve p o Wer
Nor malized
del a y ti m e
Dual V t do m i nos1G~z111
Kan g s do m i nos1G~z11.Z091.078
F irst p r o p osed
do m i nos
1G~z10.91Z0.905 Second p r o p osed
do m i nos
1G~z10.88Z0.863
F i g.8Co m p arison of t he leaka g e current of fi ve diff er-ent8-i n p ut OR do m i no g ates The leaka g e current of each do m i no is nor m alized t o t he t otal l eaka g e currents of dual V t do m i nos W it h hi g h i n p uts.
4Concl us i on
in t hi s p a p er We have p r o p osed t Wo ne W cir-cuits t o su pp ress l eaka g e currents and enhance noi se i mmunit y Whil e decreasi n g t he acti ve p o Wer f or hi g h fi n-i n do m i no OR g at es i n sub-70n m C MOS t echnol o g i es.S i mul ati on results sho W t hat under si m il ar noi se i mmunit y conditi ons our p r o-p osed t echni C ues result i n8.8and11.8ac-ti ve p o Wer reducti on Whil e enhanci n g t he s p eed b y 9.5and13.7as co m p ared t o dual V t do m i no OR g at es W it h no g ati n g st a g e res p ecti vel y.A t t he sa m e ti m e t he t ot al l eaka g es of t he t Wo ne W W i de OR do m i nos W ere also reduced b y u p to 80.8 and8Z.4res p ecti vel y t he latter of Which is even better t han K an g s desi g n i n Ref.16].
in additi on f or dual V t do m i nos We have di s-cussed Whi ch st at e of t he eval uati on node i s bett er f or reduci n g t he t ot al l eaka g e current.Our anal y-si s sho Ws t hat it de p ends on t he rel ati ve m a g ni-t ude of t he i ndi vi dual l eaka g e co m p onents.W hen sub-t hreshol d l eaka g e current m akes a l ar g er con-tri buti on t o t he t ot al l eaka g e current a l o W eval u-ati on node st at e i s bett er and When g at e l eaka g e current beco m es do m i nant a hi g h eval uati on node st at e i s p ref erred.
References
1]Chatt er ee B S achdev M Kri shnna murt h y R.D esi g ni n g l eaka g e t ol erant l o W p o Wer W i de-OR do m i nos f or sub-
130n m C MOS t echnol o g i es.M i cr oel ectr on J Z00536<6>:
801
Z]W an g L i n g W en Don g xi n Yan g X i aozon g et al.S y nt hesi s sche m e f or l o W p o Wer desi g ns under ti m e constrai nts.Chi-
nese Jour nal of S e m i conduct ors Z005Z6
3]Sun~ui L i W enhon g Zhan g O i anli n g.A l o W-p o Wer su p er-p erf or m ance f our-Wa y set-associ ati ve C MOS cache m e mo-
r y.Chi nese Jour nal of S e m i conduct ors Z004Z5<4>:366
4]int er nati onal T echnol o gy Road m a p f or S e m i conduct ors Z001htt p:/p ubli https://www.wendangku.net/doc/869499139.html,/
5]Chen Ji nhui C l ar k L T Cao Yu.Robust desi g n of hi g h f an-
i n/out subt hreshol d circuits.pr oceedi n g s of int er nati onal
Conf erence on Co m p ut er D esi g n Z005:405
6]Keshavarzi A Narendra S Bor kar S et al.T echnol o gy scal-
i n g behavi or of o p ti mu m reverse bod y bi as f or st andb y
l eaka g e p o Wer reducti on i n C MOS i C s.pr oceedi n g s of in-
t er nati onal S y m p osi u m on Lo W po Wer e l ectr oni cs and D e-
si g n1999:Z5Z
7]Abdoll ahi A Fall ah F pedra m M.Leaka g e current reducti on
i n C MOS VLS i circuits b y i n p ut vect or contr ol.i eee
T rans Ver y Lar g e S cal e int e g rati on S y st e m s Z0041Z
140
8]Khandel Wal V S ri vast ava A.Leaka g e contr ol t hr ou g h fi ne-
g rai ned p l ace m ent and sizi n g of sl ee p transi st ors.pr oceed-
i n g s of i eee/AC Mint er nati onal Conf erence on Co m p ut er
A i ded D esi g n Z004:533
9]Kur oda T Fu it a T M it a S et al.A0.9V150M~z10m W 4mm Z Z-D di scret e cosi ne transf or m core p r ocessor W it h
vari abl e-t hreshol d-volt a g e sche m e.pr oceedi n g s of43r d
iSSCC1996:1770
10]Kur oda T Suzuki K M it a S et al.Vari abl e su pp l y-volt a g e sche m e f or l o W-p o Wer hi g h-s p eed C MOS di g it al desi g n.
i eee J Soli d-S t at e C ircuits199833<3>:454
11]O i n~ulf an g Cao Yu M ar kovi c D et al.SRA M l eaka g e su pp ressi on b y m i ni m izi n g st andb y su pp l y volt a g e.pr o-
ceedi n g s of t he5t h int er nati onal S y m p osi u m on O ualit y e-
l ectr oni
c D esi g n Z004:55
1Z]V l adi m irescu A Cao Yu Tho m as O et al.U ltra-l o W-volt a g e
r obust desi g n i ssues i n dee p-sub m i cr on C MOS.pr oceedi n g s
of t he Z nd Annual i eee Nort heast W or ksho p on C ircuits
and S y st e m s Z004:49
13]Kao J T Chandrakasan A p.Dual-t hreshol d volt a g e t ech-
ni C ues f or l o W-p o Wer di g it al circuits.i eee J Soli d-S t at e 018
第5期Guo Baozen g et al D esi g ni n g Leaka g e-T ol erant and Noise-i mmune enhanced Lo W po Wer W i de
C ircuits Z0003571009
14Kursun V Fri ed m an e G.Node volt a g e de p endent sub-t hreshol d l eaka g e current charact eri sti cs of d y na m i c cir-
cuits.pr oceedi n g s of i eee AC Mint er nati onal S y m p osi u m
on O ualit y e l ectr oni c D esi g n Z004104
15L i u Z Kursun V.Shift ed l eaka g e p o Wer charact eri sti cs of
d y na m i c circuits du
e t o g at e oxi de t unneli n g.pr oceedi n g s
of i eee int er nati onal S y st e m s on Chi p SOC Conf erence
Z005151
16Kan g S M Yan g G W an g Z D.Gat e l eaka g e t ol erant circuits
i n dee p sub-100n m C MOS t echnol o g i es.pr oceedi n g s of t he
int er nati onal Soci et y f or O p ti cal en g i neeri n g Spi e Z004
56
17Kursun V Fri ed m an e G.Lo W s W i n g dual t hreshol d volt a g e
Do m i no l o g i c.pr oceedi n g s of1Zt h G reat Lakes S y m p osi u m
on VLS i Z00Z47
18Kursun V Fri ed m an e G.Do m i no l o g i c W it h vari abl e t hreshol d.i eee T rans Ver y Lar g e S cal e int e g rati on VL-
S i S y st e m s Z0031161080
19Chi n p Zuko Wski C A G ri st ede G D et al.Charact erizati on of l o g i c circuit t echni C ues and o p ti m izati on f or hi g h-l eaka g e
C MOS t echnol o g i es.VLS i Jour nal Z005383491
Z0predi cti ve t echnol o gy model pTM htt p/WWW.eas.asu.
edu～p t m
Z1Kursun V Fri ed m an e G.S l ee p s W itch dual t hreshol d volt-
a g e Do m i no l o g i c W it h reduced st and
b y l eaka g e current.
i eee T rans Ver y Lar g e S cal e int e g rati on VLS i S y s-
t e m s Z0041Z5485
亚70n m CMO S工艺低漏电流!高噪声容限的低功耗
多输入多米诺或门的设计
郭宝增1宫娜1!T汪金辉Z
1河北大学电子信息工程学院保定07100Z
Z北京工业大学电子信息与控制工程学院北京1000Z Z
摘要"提出了两种新的电路技术在降低多输入多米诺或门的动态功耗的同时减小了漏电流并提高了电路
的噪声容限.采用新的电路技术设计了八输入多米诺或门并基于45n m BS i M4Spi Ce模型对其进行了模拟.
模拟结果表明设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗减小了总的漏电流同时
提高了工作速度.与双阈值多米诺电路相比设计的两种电路动态功耗分别降低了8.8和11.8电路速度分
别提高了9.5和13.7同时总的漏电流分别降低了80.8和8Z.4 .基于模拟结果也分析了双阈值多米
诺电路中求值点的不同逻辑状态对总的漏电流的影响.
关键词"低功耗漏电流多米诺或门噪声容限
EEACC1130B1Z65
中图分类号"TN4文献标识码"A文章编号"0Z53-4177#Z006$05-0804-08
T通信作者.Email ki n g a PP l e＠chi naacc.co m
Z005-1Z-08收到Z006-01-07定稿④Z006中国电子学会
118
亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多
米诺或门的设计
作者：郭宝增， 宫娜， 汪金辉， Guo Baozeng， Gong Na， Wang Jinhui
作者单位：郭宝增,宫娜,Guo Baozeng,Gong Na(河北大学电子信息工程学院,保定,071002)， 汪金辉,Wang Jinhui(北京工业大学电子信息与控制工程学院,北京,100022)
刊名：
半导体学报
英文刊名：CHINESE JOURNAL OF SEMICONDUCTORS
年，卷(期)：2006,27(5)
被引用次数：5次
参考文献(21条)
1.Chatterjee B;Sachdev M;Krishnnamurthy R Designing leakage tolerant,low power wide-OR dominos for sub-130nm CMOS technologies[外文期刊] 2005(06)
2.Wang Ling;Wen Dongxin;Yang Xiaozong Synthesis scheme for low power designs under time constraints[期刊论文]-Chinese Journal of Semiconductors 2005(02)
3.Sun Hui;Li Wenhong;Zhang Qianling A low-power super-performance four-way set-associative CMOS cache memory[期刊论文]-Chinese Journal of Semiconductors 2004(04)
4.International Technology Roadmap for Semiconductors 2001
5.Chen Jinhui;Clark L T;Cao Yu Robust design of high fan-in/out subthreshold circuits 2005
6.Keshavarzi A;Narendra S;Borkar S Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's 1999
7.Abdollahi A;Fallah F;Pedram M Leakage current reduction in CMOS VLSI circuits by input vector control 2004(02)
8.Khandelwal V;Srivastava A Leakage control through fine-grained placement and sizing of sleep transistors 2004
9.Kuroda T;Fujita T;Mita S A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme 1996
10.Kuroda T;Suzuki K;Mita S Variable supply-voltage scheme for low-power high-speed CMOS digital design[外文期刊] 1998(03)
11.Qin Hulfang;Cao Yu;Markovic D SRAM leakage suppression by minimizing standby supply voltage 2004
12.Vladimirescu A;Cao Yu;Thomas O Ultra-low-voltage robust design issues in deep-submicron CMOS 2004
13.Kao J T;Chandrakasan A P Dual-threshold voltage techniques for low-power digital circuits[外文期刊] 2000(07)
14.Kursun V;Friedman E G Node voltage dependent sub-threshold leakage current characteristics of dynamic circuits 2004
15.Liu Z;Kursun V Shifted leakage power characteristics of dynamic circuits due to gate oxide tunneling 2005
16.Kang S M;Yang G;Wang Z D Gate leakage tolerant circuits in deep sub-100nm CMOS technologies
2004
17.Kursun V;Friedman E G Low swing dual threshold voltage Domino logic 2002
18.Kursun V;Friedman E G Domino logic with variable threshold[外文期刊] 2003(06)
19.Chin P;Zukowski C A;Gristede G D Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies[外文期刊] 2005(03)
20.Predictive technology model(PTM)
21.Kursun V;Friedman E G Sleep switch dual threshold voltage Domino logic with reduced standby leakage current[外文期刊] 2004(05)
本文读者也读过(5条)
1.汪金辉.宫娜.冯守博.段丽莹.侯立刚.吴武臣.董利民.Wang Jinhui.Gong Na.Feng Shoubo.Duan Liying.Hou Ligang.Wu Wuchen.Dong Limin亚65nm工艺新型p结构多米诺与门设计[期刊论文]-半导体学报2007,28(11)
2.侯进永.邢座程.HOU Jin-yong.XING Zuo-cheng一种低功耗预比较TLB结构[期刊论文]-国防科技大学学报2006,28(5)
3.赵晓莺.佟冬.程旭.Zhao Xiaoying.Tong Dong.Cheng Xu VSF:CMOS组合电路的静态功耗评估模型[期刊论文]-半导体学报2007,28(5)
4.胡晓慧.张慧熙.李智.沈继忠基于多阈值技术的组合逻辑电路设计[会议论文]-2005
5.郎燕峰.LANG Yan-feng多值低功耗双边沿触发器的简化设计[期刊论文]-杭州电子科技大学学报2010,30(5)
引证文献(5条)
1.汪金辉.宫娜.耿淑琴.侯立刚.吴武臣.董利民45mm低功耗、高性能Zipper CMOS多米诺全加器设计[期刊论文]-电子学报 2009(2)
2.汪金辉.宫娜.耿淑琴.侯立刚.吴武臣.董利民45nm工艺pn混合下拉网络多米诺异或门设计[期刊论文]-半导体学报 2008(12)
3.汪金辉.宫娜.左磊.彭晓宏.吴武臣双阈值多米诺或门性能估计及其工艺浮动下的适用性分析[期刊论文]-电子学报 2010(11)
4.汪金辉.宫娜.侯立刚.吴武臣.董利民低功耗、高性能多米诺电路电荷自补偿技术[期刊论文]-半导体学报2008(7)
5.汪金辉.宫娜.冯守博.段丽莹.侯立刚.吴武臣.董利民亚65nm工艺新型p结构多米诺与门设计[期刊论文]-半导体学报 2007(11)
引用本文格式：郭宝增.宫娜.汪金辉.Guo Baozeng.Gong Na.Wang Jinhui亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计[期刊论文]-半导体学报 2006(5)