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CDCEL913PW中文资料

FEATURES

APPLICATIONS

Xout S1/SDA V S2/SCL V Y1GND V Y2Y3

C r y s t a l o r C l o c k I n p u t

V GND

V Y1

V CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

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Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V,2.5-V,and 3.3-V Outputs

Flexible Clock Driver

?Member of Programmable Clock Generator –Three User-Definable Control Inputs Family

[S0/S1/S2]e.g.,SSC Selection,

Frequency Switching,Output Enable or –CDCE913/CDCEL913:1-PLL,3Outputs Power Down

–CDCE925/CDCEL925:2-PLL,5Outputs –Programmable SSC Modulation –CDCE937/CDCEL937:3-PLL,7Outputs –Enables 0-PPM Clock Generation

–CDCE949/CDCEL949:4-PLL,9Outputs –Generates Common Clock Frequencies ?In-System Programmability and EEPROM Used With TI-DaVinci?,OMAP?,DSPs –Serial Programmable Volatile Register –Generates Highly Accurate Clocks for –Nonvolatile EEPROM to Store Customer Video,Audio,USB,IEEE1394,RFID,Setting

Bluetooth?,WLAN,Ethernet?,and ?Flexible Input Clocking Concept

GPS

–External Crystal:8MHz to 32MHz ? 1.8-V Device Power Supply –On-Chip VCXO:Pull Range ±150ppm ?

Separate Output Supply Pins –Single-Ended LVCMOS up to 160MHz –CDCE913:3.3V and 2.5V ?Free Selectable Output Frequency up to –CDCEL913:1.8V

230MHz

?Wide Temperature Range –40°C to 85°C ?Low-Noise PLL Core

?Packaged in TSSOP

–PLL Loop Filter Components Integrated ?

Development and Programming Kit for Easy –Low Period Jitter (Typical 50ps)

PLL Design and Programming (TI Pro-Clock?)

D-TV,STB,IP-STB,DVD-Player,DVD-Recorder,Printer

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DaVinci,OMAP,Pro-Clock are trademarks of Texas Instruments.Bluetooth is a trademark of Bluetooth SIG.I2C is a trademark of Philips Electronics.

Ethernet is a trademark of Xerox Corporattion.

PRODUCTION DATA information is current as of publication date.Copyright ?2007,Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

https://www.wendangku.net/doc/8712925888.html, CDCE913

CDCEL913

SCAS849A–JUNE2007–REVISED AUGUST2007

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The CDCE913and CDCEL913are modular PLL-based low-cost,high-performance,programmable clock synthesizers,multipliers,and dividers.They generate up to3output clocks from a single input frequency.Each output can be programmed in-system for any clock frequency up to230MHz,using the integrated configurable PLL.

The CDCx913has separate output supply pins,V DDOUT,which is1.8V for CDCEL913and2.5V to3.3V for CDCE913.

The input accepts an external crystal or LVCMOS clock signal.If an external crystal is used,an on-chip load capacitor is adequate for most applications.The value of the load capacitor is programmable from0to20pF. Additionally,an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal,i.e.PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio/video,networking(WLAN,BlueTooth, Ethernet,GPS)or interface(USB,IEEE1394,Memory Stick)clocks from e.g.,a27-MHz reference input frequency.

The PLL supports SSC(spread-spectrum clocking).SSC can be center-spread or down-spread clocking which is a common technique to reduce electro-magnetic interference(EMI).

Based on the PLL frequency and the divider settings,the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic.

The device supports non-volatile EEPROM programming for ease customization of the device to the application. It is preset to a factory default configuration(see the DEFAULT DEVICE CONFIGURATION section).It can be re-programmed to a different application configuration before PCB assembly,or re-programmed by in-system programming.All device settings are programmable through SDA/SCL bus,a2-wire serial interface.

Three programmable control inputs,S0,S1and S2,can be used to select different frequencies,or change SSC setting for lowering EMI,or other control features like,outputs disable to low,outputs3-state,power down,PLL bypass etc).

The CDCx913operates in a1.8-V environment.It is characterized for operation from–40°C to85°C

Terminal Functions for CDCE913,CDCEL913

TERMINAL

I/O DESCRIPTION

NAME PIN TSSOP14

Y1–Y311,9,8O LVCMOS outputs

Xin/CLK1I Crystal oscillator input or LVCMOS clock Input(selectable via SDA/SCL bus)

Xout14O Crystal oscillator output(leave open or pullup when not used)

V Ctrl4I VCXO control voltage(leave open or pullup when not used)

V DD3Power 1.8-V power supply for the device

CDCEL913:1.8-V supply for all outputs

V DDOUT6,7Power

CDCE913:3.3-V or2.5-V supply for all outputs

GND5,10Ground Ground

S02I User-programmable control input S0;LVCMOS inputs;internal pullup500k

SDA:bidirectional serial data input/output(default configuration),LVCMOS internal

SDA/S113I/O or I pullup;or

S1:user-programmable control input;LVCMOS inputs;internal pullup500k

SCL:serial clock input LVCMOS(default configuration),internal pullup500k or

SCL/S212I

S2:user-programmable control input;LVCMOS inputs;internal pullup500k

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V DD

GND

V DDOUT

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL RESISTANCE for TSSOP (PW)PACKAGE (1)(2)

CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

over operating free-air temperature range (unless otherwise noted)(1)

VALUE

UNIT V DD Supply voltage range –0.5to 2.5V V I Input voltage range (2)–0.5to V DD +0.5V V O Output voltage range (2)

–0.5to V DD +0.5

V I I Input current (V I <0,V I >V DD )20mA I O Continuous output current 50mA T stg Storage temperature range –65to 150

°C T J Maximum junction temperature

125

°C

(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

over operating free-air temperature range (unless otherwise noted)

AIRFLOW TSSOP14PARAMETER

(lfm)

°C/W 0

112150105T JA

Thermal resistance junction-to-ambient

250102500

97T JC Thermal resistance junction-to-case

–

(1)The package thermal impedance is calculated in accordance with JESD 51and JEDEC2S2P (high-k board).

(2)

For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI website at https://www.wendangku.net/doc/8712925888.html, .

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RECOMMENDED OPERATING CONDITIONS

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1)

EEPROM SPECIFICATION

CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

MIN

NOM MAX UNIT V DD Device supply voltage

1.7 1.8

1.9V Output Yx supply voltage for CDCE913,V DDOUT

2.3

3.6V O V Output Yx supply voltage for CDCEL913,V DDOUT 1.7 1.9V IL Low-level input voltage LVCMOS 0.3V DD

V V IH High-level input voltage LVCMOS 0.7V DD

V V I

(thresh)

Input voltage threshold LVCMOS 0.5V DD V

Input voltage range S0

0 1.9V I(S)V Input voltage range S1,S2,SDA,SCL;V I(thresh)=0.5V DD 0 3.6V I(CLK)Input voltage range CLK 0

1.9V Output current (V DDOUT =3.3V)±12I OH /I OL Output current (V DDOUT =

2.5V)±10mA Output current (V DDOUT =1.8V)±8C L Output load LVCMOS 15

pF T A

Operating free-air temperature

–40

°C

MIN

NOM MAX UNIT f Xtal Crystal input frequency range (fundamental mode)82732MHz ESR Effective series resistance 100

?f PR Pulling range (0V ≤V Ctrl ≤1.8V)(2)

±120

±150

ppm Frequency control voltage,V Ctrl 0

VDD V C 0/C 1Pullability ratio

220C L On-chip load capacitance at Xin and Xout

(1)For more information about VCXO configuration,and crystal recommendation,see application report (SCAA085).

(2)

Pulling range depends on crystal-type,on-chip crystal load capacitance and PCB stray capacitance;pulling range of min ±120ppm applies for crystal listed in the application report (SCAA085).

MIN

TYP MAX

UNIT EEcyc Programming cycles of EEPROM 1001000

cycles EEret

Data retention

years

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TIMING REQUIREMENTS

CDCE913

CDCEL913 SCAS849A–JUNE2007–REVISED AUGUST2007

over recommended ranges of supply voltage,load,and operating free-air temperature

MIN NOM MAX UNIT CLK_IN REQUIREMENTS

PLL bypass mode0160

f CLK LVCMOS clock input frequency MHz

PLL mode8160

t r/t f Rise and fall time CLK signal(20%to80%)3ns Duty cycle CLK at V DD/240%60%

STANDARD FAST

MODE MODE UNIT

MIN MAX MIN MAX

SDA/SCL TIMING REQUIREMENTS(see Figure12)

f SCL SCL clock frequency01000400kHz

t su(START)START setup time(SCL high before SDA low) 4.70.6μs

t h(START)START hold time(SCL low after SDA low)40.6μs

t w(SCLL)SCL low-pulse duration 4.7 1.3μs

t w(SCLH)SCL high-pulse duration40.6μs

t h(SDA)SDA hold time(SDA valid after SCL low)0 3.4500.9μs

t su(SDA)SDA setup time250100ns

t r SCL/SDA input rise time1000300ns

t f SCL/SDA input fall time300300ns

t su(STOP)STOP setup time40.6μs

t BUS Bus free time between a STOP and START condition 4.7 1.3μs

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DEVICE CHARACTERISTICS

CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS MIN

TYP (1)

MAX UNIT

OVERALL PARAMETER All outputs off,f CLK =27MHz,All PLLS on 11I DD

Supply current (see Figure 3)

f VCO =135MHz;mA

9Per PLL f OUT =27MHz V DDOUT =3.3V 1.3No load,all outputs on,I DD(OUT)Supply current (see Figure 4and Figure 5)mA f OUT =27MHz V DDOUT =1.8V 0.7Power-down current.Every circuit powered I DD(PD)f IN =0MHz,

V DD =1.9V

μA

down except SDA/SCL

Supply voltage Vdd threshold for power-up V (PUC)0.85 1.45V control circuit

f VCO VCO frequency range of PLL 80

230

MHz V DDOUT =3.3V 230f OUT

LVCMOS output frequency

MHz

V DDOUT =1.8V

230

LVCMOS PARAMETER V IK LVCMOS input voltage V DD =1.7V;I I =–18mA –1.2V I I LVCMOS Input current

V I =0V or V DD ;V DD =1.9V ±5μA I IH LVCMOS Input current for S0/S1/S2V I =V DD ;V DD =1.9V 5μA I IL LVCMOS Input current for S0/S1/S2V I =0V;V DD =1.9V –4

μA Input capacitance at Xin/Clk V IClk =0V or V DD 6C I

Input capacitance at Xout V IXout =0V or V DD 2pF

Input capacitance at S0/S1/S2

V IS =0V or V DD

CDCE913-LVCMOS PARAMETER FOR V DDOUT =3.3V –MODE

V DDOUT =3V,I OH =–0.1mA

2.9V OH

LVCMOS high-level output voltage

V DDOUT =3V,I OH =–8mA 2.4V

V DDOUT =3V,I OH =–12mA 2.2

V DDOUT =3V,I OL =0.1mA

0.1V OL LVCMOS low-level output voltage V DDOUT =3V,I OL =8mA 0.5V V DDOUT =3V,I OL =12mA 0.8

t PLH ,t PHL Propagation delay PLL bypass

3.2ns t r /t f Rise and fall time V DDOUT =3.3V (20%–80%)0.6ns t jit(cc)Cycle-to-cycle jitter (2)(3)

1PLL switching,Y2-to-Y35070ps t jit(per)Peak-to-peak period jitter (3)

1PLL switching,Y2-to-Y360

100ps t sk(o)Output skew

(4)

,See Table 2

f OUT =50MHz;Y1-to-Y360ps

odc

Output duty cycle

(5)

f VCO =100MHz;Pdiv =145%55%

CDCE913–LVCMOS PARAMETER for V DDOUT =2.5V –Mode V DDOUT =2.3V,I OH =–0.1mA

2.2V OH

LVCMOS high-level output voltage

V DDOUT =2.3V,I OH =–6mA 1.7V

V DDOUT =2.3V,I OH =–10mA 1.6

V DDOUT =2.3V,I OL =0.1mA

0.1V OL LVCMOS low-level output voltage V DDOUT =2.3V,I OL =6mA 0.5V V DDOUT =2.3V,I OL =10mA 0.7

t PLH ,t PHL Propagation delay PLL bypass

3.6ns t r /t f Rise and fall time V DDOUT =2.5V (20%–80%)0.8ns t jit(cc)Cycle-to-cycle jitter (2)(3)

1PLL switching,Y2-to-Y35070ps t jit(per)Peak-to-peak period jitter (3)

1PLL switching,Y2-to-Y360

100ps t sk(o)Output skew

(4)

,See Table 2

f OUT =50MHz;Y1-to-Y360ps

odc

Output duty cycle (5)

f VCO =100MHz;Pdiv =1

45%

55%

(1)All typical values are at respective nominal V DD .(2)10000cycles.

(3)Jitter depends on configuration.Jitter data is for input frequency =27MHz,f VCO =108MHz,f OUT =27MHz (measured at Y2).

(4)The tsk(o)specification is only valid for equal loading of each bank of outputs,and the outputs are generated from the same divider.(5)odc depends on output rise and fall time (t r /t f );data sampled on rising edge (tr)

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PARAMETER MEASUREMENT INFORMATION

CDCE913

Typical Driver Impedance

~ 32W ~ 18W

CDCE913

CDCEL913

SCAS849A–JUNE2007–REVISED AUGUST2007

DEVICE CHARACTERISTICS(continued)

over recommended operating free-air temperature range(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP(1)MAX UNIT CDCEL913—LVCMOS PARAMETER for V DDOUT=1.8V–Mode

V DDOUT=1.7V,I OH=–0.1mA 1.6

V OH LVCMOS high-level output voltage V DDOUT=1.7V,I OH=–4mA 1.4V

V DDOUT=1.7V,I OH=–8mA 1.1

V DDOUT=1.7V,I OL=0.1mA0.1

V OL LVCMOS low-level output voltage V DDOUT=1.7V,I OL=4mA0.3V

V DDOUT=1.7V,I OL=8mA0.6

t PLH,t PHL Propagation delay PLL bypass 2.6ns

t r/t f Rise and fall time V DDOUT=1.8V(20%–80%)0.7ns

t jit(cc)Cycle-to-cycle jitter(6)(7)1PLL switching,Y2-to-Y380110ps

t jit(per)Peak-to-peak period jitter(7)1PLL switching,Y2-to-Y3100130ps

t sk(o)Output skew(8),See Table2f OUT=50MHz;Y1-to-Y350ps odc Output duty cycle(9)f VCO=100MHz;Pdiv=145%55%

SDA/SCL PARAMETER

V IK SCL and SDA input clamp voltage V DD=1.7V;I I=–18mA–1.2V

I IH SCL and SDA input current V I=V DD;V DD=1.9V±10μA

V IH SDA/SCL input high voltage(10)0.7V DD V

V IL SDA/SCL input low voltage(10)0.3V DD V

V OL SDA low-level output voltage I OL=3mA,V DD=1.7V0.2V DD V

C I SCL/SDA Input capacitance V I=0V or V DD310pF

(6)10000cycles.

(7)Jitter depends on configuration.Jitter data is for input frequency=27MHz,f VCO=108MHz,f OUT=27MHz(measured at Y2).

(8)The tsk(o)specification is only valid for equal loading of each bank of outputs,and the outputs are generated from the same divider.

(9)odc depends on output rise and fall time(t r/t f);data sampled on rising edge(tr)

(10)SDA and SCL pins are3.3V tolerant.

Figure1.Test Load

Figure2.Test Load for50-?Board Environment

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TYPICAL CHARACTERISTICS

507090110130150170190210230f - Output Frequency - MHz

OUT I D D O U T - m A

60110160210

f - Frequency - MHz

VCO I - S u p p l y C u r r e n t - m A

D D

f - Output Frequency - MHz

OUT I D D O U T - m A

CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

CDCE913,CDCEL913CDCE913

SUPPLY CURRENT

OUTPUT CURRENT

PLL FREQUENCY

OUTPUT FREQUENCY

Figure 3.

Figure 4.

CDCEL913

OUTPUT CURRENT

OUTPUT FREQUENCY

Figure 5.

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APPLICATION INFORMATION CONTROL TERMINAL CONFIGURATION

CDCE913

CDCEL913 SCAS849A–JUNE2007–REVISED AUGUST2007

The CDCE913/CDCEL913has three user-definable control terminals(S0,S1,and S2)which allow external control of device settings.They can be programmed to any of the following functions:

?Spread spectrum clocking selection→spread type and spread amount selection

?Frequency selection→switching between any of two user-defined frequencies

?Output state selection→output configuration and power down control

The user can predefine up to eight different control settings.Table1and Table2explain these settings.

Table1.Control Terminal Definition

External Control Bits PLL1Setting Y1Setting

PLL Frequency

Control Function SSC Selection Output Y2/Y3Selection Output Y1and Power-Down Selection

Selection

Table2.PLLx Setting(can be selected for each PLL individual)(1)

SSC Selection(Center/Down)

SSCx[3-bits]Center Down

0000%(off)0%(off)

001±0.25%–0.25%

010±0.5%–0.5%

011±0.75%–0.75%

100±1.0%–1.0%

101±1.25%–1.25%

110±1.5%–1.5%

111±2.0%–2.0%

FREQUENCY SELECTION(2)

FSx FUNCTION

0Frequency0

1Frequency1

OUTPUT SELECTION(3)(Y2 (3)

YxYx FUNCTION

0State0

1State1

(1)Center/Down-Spread,Frequency0/1and State0/1are user-definable in PLLx Configuration Register;

(2)Frequency0and Frequency1can be any frequency within the specified f VCO range.

(3)State0/1selection is valid for both outputs of the corresponding PLL module and can be power down,

3-state,low or active

Table3.Y1Setting(1)

Y1SELECTION

Y1FUNCTION

0State0

1State1

(1)State0and State1are user definable in Generic Configuration

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Xin

Xout

V V

Y1 = 27 MHz

Y2 = 27 MHz

Y3 = 27 MHz SDA/SCL SERIAL INTERFACE

CDCE913

CDCEL913

SCAS849A–JUNE2007–REVISED AUGUST2007

S1/SDA and S2/SCL pins of the CDCE913/CDCEL913are dual function pins.In default configuration they are defined as SDA/SCL for the serial programming interface.They can be programmed as control-pins(S1/S2)by setting the appropriate bits in the EEPROM.Note that the changes to the Control Register(Bit[6]of Byte02h) have no effect until they are written into the EEPROM.

Once they are set as control pins,the serial programming interface is no longer available.However,if V DDOUT is forced to GND,the two control pins,S1and S2,temporally act as serial programming pins(SDA/SCL).

S0is not a multi use pin;it is a control pin only.

The internal EEPROM of CDCE913/CDCEL913is pre-configured with a factory default configuration as shown in Figure6(The input frequency is passed through the output as a default).This allows the device to operate in default mode without the extra production step of programming it.The default setting appears after power is supplied or after power-down/up sequence until it is reprogrammed by the user to a different application configuration.A new register setting is programmed via the serial SDA/SCL Interface.

Figure6.Default Configuration

A different default setting can be programmed upon customer request.Contact Texas Instruments sales or marketing representative for more information.

Table4shows the factory default setting for the Control Terminal Register.Note that even though8different register settings are possible,in default configuration,only the first two settings(0and1)can be selected with S0,as S1and S2are configured as programming pins in default mode.

Table4.Factory Default Setting for Control Terminal Register(1)

(1)In default mode or when programmed respectively,S1and S2act as serial programming interface,SDA/SCL.They do not have any

control-pin function but they are internally interpreted as if S1=0and S2=0.S0,however,is a control-pin which in the default mode switches all outputs ON or OFF(as previously predefined).

The CDCE913/CDCEL913operates as a slave device of the2-wire serial SDA/SCL bus,compatible with the popular SMBus or I2C specification.It operates in the standard-mode transfer(up to100kbit/s)and fast-mode transfer(up to400kbit/s)and supports7-bit addressing.

The S1/SDA and S2/SCL pins of the CDCE913/CDCEL913are dual function pins.In the default configuration they are used as SDA/SCL serial programming interface.They can be re-programmed as general purpose control pins,S1and S2,by changing the corresponding EEPROM setting,Byte02h,Bit[6].

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DATA PROTOCOL

COMMAND CODE DEFINITION

Generic Programming Sequence

MSB

LSB

MSB

LSB

Start Condition

Repeated Start Condition

1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx Acknowledge (ACK = 0 and NACK =1)Stop Condition

Master-to-Slave Transmission Slave-to-Master Transmission

CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

The device supports Byte Write and Byte Read and Block Write and Block Read operations.For Byte Write/Read operations,the system controller can individually access addressed bytes.

For Block Write/Read operations,the bytes are accessed in sequential order from lowest to highest byte (with most significant bit first)with the ability to stop after any complete byte has been transferred.The numbers of Bytes read-out are defined by Byte Count in the Generic Configuration Register.At Block Read instruction,all bytes defined in the Byte Count must be readout to correctly finish the read cycle.

Once a byte has been sent,it is written into the internal register and is effective immediately.This applies to each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM Write Cycle is initiated,the internal SDA registers are written into the EEPROM.During this Write Cycle,data is not accepted at the SDA/SCL bus until the write cycle is completed.However,data can be read out during the programming sequence (Byte Read or Block Read).The programming status can be monitored by EEPIP ,byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code,as described in Table 5.

Table 5.Slave Receiver Address (7Bits)

DEVICE

A6A5A4A3A2A1(1)A0(1)R/W CDCE913/CDCEL91311001011/0CDCE925/CDCEL92511001001/0CDCE937/CDCEL93711011011/0CDCE949/CDCEL9491

1/0

(1)

Address bits A0and A1are programmable via the SDA/SCL bus (byte 01,bit [1:0].This allows addressing up to 4devices connected to the same SDA/SCL bus.The least-significant bit of the address byte designates a write or read operation.

Table https://www.wendangku.net/doc/8712925888.html,mand Code Definition

BIT DESCRIPTION

0=Block Read or Block Write operation 71=Byte Read or Byte Write operation

(6:0)

Byte Offset for Byte Read ,Block Read ,Byte Write and Block Write operation.

Figure 7.Generic Programming Sequence

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Byte Write Programming Sequence

Byte Read Programming Sequence

Block Write Programming Sequence (1)

…

Block Read Programming Sequence

…

Timing Diagram for the SDA/SCL Serial Control Interface

SDA

IH IL

CDCE913CDCEL913

SCAS849A–JUNE 2007–REVISED AUGUST 2007

Figure 8.Byte Write Protocol

Figure 9.Byte Read Protocol

(1)

Data byte 0bits [7:0]is reserved for Revision Code and Vendor Identification.Also,it is used for internal test purpose and should not be overwritten.

Figure 10.Block Write Protocol

Figure 11.Block Read Protocol

Figure 12.Timing Diagram for SDA/SCL Serial Control Interface

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SDA/SCL HARDWARE INTERFACE

SDA/SCL CONFIGURATION REGISTERS

CDCE913

CDCEL913 SCAS849A–JUNE2007–REVISED AUGUST2007

Figure13shows how the CDCE913/CDCEL913clock synthesizer is connected to the SDA/SCL serial interface bus.Multiple devices can be connected to the bus but the speed may need to be reduced(400kHz is the maximum)if many devices are connected.

Note that the pullup resistors(R P)depends on the supply voltage,bus capacitance,and number of connected devices.The recommended pullup value is 4.7k?.It must meet the minimum sink current of3mA at V OL max=0.4V for the output stages(for more details see the SMBus or I2C?Bus specification).

Figure13.SDA/SCL Hardware Interface

The clock input,control pins,PLLs,and output stages are user configurable.The following tables and explanations describe the programmable functions of the CDCE913/CDCEL913.All settings can be manually written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock?software.TI Pro-Clock?software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

Table7.SDA/SCL Registers

Address Offset Register Description Table

00h Generic Configuration Register Table9

10h PLL1Configuration Register Table10

The grey-highlighted bits,described in the Configuration Registers tables in the following pages,belong to the Control Terminal Register.The user can predefine up to eight different control settings.These settings then can be selected by the external control pins,S0,S1,and S2.See the Control Terminal Configuration section.

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Table 8.Configuration Register,External Control Terminals

(1)

Address Offset refers to the byte address in the Configuration Register in Table 9and Table 10.

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Table 9.Generic Configuration Register

(1)Writing data beyond ‘20h’may affect device function.(2)All data transferred with the MSB first.(3)Unless customer-specific setting.

(4)During EEPROM programming,no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is completed.Data,however,can be read out during the programming sequence (Byte Read or Block Read).

(5)If this bit is set to high in the EEPROM,the actual data in the EEPROM is permanently locked.No further programming is possible.Data,however can still be written via SDA/SCL bus to the internal register to change device function on the fly.But new data can no longer be saved to the EEPROM.EELOCK is effective only,if written into the EEPROM.

(6)Selection of “control pins”is effective only if written into the EEPROM.Once written into the EEPROM,the serial programming pins are no longer available.However,if V DDOUT is forced to GND,the two control pins,S1and S2,temporally act as serial programming pins (SDA/SCL),and the two slave receiver address bits are reset to A0=”0”and A1=“0”.

(7)These are the bits of the Control Terminal Register (see Table 8).The user can predefine up to eight different control settings.These settings then can be selected by the external control pins,S0,S1,and S2.

(8)

The internal load capacitor (C1,C2)has to be used to achieve the best clock performance.External capacitors should be used only to finely adjust CL by a few picofarads.The value of CL can be programmed with a resolution of 1pF for a crystal load range of 0pF to 20pF.For CL >20pF,use additional external capacitors.Also,the value of the device input capacitance has to be considered which always adds 1.5pF (6pF//2pF)to the selected CL.For more information about VCXO configuration and crystal recommendation,see application report SCAA085.

(9)

The EEPROM WRITE bit must be sent last.This ensures that the content of all internal registers are stored in the EEPROM.The

EEWRITE cycle is initiated with the rising edge of the EEWRITE bit.A static level high does not trigger an EEPROM WRITE cycle.The EEWRITE bit has to be reset to low after the programming is completed.The programming status can be monitored by reading out EEPIP.If EELOCK is set to high,no EEPROM programming is possible.

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Table 9.Generic Configuration Register (continued)

Offset (1)Bit (2)

Acronym

Default (3)

Description

07h-0Fh

—

Unused address range

Table 10.PLL1Configuration Register

(1)Writing data beyond 20h may adversely affect device function.(2)All data is transferred MSB-first.(3)Unless a custom setting is used

(4)

The user can predefine up to eight different control settings.In normal device operation,these settings can be selected by the external control pins,S0,S1,and S2.

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SCAS849A–JUNE2007–REVISED AUGUST2007 Table10.PLL1Configuration Register(continued)

OFFSET(1)Bit(2)Acronym Default(3)DESCRIPTION

0–down

7SSC1DC0b PLL1SSC down/center selection:

1–center

16h

0–reset and stand-by

6:0Pdiv201h7-Bit Y2-Output-Divider Pdiv2:

1-to-127is divider value

7—0b Reserved–do not write others than0

17h0–reset and stand-by

6:0Pdiv301h7-Bit Y3-Output-Divider Pdiv3:

1-to-127is divider value

18h7:0PLL1_0N[11:4]

004h

7:4PLL1_0N[3:0]

19h

3:0PLL1_0R[8:5]

000h PLL1_0:30-Bit Multiplier/Divider value for frequency f

VCO1_0

7:3PLL1_0R[4:0]

(for more information,see paragraph PLL Multiplier/Divider Definition).

1Ah

2:0PLL1_0Q[5:3]

10h

7:5PLL1_0Q[2:0]

4:2PLL1_0P[2:0]010b

1Bh00–f VCO1_0<125MHz

01–125MHz≤f VCO1_0<150MHz

1:0VCO1_0_RANGE00b f VCO1_0range selection:

10–150MHz≤f VCO1_0<175MHz

11–f VCO1_0≥175MHz

1Ch7:0PLL1_1N[11:4]

004h

7:4PLL1_1N[3:0]

1Dh

3:0PLL1_1R[8:5]

000h PLL1_1:30-Bit Multiplier/Divider value for frequency f

VCO1_1

1Eh7:3PLL1_1R[4:0]

(for more information see paragraph PLL Multiplier/Divider Definition)

2:0PLL1_1Q[5:3]

10h

1Fh7:5PLL1_1Q[2:0]

4:2PLL1_1P[2:0]010b

00–f VCO1_1<125MHz

01–125MHz≤f VCO1_1<150MHz

1:0VCO1_1_RANGE00b f VCO1_1range selection:

10–150MHz≤f VCO1_1<175MHz

11–f VCO1_1≥175MHz

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?OUT+?IN

Pdiv

M(1)

?VCO+?IN N

M(2)

?P=4–int ǒlog2N

ǔ[if P t0then P+0]

?Q=int ǒN?M ǔ

CDCE913

CDCEL913

SCAS849A–JUNE2007–REVISED AUGUST2007

At a given input frequency(?IN),the output frequency(?OUT)of the CDCE913/CDCEL913can be calculated:

where

M(1to511)and N(1to4095)are the multiplier/divide values of the PLL;Pdiv(1to127)is the output divider.

The target VCO frequency(?VCO)of each PLL can be calculated:

The PLL internally operates as fractional divider and needs the following multiplier/divider settings:

?R=N′–M×Q

where

N′=N×2P;

N≥M;

100MHz200MHz.

Example:

for?IN=27MHz;M=1;N=4;Pdiv=2;for?IN=27MHz;M=2;N=11;Pdiv=2;

→f OUT=54MHz→f OUT=74.25MHz

→f VCO=108MHz→f VCO=148.50MHz

→P=4–int(log24)=4–2=2→P=4–int(log25.5)=4–2=2

→N′’=4×22=16→N′’=11×22=44

→Q=int(16)=16→Q=int(22)=22

→R=16–16=0→R=44–44=0

The values for P,Q,R,and N’are automatically calculated when using TI Pro-Clock?software.

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PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)

Lead/Ball Finish

MSL Peak Temp (3)CDCE913PW PREVIEW TSSOP PW 1490TBD Call TI Call TI CDCE913PWR PREVIEW TSSOP PW 142000TBD Call TI Call TI CDCEL913PW PREVIEW TSSOP PW 1490TBD Call TI Call TI CDCEL913PWR

PREVIEW

TSSOP

2000

TBD

Call TI

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/8712925888.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty

as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

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