正弦脉宽调制波(PWM)的verilog文档

module pwm_1phase(
clk,
rst,
pwm
);
input clk;
input rst;
output pwm;

wire [9:0]q1;
wire [7:0]q2;

wire [7:0]rom_data;
wire [7:0]rom_addr;
wire clk_9;

reg [6:0]cnt;
reg [7:0]CNT;

assign clk_9 = q1[9];
assign CLK_0 = q1[0];

always@(posedge clk_9 or negedge rst)
if(!rst)
cnt = 0;
else if(cnt ==125)
cnt = 0;
else
cnt = cnt + 1;

assign rom_addr = cnt;

always@(posedge CLK_0 or negedge rst)
if(!rst)
CNT = 0;
else if(clk_9 == 0 && CNT != 255)
CNT = CNT + 1;
else if(clk_9 == 1 && CNT != 0)
CNT = CNT - 1;
else
CNT = CNT;


assign q2 = CNT;

counter1 my_counter1(
.CLK(clk),
.RST(rst),
.Q1(q1)
);
rom_126data my_rom_126_data(
.ROM_DATA(rom_data),
.ROM_ADDR(rom_addr)
);
comp_rom_counter my_comp_rom_counter(
.RST(rst),
.CLK(clk),
.PWM(pwm),
.ROM_DATA(rom_data),
.Q2(q2)
);


endmodule


module counter1(
CLK,
RST,
Q1
);
input CLK,RST;
output [9:0]Q1;

reg [9:0]cnt;

always@(posedge CLK or negedge RST)
if(!RST)
cnt = 0;
else cnt = cnt + 1;

assign Q1 = cnt;

endmodule


module rom_126data(
ROM_DATA,
ROM_ADDR
);
input [7:0]ROM_ADDR;
output [7:0]ROM_DATA;

reg [7:0]ROM[125:0];


assign ROM_DATA = ROM[ROM_ADDR];
initial $readmemb("rom_pwm.txt",ROM,0,125);

endmodule

module comp_rom_counter(
RST,
CLK,
PWM,
ROM_DATA,
Q2
);
output PWM;
input [7:0]ROM_DATA;
input [7:0]Q2;
input CLK;
input RST;

reg PWM;

always@(posedge CLK or negedge RST)
if(!RST)
PWM = 0;
else if(Q2 < ROM_DATA)
PWM = 1;
else if(Q2 > ROM_DATA)
PWM = 0;
else if(Q2 == 255 & ROM_DATA == 255)
PWM = 0;
else if(Q2 == 0 & ROM_DATA == 0)
PWM = 1;
else
PWM = PWM;


endmodule


module testbench;
wire pwm_t;
reg clk_t;
reg rst_t;

pwm_1phase my_pwm_1phase(
.clk(clk_t),
.rst(rst_t),
.pwm(pwm_t)
);

initial
begin
rst_t = 1;
#10rst_t = 0;
#10rst_t = 1;
end

initial
begin
clk_t = 0;
forever #1clk_t = ~clk_t;
end

endmodule

10000000
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11111111
11111111
11111111
11111111
11111111
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11000000
10111010
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10101111

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00000001
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