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A Nonlinear-Disturbance-Observer-Based DC-Bus Voltage Control for a Hybrid AC DC Microgrid

A Nonlinear-Disturbance-Observer-Based DC-Bus Voltage Control for a Hybrid AC DC Microgrid
A Nonlinear-Disturbance-Observer-Based DC-Bus Voltage Control for a Hybrid AC DC Microgrid

A Nonlinear-Disturbance-Observer-Based DC-Bus V oltage Control for a Hybrid AC/DC Microgrid Chengshan Wang,Senior Member,IEEE,Xialin Li,Li Guo,Member,IEEE,and Yun Wei Li,Senior Member,IEEE

Abstract—DC-bus voltage control is an important task in the op-eration of a dc or a hybrid ac/dc microgrid system.To improve the dc-bus voltage control dynamics,traditional approaches attempt to measure and feedforward the load or source power in the dc-bus control scheme.However,in a microgrid system with distributed dc sources and loads,the traditional feedforward-based methods need remote measurement with communications.In this paper,a nonlinear disturbance observer(NDO)based dc-bus voltage con-trol is proposed,which does not need the remote measurement and enables the important“plug-and-play”feature.Based on this observer,a novel dc-bus voltage control scheme is developed to sup-press the transient?uctuations of dc-bus voltage and improve the power quality in such a microgrid system.Details on the design of the observer,the dc-bus controller and the pulsewidth-modulation (PWM)dead-time compensation are provided in this paper.The effects of possible dc-bus capacitance variation are also consid-ered.The performance of the proposed control strategy has been successfully veri?ed in a30kV A hybrid microgrid including ac/dc buses,battery energy storage system,and photovoltaic(PV)power generation system.

Index Terms—DC–AC bidirectional converter,dc-bus voltage control,hybrid ac/dc microgrid,nonlinear disturbance observer (NDO),plug-and-play.

I.I NTRODUCTION

A HYBRID ac/dc microgrid is regarded as a small scale

power generation,distribution and consumption system with the presence of ac and dc buses,distributed generation(DG) units,energy storage systems,and ac/dc loads[1]–[3].In such a system,the DG units with nonpower frequency output voltage or dc output voltage can be connected into the dc bus through ac–dc converters and dc–dc converters,respectively.The dc subgrid is tied to the ac bus via one or multiple bidirectional dc–ac interlinking converters[4]–[6].Compared to an ac or dc microgrid,a hybrid ac/dc microgrid can take advantage of both

Manuscript received July3,2013;revised September26,2013and Decem-ber23,2013;accepted December26,2013.Date of publication January2, 2014;date of current version July8,2014.This work was supported by the National High Technology Research and Development of China(863Program) (2011AA05A107)and Ph.D.Programs Foundation of Ministry of Education of China(20120032120084).Recommended for publication by Associate Editor Z.Chen.

C.Wang,X.Li,and L.Guo are with the School of Electrical and Engineer-ing Automation,Tianjin University,Tianjin300072,China(e-mail:cswang@ https://www.wendangku.net/doc/8f14019236.html,;xialinlee@https://www.wendangku.net/doc/8f14019236.html,;liguo@https://www.wendangku.net/doc/8f14019236.html,).

Y.W.Li is with the Department of Electrical and Computer Engineering, University of Alberta,Edmonton,AB T6G2V4,Canada(e-mail:yunwei.li@ ualberta.ca).

Color versions of one or more of the?gures in this paper are available online at https://www.wendangku.net/doc/8f14019236.html,.

Digital Object Identi?er

10.1109/TPEL.2013.2297376Fig.1.An Example diagram of a hybrid ac/dc microgrid[1],[2].

DG units and storage systems to meet load demand requirements with less power conversion stages.As a result,the system can operate with improved ef?ciency,economy,and reliability. Fig.1shows an example diagram of a hybrid ac/dc microgrid scheme[1],[2].In the ac subgrid,the bus voltage and frequency are mainly decided by the main ac grid in grid-connected opera-tion and by the supply/demand of the reactive and active power in the autonomous islanding operation.However,with no reac-tive power?ow in the dc subgrid,only the active power distur-bance will lead to the dc-bus voltage?uctuation.The main rea-sons for the power disturbances in the dc subgrid are:1)abrupt change of dc loads;2)DG units and storage systems output power variations;and3)power exchange?uctuations between the dc and ac subgrids.If not controlled properly,the dc-bus voltage variation could trigger dc system protection.Therefore, a suitable dc-bus voltage control strategy plays a key role to en-sure good power quality and stable operation of the dc subgrid or even the whole ac/dc microgrid system.

In general,the dc voltage can be regulated by either the bidi-rectional dc–ac converter or the energy storage systems in a dc subgrid.In most hybrid ac/dc microgrids,the ac subgrid has the capability to support the dc subgrid while maintaining the stability of the ac bus voltage.Thus the bidirectional dc–ac in-verter between the dc and ac subgrids is usually used to ensure a constant dc-bus voltage and maintain the power and energy balance within the dc subgrid[7]–[10].This is also the scenario considered in this paper.

For the dc–ac bidirectional inverter control,the conventional dual-loop control strategy is usually adopted.In such a dual-loop control,the outer dc-bus voltage control loop maintains a constant dc-bus voltage,while the inner current loop is for

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current https://www.wendangku.net/doc/8f14019236.html,ually,PI controllers are used for the volt-age and current control,especially when the current control is implemented in the synchronous reference frame[11]–[17]. To improve dc-bus voltage control dynamics,feeding forward the disturbance(dc system mismatched current or power in-formation)in the dual-loop control has been proposed to track the mismatched power quickly and reduce the dc-bus voltage ?uctuation[18]–[23].However,these feedforward methods are limited to the condition that the dc–ac converter control scheme can have the information of DGs,energy storage systems,and loads current/power in real time.For a hybrid ac/dc microgrid as shown in Fig.1,it is impractical to have the entire sources or loads information due to the dispersed nature of DGs,en-ergy storage systems and loads.High bandwidth communica-tions between the sources/loads of the dc subgrid and the dc–ac converter will be required in this case,which is against the scalability and plug-and-play feature desired for such an ac/dc microgrid.

More recent methods to improve the dynamics of dc volt-age control without involving the possible remote measure-ment include the constant-frequency asynchronous sigma-delta modulation(CF-ASDM)control[24],the one line-cycle regu-lation approach(OLCRA)and one-sixth line-cycle regulation approach(OSLCRA)based dc-bus voltage control[25].For the CF-ASDM method,the dc-bus voltage is regulated between the high/low bounds by using a hysteresis comparator to gen-erate the current loop reference.The idea is essentially similar to a voltage controller.But how to set the hysteresis band to achieve an accurate regulation of dc voltage and how to prop-erly scale the reference current from the hysteresis comparator is not straightforward.The OLCRA and OSLCRA methods con-trol the dc-bus voltage indirectly through the charge and power balance principle.These methods need accurate information of the dc-bus capacitance to achieve good control accuracy,and therefore,an estimation of the dc-bus capacitance is part of the control scheme.

In this paper,a dc-bus voltage control method based on a nonlinear disturbance observer(NDO)is proposed,where the simple and well-accepted dual-loop control with PI controllers are used together with a disturbance feedforward loop aided by the NDO.The proposed method only uses the dc-bus voltage and instantaneous power through the dc–ac converter and does not require voltage and current information of the sources/loads in the dc subgrid.As a result,the decentralized control with plug-and-play feature is achieved.Based on the developed ob-server,an improved feedforward method is designed by setting a?rst derivative element in series with the feedforward chan-nel to compensate the current loop dynamics and the observer convergence rate.The effects of the possible dc-bus capacitance variation are also analyzed in the dc voltage control scheme. Lastly,considering the dead-time effect to the control perfor-mance of current loop[26],[27],a dead-time compensator is also designed to further improve the performance of the pro-posed feedforward method.The performance of the proposed method has been veri?ed in a30kV A hybrid microgrid system including battery energy storage and photovoltaic(PV)power generation

system.Fig.2.Con?guration of the dc subgrid system.

II.DC S UBGRID/M ICROGRID M ODEL

An example dc subgrid system is illustrated in Fig.2,where all DG units and dc loads are connected to the dc bus.In this system,the PV unit is controlled with maximum power point tracking(MPPT)and its dc–dc converter operates in boost stage. In order to compensate the PV output variation,the dc load changes,and to track the dispatched demands from the central control system[7],[28],the battery energy storage system is adopted and operate with bidirectional energy?ow.The dc–ac converter between the dc subgrid and the ac grid is formed by a three phase pulsewidth-modulation(PWM)voltage-source inverter(VSI)and an LCL?lter.As discussed earlier,this inter-linking inverter controls the dc-bus voltage to be constant and maintain the power and energy balance within the dc subgrid. In this paper,the proposed dc-bus voltage control method is implemented in a system as shown in Fig.2.

In the dc subgrid,as shown in Fig.2,the dynamic differential equation for the capacitor voltage of dc bus can be described as C

du dc

dt

=(i bat+i pv?i load)?i dc(1) where C represents the value of the dc-bus capacitor;u dc,i bat, i pv,i load,and i dc denote the dc-bus voltage,output dc currents of the battery storage system,PV unit,dc load consumption, and the input dc current of the interlinking dc–ac converter, respectively.

The dc/ac converter model in the synchronous dq frame (which is oriented with the grid voltage)can be depicted as

?

???

???

???

???

???

???

???

???

???

???

???

???

???

???

???

???

e d=L1

di invd

dt

+i invd R1+[v cd+(i invd?i d)R d]+ωL1i invq e q=L1

di invq

dt

+i invq R1+[v cq+(i invq?i q)R d]?ωL1i invd i invd=C f

dv cd

dt

+i d+ωC f v cq

i invq=C f

dv cq

dt

+i q?ωC f v cd

v cd+(i invd?i d)R d=L2

di d

dt

+i d R2+u d+ωL2i q

v cq+(i invq?i q)R d=L2

di q

dt

+i q R2?ωL2i d

(2)

Fig.3.Structure of the traditional dc-bus voltage control system.

where e d and e q are the d-and q-axis components of inverter output voltage;u d is the d-axis component of grid voltage(since the dq frame is oriented with the grid voltage,the q axis compo-nent u q is equal to0);ωis the fundamental angular frequency; L1and L2are the?lter inductances(see Fig.2);R1and R2 denote the equivalent resistances describing the system loss and the parasitic resistances of the?lter inductances;C f and R d are the?lter capacitance and passive damping resistance,respec-tively;i invd and i invq denote the active and reactive components of the converter side current;i d and i q are the active and reactive components of the grid side current;v cd and v cq are the d and q axis components of?lter capacitance voltage.

The traditional dual loop control strategy for dc-bus voltage control is shown in Fig.3,where i o=i bat+i pv?i load.The outer voltage loop usually adopts PI controller to track the refer-ence voltage,while the inner loop is for current tracking with PI controller based on grid voltage oriented control method.If the grid side current(i d and i q)are chosen to be the feedback vari-ables for the current loop,the control equations can be depicted as

?????????

????????e dref=u d+ω(L1+L2)i q+(i dref?i d)k pid+k iid u dr e qref=?ω(L1+L2)i d+(i qref?i q)k pid+k iid u qr

u dr=

i dref?i d

s

u qr=

i qref?i q

s

(3)

where k pid and k iid are the proportional and integral gains of the current loop controller,respectively.e dref and e qref represent the reference modulation voltages(which are equal to“e d”and “e q”if the control delay and dead time are not considered). Because the LCL?lter aims to primarily reduce the high-frequency current ripple,and the closed-loop bandwidth of the current control is always designed to be less than the resonant frequency of the LCL?lter[17],the in?uence of the?lter ca-pacitors can be neglected in the latter section for the dc-bus control system design(which is mainly focused on the lower frequency range)[15],[29].As a consequence,the grid voltage, grid side current and the inverter output voltage in dq frame can be expressed as

e d=u d+L(di d/dt)+ωLi q+i d R

e q=L(di q/dt)?ωLi d+i q R

(4)

where L=L1+L2;R=R1+R2.

According(3)and(4),the closed-loop transfer function G c(s) for the current control is obtained in the following equation:

G c(s)=

(k pid s+k iid)

Ls2+(R+k pid)s+k iid

.(5)

TABLE I

S YSTEM P

ARAMETERS

As shown in(5),G c(s)is a typical second-order system

with an additional closed-loop zero,whose damping ratio?and

natural angular frequencyωn are de?ned by

?

???

???

2?ωn=

k pid+R

L

ω2n=

k iid

L

(6)

Considering the limited overcurrent ability of the power con-

verters,step response overshoot should be avoided in the control

design.From(6),it can be seen that a larger integral gain will

lead to a higher natural frequency and lower damping ratio with

less system damping.With the system parameters shown in Ta-

ble I,when the current control PI parameters are selected as k pid

=1and k iid=20,the following performance of the current loop

can be obtained:?=2.1,ωn=80rad/s,t s=4.4/?ωn=26ms.

When damping ratio?is greater than1,means step response

overshoot will be avoided for the current tracking.While the

settling time t s=26ms means current control loop will need

about26ms to track the reference with zero steady error.

From Fig.3,the dc-bus voltage response can be depicted by

u dc(s)=

(k pu/C)(1+(k iu/k pu s))(1/s)G c(s)k

1+(k pu/C)(1+(k iu/k pu s))(1/s)G c(s)k

U dcref(s)

+

1/sC

1+(k pu/C)(1+(k iu/k pu s))(1/s)G c(s)k

i o(s)

(7)

where the?rst term in(7)describes the tracking performance of

the voltage controller,while the latter term represents the distur-

bance rejection performance.k pu and k iu are the proportional

Fig.4.Structure of the proposed dc-bus voltage control system.

gain and integral constant of the outer voltage loop controller (τ=k pu /k iu ).G c (s )is the closed-loop transfer function of the inner current loop as shown in (5).k is a scale factor equal to 1.5u d /U dc according to (8),where U dc is the average value of dc-bus voltage.

Neglecting the conversion loss of the converters,the active power p g transferred between the dc subgrid and the ac grid can be expressed by

p g =u dc i dc =1.5u d i d .

(8)

As illustrated in (1),the dc-bus voltage is prone to the power disturbance in the dc microgrid such as abrupt change of dc load (i load ),output variation of DG units and energy storage systems (i bat ,and i pv ).If the control system dynamic response speed needs to be improved to reduce the impact of disturbance current on the dc-bus voltage,the stability margin of the control system has to be sacri?ced,which will be analyzed later.In this paper,an NDO-based dc-bus voltage control strategy is pro-posed.As demonstrated in Fig.4,the proposed control scheme is comprised of three parts:

1)NDO:The NDO is implemented to track the power dis-turbances in the dc subgrid.It also provides reference for both the dead-time compensation in current loop and feedforward control in the voltage loop.

2)V oltage loop:It adopts PI regulator in parallel with an improved power disturbance feedforward control to com-pensate the delay inherently involved in the current loop response and observer convergence rate.

3)Current loop:The current loop is based on the voltage-oriented control with dead-time compensation.The dead-time effect has to be compensated to avoid impacts on the dynamic response of current loop and the dc-bus voltage control performance.

Details on the design of the NDO,voltage loop with feed-forward control,and the current control loop with dead-time compensation are presented in the next section.

III.DC-B US V OLTAGE C ONTROL S TRATEGY

A.Design of an NDO

According to (1),(4)and (8),the second-order system de-picted in (9)(considering active current dynamic equation only)can be used to describe the dc-bus voltage control system

?

??????du dc dt =?1.5u d i d Cu dc +i o C

di d dt =?R L i d ?ωi q

+e d ?u d

L (9)

where i o =i bat +i pv ?i load .

In order to obtain the standard form for NDO,the following de?nition has been adopted:?

??????????????????

x =[x 1x 2]T =[u dc i d ]T ,u =e d ,d (t )=i o a (x )=?R L i d ?ωi q ?

u d L ,b (x )=1L

g 2(x )= 1C 0 T y =x 1

(10)

where x 1and x 2are state variables,u is the control input,d (t )is the mismatched disturbance,and y is the output.Then,the system (9)can be rewritten as

˙x =f (x )+g 1(x )u +g 2(x )d (t )

y =x 1(11)where f (x )=[?1.5u d x 2/Cx 1a (x )]T ,g 1(x )=[0b (x )]T .

As a consequence,the disturbance in (11)can be estimated by the NDO [30],[31]????

d =z +p (x )

dz dt

=?(l (x )g 2

(x ))z ?l (x )[g 2(x )p (x )+f (x )+g 1(x )u ]

(12)

where?d is the estimation of the disturbance,z is the intermediate state of the nonlinear observer,and p(x)is the observer function needed to be designed,which can be depicted by

p(x)=l1x1+l2x2(13) The observer gains l(x)are then decided by

l(x)=?p(x)

?x

=[l1l2].(14)

Assumption:The disturbance d(t)in system(11)satis?es

????

???d?=sup|d(t)|

t>0

lim

t→∞

dd(t)

dt

=0

(15)

Note that the disturbance i o in dc microgrid is always satis-?ed for this assumption.With the assumption in(15),the error convergence equation can be derived by

de d(t) dt +(l(x)g

2

(x))e d(t)=0(16)

where e d(t)=d(t)??d(t).

If the observer gains l(x)are selected such that l(x)g2(x)>0, which implies(16)is globally asymptotically stable[30],distur-bance estimation?d of NDO in(12)can track the disturbance d(t) of system(11)asymptotically with time constant1/l(x)g2(x). To simplify the observer design and eliminate the in?uence of other uncertain factors(such as a(x)and u)on the observation, the observer gains can be chosen as l1>0,l2=0.The time con-stant for the novel disturbance observation is C/l1.Generally, the dynamic response of the observer is faster than that of the feedback control system.However,if l1is too large,the system may subject to saturation or noise during implementation. With these considerations,an NDO to track the disturbance i o in(9)can be determined by

???

?? i

o

=z+l1u dc

dz

dt

=?

l1

C

z?

l21u dc

C

+

1.5u d

Cu dc

l1i d

(17)

where i o is the estimated value of the disturbance i o.

The proposed NDO can estimate the mismatched disturbance in(9),which implies that the disturbances act via the different channel as the control input.On the other side,the NDO can be designed separately from the controller design.If(9)is lin-earized and consider the linear observers presented in[32],[33], more observer gains need to be designed and the implementa-tion of the linear observers is more complicated than that of the NDO(17).

From(16)and(17),the following relationship to describe the observed value and the actual value of disturbance current has been considered:

?i o (s)=

1

1+T dob s

i o(s)(18)

where T dob=C/l1

.

Fig.5.DC-bus voltage control block.

B.Voltage Loop with an Improved Feedforward Control

From the power balance point of view,the transients triggered

by the disturbance current i o in the dc subgrid will?rst cause

?uctuations on dc bus.Then,the active current reference value

i dref will be regulated accordingly by the outer voltage loop con-

troller in the traditional dual-loop control structure to stabilize

the dc voltage.As a result,the output current i d of the dc–ac

inverter will lag the variation of i o.When large perturbation

occurs,the dc bus may suffer signi?cant impact.In order to re-

duce the impact,an NDO-based improved feedforward control

loop has been embedded in the dc-bus voltage loop as shown

in Fig.4.The schematic of the voltage loop with the proposed

improved feedforward control is illustrated in Fig.5,where the

dc-bus voltage response can be depicted by

u dc(s)=

(1/sC)G upi(s)G c(s)k

1+(1/sC)G upi(s)G c(s)k

U dcref(s)

+

1

sC+G upi(s)G c(s)k

i o(s)

?G fd(s)G c(s)k

sC+G upi(s)G c(s)k

?i

o

(s).(19)

As the feedforward control has an open-loop nature,its dy-

namic response will be faster than the feedback loop control.

However,if the feedforward value is not so accurate that the

open loop control will result in steady-state mismatch with the

reference.Thus,the PI controller will help to eliminate the errors

between the reference and the feedback.

As can be seen from(18)and(19),if the feedforward transfer

function G fd(s)is designed as

G fd(s)=

1+T dob s

kG c(s)

(20)

the in?uence of the disturbance current i o on the dc-bus volt-

age u dc can be mitigated signi?cantly.In the proposed control

scheme,the disturbance current needed for the feedforward con-

trol is produced from the NDO designed in(17).This is done

without any additional current sensors or communication be-

tween the dc subgrid and the dc–ac converter,and therefore the

system scalability and plug-and-play feature of the DGs within

the dc subgrid are maintained.

Combining(5)and(20),the detailed representation of the

function G fd(s)can be obtained as

G fd(s)=

1

k

Ls+R

k pid s+k iid

s+1

(1+T dob s)

=

1

k

[G LD(s)s+1](1+T dob s)(21)

Fig.6.Equivalent circuit of DG/load connected to dc link in the dc subgrid.

where G LD (s )is a lead and lag https://www.wendangku.net/doc/8f14019236.html,ually during the transient,the rate of the disturbance current i o is much higher than the corner frequencies of G LD (s ),and the reduced order of G LD (s )can be used to simplify the analysis

G LD (s )≈

L k pid

.(22)

From the earlier analysis,the feedforward function G fd (s )can be expressed as

G fd (s )=

1+((L/k pid )+T dob )s k =1+T fd s k

(23)

where T fd is called derivative time constant.

It is obvious that the ultimate feedforward function G fd (s )compensates both the tracking time delay of NDO and the re-sponse time of the current loop.A larger proportional gain (k pid )of the current controller,or higher convergence rate of NDO will lead to smaller derivative time constant T fd .

In a practical control system,the output of NDO i o contains

both the estimated value of the disturbance current and high-frequency noise signals.The simple differential operation in (23)will therefore be sensitive to the high-frequency noises.To avoid this noise ampli?cation,a derivative ?lter as shown in (24)can be adopted,which can reduce the sensitivity to high-frequency noise while without affecting much the disturbance estimation ability.In (24),N is the ?ltering coef?cient,which determines the corner frequency of the derivative ?lter

G fd (s )=1

k 1+T fd Ns N +s

.(24)

C.Effects of DC-Bus Capacitance Variations

In an actual dc subgrid,dc loads or the DG units are usually

connected to the dc bus through line impedance (as shown in Fig.2).An equivalent circuit of the DG or load connected to the dc bus is shown in Fig.6,where the DG or load is represented as a capacitance C r (used as voltage stabilizer and ?lter)in parallel with an impedance R eq (which can be negative for DG).This will lead to two possible complications:1)possible resonance caused by the line impedance and dc-bus capacitance [34],and 2)the variation of equivalent dc-bus capacitance [35].In a low voltage microgrid with relatively small capacity,the line/cable resistance R cable could provide damping to the system,and therefore,the uncertainty in the equivalent dc-link capacitance is considered due to connection/disconnection of dc sources and loads.

In order to achieve good performance in both dc-bus volt-age tracking and disturbance rejection,the open loop frequency characteristic of the voltage control should have a phase

margin

Fig.7.Impact of k p u and k iu on the frequency characteristic and the band-width of the control

system.

Fig.8.Feasible region of the dc-bus capacitance value C and the proportional gain k p u when (a)τ=0.1and (b)τ=0.02.

about 45?,wide middle frequency bandwidth,and appropriate cut-off frequency.Considering the stability margin of the control system,the closed-loop control bandwidth and anti-disturbance capability,the relationship between the parameters of the dc-bus voltage controller and the equivalent capacitance is analyzed here.

Fig.7describes the impact of voltage control parameters (k pu and k iu )on the phase margin of the frequency characteristic and the bandwidth of the control system using the model in (7).It can be seen that a larger equivalent proportional gain k pu /C will lead to a wider bandwidth,but result in a smaller phase margin.If the integral gain is larger,the stability margin will be reduced,although the settling time can be shortened.Further,it can be seen from Fig.7that,with τ=k pu /k iu =0.1,in order to ensure a certain bandwidth of dc-bus voltage control systems (such as [50,300](rad/s))and guarantee the phase margin is greater than 45?,the equivalent proportional gain k pu /C can be chosen from 50to 340.

From (7),if the current loop dynamics are neglected,the dc-bus voltage ?uctuation caused by the disturbance current can be depicted as (without the feedforward)

Δu dc (s )=

s

s 2C +k pu ks +k pu k/τ

Δi o (s ).

(25)

Through the aforementioned analysis,to achieve the given stability margin,the closed-loop control bandwidth range and the dc-bus voltage variations under the disturbance,the feasi-ble region of the dc-bus capacitance value C under different proportional gain k pu of the dc-bus voltage control system can be obtained as shown in Fig.8,where the minimum value of

Fig.9.(a)Root loci of system(27)with C changing from0.01to0.08F.

(b)Performance of the NDO-based dc-bus voltage control under transient with different capacitances.

capacitance is limited by the dc-bus voltage variations under disturbance[36],[37],and the maximum value is limited by the stability margin and the closed-loop control bandwidth.It can be seen from Fig.8that a smaller proportional gain k pu allows larger range of capacitance variation.Furthermore,by compar-ing Fig.8(a)and(b),it can be seen that the integral time constant τof the dc voltage control system has obvious effects on the feasible capacitance variation range.A smaller time constant will signi?cantly reduce this range.

On the other hand,the dc-bus capacitance also has impact on the performance of the NDO as shown in(17),where the estimation of the disturbance current can be depicted as

i o (s)=

kl1

sC0+l1

i d(s)+

l1C0s

sC0+l1

u dc(s)(26)

where C0is the normal value of the capacitance. Therefore,the variation of the dc-bus voltage can be analyzed by(27),at the bottom of this page,from Fig.4and(5),(19)and (26).

When the normal value of the dc-bus capacitance is selected as0.01F for the control system and observer design,the root loci of system(27)and the time-domain performance of the NDO-based dc-bus voltage control under transient with different actual values of the capacitance are shown in Fig.9(a)and(b), respectively.As shown in Fig.9(a),when the difference between the normal value and actual value of the dc-bus capacitance becomes greater,the system will become more oscillatory with reduced damping.In Fig.9(b),obvious oscillation occurs when C is equal to0.04F(four times of the nominal value C0), which will deteriorate the performance of the proposed control system.However,the NDO-based dc-bus control system still has good robustness against the parameters variation.E.g.in the system under study,when the control parameters are selected as described in Section IV(A),the allowed variation range of

the Fig.10.(a)Root loci of system(28)and(29)with L cab le changing from1 to10mH.(b)Performance comparison of the proposed dc-bus voltage control and traditional method.

dc-bus capacitance considering both the dc voltage control and NDO dynamics can be around0.02F(two times of C0).This can be veri?ed through Fig.9(a),where0.02F leads to suf?cient stability margin and good damping of the system response.

If the effect of the line impedance shown in Fig.6on the system stability can not be ignored,the variation of the dc-bus voltage shown in(27)can be modi?ed to be(28),at the bottom of this page.

Then(28)can be used to analyze the effect of the line impedance on the dc voltage control system with NDO method. The following expression(which is the dc voltage variation with the traditional method)can be used to analyze the effect of the line impedance on the performance of the traditional dc voltage control system:

Δu dc(s)=

1

(s2L cable C r+sR cable C r+1)(kG upi(s)G c(s)+sC0)+sC r ×Δi s(s).(29) Fig.10(a)shows the comparison of the root loci of system(28) and(29)with L cable changing from1mH to10mH.Especially, the eigenvalues denoted by Eig.1and Eig.2are obtained from (29)and(28),respectively,when the resistance value R cable= 0.1Ωand inductance value L cable=2mH.While,when R cable increased to0.5Ω,eigenvalues denoted by Eig.1and Eig.2will move toward the symbols Eig.3and Eig.4,respectively.It can be seen that:1)when the inductance value L cable becomes greater, the system will become more oscillatory with reduced damping;

2)the resistance R cable could provide damping to the system by comparing the poles positions of Eig.1and Eig.3,or that of Eig.2 and Eig.4;3)under the same condition,the proposed control can provide more damping to the system than the traditional method because by comparing the poles positions of Eig.1and Eig.2,

Δu dc(s)=

1?G c(s)G fd(s)(kl1/sC0+l1)

sC(1?G c(s)G fd(s)(kl1/sC0+l1))+k(G upi(s)G c(s)+G c(s)G fd(s)(sC0l1/sC0+l1))

Δi o(s)(27)

Δu dc(s)=

1?G c(s)G fd(s)(kl1/(sC0+l1))

(s2L cable C r+sR cable C r+1)(kG upi(s)G c(s)+sC0)+(1?G c(s)G fd(s)(kl1/(sC0+l1)))sC r

Δi s(s)(28)

Fig.11.V oltage error vector introduced by dead-time.

or that of Eig.3and Eig.4.The earlier comments1)and2)are consistent with the analysis in[34].In order to further verify comments3),Fig.10(b)shows the time-domain performance comparison of the proposed dc-bus voltage control(28)and traditional method(29)with the disturbance currentΔi s= 1A.As can be seen from Fig.10(b),when the line impedance L cable=5mH and R cable=0.1Ω,the NDO-based control can not only suppress the maximum dc voltage?uctuation,but also reduce the dc voltage oscillations(from0.3V under traditional method to0.18V under the proposed control),which means the proposed method has the ability to reduce the oscillations caused by the line impedance.

Note that for the model considered in this section,the control of sources and loads that connected to the dc link through dc/dc converters are not considered.A full model with the control of other dc/dc converters and the effects of constant power loads (CPLs)are analyzed in the Appendix,where it shows that as long as the NDO and dc/dc converter control are designed properly, the dc-bus voltage control system will have acceptable stability margin and good dynamics using the simpli?ed analysis in this section.

D.Dead-Time Compensation

In a voltage-source converter,the dead-time is implemented in the PWM signals for two switching devices in the same leg. Although the dead-time T d is very small,it causes deviations between the ideal modulation voltages(e dpwm and e qpwm)and the actual output voltages(e d and e q)(see Fig.4),leading to current control performance degradation[26],[27].This cur-rent control dynamics degradation will consequently affect the disturbance feedforward control.

To analyze the dead-time effects,the ac voltages and currents in abc and dq frames are represented in the coordinate frames illustrated in Fig.11,where U and I denote the grid voltage vector and grid side current vector,respectively.δ,θand?are the angles between U and I,between U and a-axis,and between I and a-axis,respectively.Based on the space vector analysis method,voltage error vector concept is adopted to describe the deviations caused by the dead-time[38].As shown in Fig.11, the space is divided into six equal sectors,and the voltage error vector denoted byΔEi(i=1,2,...,6)will change its position 6times in a power frequency cycle.The detailed relationship betweenΔEi and?is depicted in[38].If the6th harmonic component is not considered,the voltage error vector can be de-scribed to be a vector whose amplitude is equal to2u dc T d/(3T s)(where T s is the switching period.),and phase lags behind the grid side current vector I with180?.Therefore,the projections values ofΔEi in dq frame can be derived as

?

???

???

???

???

ΔE d=?ΔE

i d

i2

d

+i2q

ΔE q=?ΔE

i q

i2

d

+i2q

(30)

whereΔE is the amplitude of the voltage error vector.

Due to the voltage errorsΔE d andΔE q,the actual output voltages(e d and e q)obtained from the ideal modulation voltages (e dpwm and e qpwm)can be expressed by

e dpwm+ΔE d=e d

e qpwm+ΔE q=e q.(31) As a result,the response o

f i d should be modi?ed to

i d(s)=G c(s)i dref(s)+

s

Ls2+(R+k pid)s+k iid

ΔE d(s).

(32) Based on(32),the dc-bus voltage response as shown in(18) should be updated to

u dc(s)

=

(1/sC)G upi(s)G c(s)k

1+(1/sC)G upi(s)G c(s)k

U dcref(s)

+

1

sC+G upi(s)G c(s)k

i o(s)?

G fd(s)G c(s)k

sC+G upi(s)G c(s)k

?i

o

(s)

?sk

Ls2+(R+k pid)s+k iid

1

sC+G upi(s)G c(s)k

ΔE d(s).

(33) According to(33),if the variation ofΔE d orΔ(ΔE d)is not equal to zero,the dc-bus voltage will be affected by this term during the transient.From(30),when the inverter delivers a certain reactive power(i q)or the disturbance of dc side results in the inverter power?ow direction,Δ(ΔE d)will not be equal to zero.Especially in the latter scenario,Δ(ΔE d)will reach its maximum value when there is no reactive power output, resulting in serious impact on the dc-bus voltage.

To compensate the dead-time effect and therefore minimize its impact on the dc-bus voltage control,the following compen-sation algorithm is designed based on the earlier analysis:

e dpwm=u d+(i dref?i d)(k pid+k iid/s)+ωL?i q?ΔE d e qpwm=(i qref?i q)(k pid+k iid/s)?ωL?i d?ΔE q.(34) The critical part o

f applying(34)is to obtain the voltage errors ΔE d andΔE q accurately.To do this,the power injected to the dc bus is?rst obtained by usin

g the dc-bus voltage multiplied by the estimated value of the disturbance i o from the NDO.Then, from(8),the required output active current i d of dc–ac to be transferred between the dc and ac subgrids can be determined. Combined wit

h the reactive current

i q,the voltage errorsΔE d andΔE q can be decided by(30).

Fig.12.30kV A hardware setup of the dc subgrid.

IV.V ERIFICATION OF THE C ONTROL S TRATEGY

https://www.wendangku.net/doc/8f14019236.html,boratory Setup Details

To verify the effectiveness of the proposed NDO-based dc-bus voltage control method,a dc subgrid system as illustrated in Fig.2has been built.This dc subgrid is interfaced to the ac grid through a dc–ac converter.The corresponding hard-ware experiment platform is shown in Fig.12,with its sys-tem parameters listed in Table I.In addition,the converters are controlled by a Renesas MCU(M32192F8)+FPGA-based digital controller,with the experimental pro?les observed by a ScopeCorder(YOKOGAW A SL1400).

To emulate the variation of the equivalent dc-link capacitance, two different capacitance values(0.01F and0.02F,respectively) as shown in Table I have been considered.From the theoretical analysis on the feasible region of the dc-bus capacitance and the proportional gain k pu of the dc-bus voltage control system as shown in Fig.8,the parameters of the voltage PI regulator are chosen as:k pu=1,k iu=10.The observer gain l1is chosen to be 10,and the theoretical setting time of NDO error equation(16)is about1ms.According to the parameters chosen earlier,the time constant T fd and the?ltering coef?cient N of the differentiator are4.1ms and200,respectively.

B.Experimental Results

1)Scenario1:In this scenario,the dc-bus capacitance is 0.01F.A disturbance on the system is introduced by controlling the batteries from standby mode to discharging mode(with current reference of30A),while the dc load and PV output are about2.8and2.5kW,respectively.The control performance of conventional PI control and the proposed method have been compared.Because the output power?ow direction of dc–ac converter is changed,this scenario can also be used to verify the performance of the dead-time compensation.

Fig.13shows the theoretical and simulation results with the traditional dual-loop control and the proposed NDO-based dc-bus voltage control method,respectively.The parameters in

the Fig.13.DC voltage variation under disturbance:(a)theoretical results using (33)and(b)simulation results.

PSCAD simulation are the same as in the Table I.The battery voltage is about550V,so with30A current output from the battery,the equivalent disturbance current to dc link i o is22A (with dc voltage at750V),which will cause the dc/ac converter to deliver power to the grid.As discussed earlier in Section III-D, the response of the dc-bus voltage control system will be affected by the voltage errors due to dead-time,which can be analyzed by(33).Fig.13(a)shows the dc-bus voltage response using(31) (only the variation is considered),while Fig.13(b)shows the dc-bus voltage variation(the reference dc-bus voltage is750V) under the transient disturbance.It can be seen that the simulation results obtained in PSCAD are consistent with the theoretical analysis.

Figs.14–16show the experimental results with traditional control and the proposed NDO-based dc-bus voltage control method,respectively.Under the traditional PI control,the dc-bus voltage increased to about787V abruptly,and it took about0.2s to return to the steady-state status,which is consistent with the theoretical analysis and simulation results.With the proposed NDO-based feedforward control method(while without dead-time compensation)as shown in Fig.15,the dc-bus voltage variation has been mitigated signi?https://www.wendangku.net/doc/8f14019236.html,pared with the results in Fig.14,the maximum dc bus has been reduced to 759V with less than28V of voltage?uctuation.The settling time of the dc-bus control system has also been shortened to about30ms.

It can be seen from Figs.14and15,the power is originally balanced in the dc subgrid and the dc–ac inverter”s power is around0.After the disturbance,output power of the dc–ac con-verter is increased to15kW due to the output power variation of the battery energy storage system.So the angle between the grid voltage vector U(d-axis)and the grid side current vector I changes,which causes variation of the voltage errorsΔE d andΔE q;and affects both the performance of current loop and the feedforward control according to(33).Fig.16shows results with the dead-time compensation based on the control scheme described in https://www.wendangku.net/doc/8f14019236.html,paring the results in Figs.15and16,the peak of the dc-bus voltage has been further reduced to755V. As can be seen from the battery current in Figs.14–16,the switching process from battery standby mode to discharging state needs about50ms.This is related to the terminal voltage of the storage system,current references and control parameters of dc–dc controller.

Fig.14.Experimental results under the traditional control scheme.(a)dc-bus voltage:6.25V/div.(b)Battery voltage:3.75V/div.(c)Battery current:5A/div.(d)Phase A voltage:125V/div.(e)Phase A current:12.5A/div.(f)PV voltage:12.5V/div.(g)PV current:1.25A/div.(h)DC load current:0.75

A/div.

Fig.15.Experimental results with NDO-based control and without dead-time compensation.(a)DC-bus voltage:5V/div.(b)Battery voltage:3.75V/div.(c)Battery current:5A/div.(d)Phase A voltage:125V/div.(e)Phase A current:12.5A/div.(f)PV voltage:12.5V/div.(g)PV current:1.25A/div.(h)DC load current:0.75A/div.

Lastly,the performance of the NDO has been shown in Fig.17,which veri?ed that the NDO can track the power dis-turbance effectively.

2)Scenario 2:Compared to the ?rst experiment,the dc-link capacitance has been changed to 0.02F in Scenario 2to verify the control performance under 100%increase of the dc-bus capacitance.The control parameters are selected to be the same in both scenarios.Again the disturbance is introduced by controlling the batteries from standby mode to

discharging

Fig.16.Experimental results with NDO-based control and with dead-time compensation.(a)DC-bus voltage:5V/div.(b)Battery voltage:3.75V/div.(c)Battery current:5A/div.(d)Phase A voltage:125V/div.(e)Phase A current:12.5A/div.(f)PV voltage:12.5V/div.(g)PV current:1.25A/div.(h)DC-load current:0.75

A/div.

Fig.17.

Output of the NDO.

mode (with current reference of 30A),while the dc load and PV output are about 2.8and 2.5kW,respectively.

As seen from Fig.18,the simulation results using PSCAD are consistent with the theoretical analysis under the https://www.wendangku.net/doc/8f14019236.html,pared to Fig.13,the variation of dc-bus capacitance has lit-tle in?uence on the stability of the control system,provided the controller parameters are chosen properly.But the dc-bus volt-age ?uctuation has been reduced to 780V under the traditional PI control due to the larger capacitance used.

Fig.19shows the experimental results with the traditional control,where the dc-bus voltage increased to about 780V during the transient.Due to the increased size of the dc-bus capacitor,the dc-bus voltage ?uctuation has been reduced com-pared to Fig.14,which is consistent with the theoretical analysis

Fig.18.DC voltage variation under disturbance:(a)theoretical results using (33)and (b)simulation

results.

Fig.19.Experimental results under the traditional control scheme.(a)DC-bus voltage:6.25V/div.(b)Battery voltage:3.75V/div.(c)Battery current:5A/div.(d)Phase A voltage:125V/div.(e)Phase A current:12.5A/div.(f)PV voltage:12.5V/div.(g)PV current:1.25A/div.(h)DC-load current:0.75A/div.

and simulation results.With the proposed NDO-based feedfor-ward control method (while without dead-time compensation)as shown in Fig.20,the maximum dc bus has been reduced to 759V with less than 21V compared with the results in Fig.18.The settling time of the dc-bus control system has also been shortened signi?cantly.Fig.21shows the results with the dead-time compensation based on the control scheme described in https://www.wendangku.net/doc/8f14019236.html,paring the results in Figs.20and 21,the peak of the dc-bus voltage has been reduced to 757V .The performance of the NDO has been shown in Fig.22,which can track the power disturbance effectively.This result in Fig.22is also consistent with Fig.9,where the NDO response starts to become a bit oscillatory when the capacitance is increased to 0.02F.

Overall,it can be seen that the designed control system has a good robustness to deal with the parameters uncertainty of the system,and there is a good match among the theoretical analysis,simulations,and experimental results.

V .C ONCLUSION

A simple NDO-based dc-bus voltage control strategy was proposed in this paper,which is especially suitable for a

hy-

Fig.20.Experimental results with NDO-based control and without dead-time compensation.(a)DC-bus voltage:5V/div.(b)Battery voltage:3.75V/div.(c)Battery current:5A/div.(d)Phase A voltage:125V/div.(e)Phase A current:12.5A/div.(f)PV voltage:12.5V/div.(g)PV current:1.25A/div.(h)DC-load current:0.75

A/div.

Fig.21.Experimental results with NDO-based control and with dead-time compensation.(a)DC-bus voltage:5V/div.(b)Battery voltage:3.75V/div.(c)Battery current:5A/div.(d)Phase A voltage:125V/div.(e)Phase A current:12.5A/div.(f)PV voltage:12.5V/div.(g)PV current:1.25A/div.(h)DC-load current:0.75A/div.

brid ac/dc microgrid or a dc microgrid.With the proposed con-trol strategy,high bandwidth communications between the dc source/loads and the dc–ac converter can be avoided,which is key for the system scalability and maintaining the plug-and-play feature of the DGs.Based on the estimated results from NDO,the proposed dc-bus voltage control method with improved feed-forward and dead-time compensation can signi?cantly reduce

Fig.22.Output of the

NDO.

Fig.23.

Con?guration of the dc subgrid system for full model analysis.

the dc-bus control settling time and mitigate the dc-bus voltage variations.The effects of equivalent dc-bus capacitance varia-tion are also considered in this paper.The experimental results from a 30kV A dc subgrid have shown the effectiveness of the proposed control strategy.

A PPENDIX

Without loss of generality,assume that the dc microgrid in-cludes two dc–dc converters for the system stability analysis,which operate in boost stage and buck stage,respectively,as shown in Fig.23.Speci?cally,the boost dc–dc converter is controlled by current regulation and transmit power from the source to the dc bus,which is typical for a PV unit or battery storage system interface in discharging mode (note that the bat-tery charging mode will be same as the buck dc–dc converter and therefore a bidirectional dc–dc converter is not used here).On the other hand,the buck dc–dc converter acting as a line-regulating converter (LRC)to supply power for the constant power loads (CPLs)is controlled by voltage regulation [5],[9],[39].

From Fig.23,the average state model of the boost dc–dc converter can be depicted as

?

??

u s =L 1di 1dt +(1?d 1)u dc

u s i 1=u dc i o 1(A1)

where u s ,i 1and i o 1denote the dc source voltage,the inductor current and output dc currents of the boost dc–dc converter,respectively,L 1is ?lter inductance,and d 1is the duty cycle.When the current loop adopts the PI controller,the duty cycle can be obtained as

?

??d 1=(i 1ref ?i 1)k pi1+k ii1u 1r

u 1r

=i 1ref ?i 1

s

(A2)

where i 1ref is the current reference,k pi1and k ii1are the propor-tional gain and integral constant of the current loop controller,respectively,u 1r is the integral state of the current PI controller.When the models in (A1)and (A2)are linearized,the resulting current response can be depicted by

Δi 1=

U dc (k pi1s +k ii1)

L 1s 2+k pi1U dc s +k ii1U dc Δi 1ref

?

(1?D 1)s

L 1s 2+k pi1U dc s +k ii1U dc

Δu dc

(A3)

where Δdenotes small disturbance,U dc is the steady-state dc voltage,D 1is the steady-state duty cycle.

Therefore,the closed-loop transfer function G i (s )in (A4)for the current control can be used to analyze the stability of the boost dc–dc converter

G i (s )=

U dc (k pi1s +k ii1)

L 1s 2+k pi1U dc s +k ii1U dc

.

(A4)

In a similar way,the average state model of the buck dc–dc converter can be depicted as

???????

??????

u o =?L 2di 2dt +d 2u dc i 2=C 2du o dt +P L u o +u dc R o u o i 2=?u dc i o 2(A5)where u o ,i 2and i o 2denote the dc source voltage,the inductor current and output dc currents of the buck dc–dc converter,respectively,L 2and C 2are the ?lter inductance and capacitance,respectively,d 2is the duty cycle,the loads includes a resistor R o and a CPL P L .

When the buck dc–dc converter adopts the dual-loop control with two PI controllers,the duty cycle can be drawn by

?

??????????????????i 2ref =(u oref ?u o )k pu2+k iu2u 2ur u 2ur =u oref ?u o s

d 2=(i 2ref ?i 2)k pi2+k ii2u 2r u 2r

=i 2ref ?i 2

s

(A6)

where u2ref is the voltage reference,i2ref is the current refer-ence;k pu2and k iu2,k pi2,and k ii2are the proportional gain and integral constant of the voltage loop and current loop controllers, respectively;u2ur and u2r are the integral states of the voltage and current PI controllers,respectively.

When the models in(A5)and(A6)are linearized the resulting load voltage response can be depicted by(A7),at the bottom of this page,whereΔdenotes small disturbance,U o is the steady-state voltage,D2is the steady-state duty cycle.

Thus,the closed-loop transfer function G uo(s)in(A8),at the bottom of this page,for the current control can be used to analyze the stability of the buck dc–dc converter.

When considering the effect of the dc–dc converters control systems on the dc-bus voltage control system stability,the com-plete signal model in(A9),at the bottom of this page,can be built through Fig.5and(A1)–(A8).

From(A9),the effect of the boost dc–dc converter,buck dc–dc converter,and the NDO on the system stability can be studied by eigenvalue analysis.The comparisons of the eigenvalues of in (A9)and the loci of the characteristic equations[which are cal-culated from characteristic equations of boost dc–dc converter in(A4),buck dc–dc converter in(A8),and dc-bus voltage con-trol system in(19)]with variation of different parameters(such as k pi1,k pu2,P L,and the NDO gain l1)are shown in Figs.24, 25,and26,respectively.In these?gures,the symbol“×”,“+”,“o,”and“?”denote the eigenvalues of the characteristic ma-trix of the complete signal model in(A9),and the loci of the characteristic equations in(19),(A8),and(A4),respectively.

Δu o=

(k pi2s+k ii2)(k pu2s+k iu2)U dc

(k pi2s+k ii2)(k pu2s+k iu2)U dc+s2+(C2s?P L

U2o

+1

R o

)s[L2s2+(k pi2s+k ii2)U dc]

Δu oref

+

D2s2

(k pi2s+k ii2)(k pu2s+k iu2)U dc+s2+(C2s?P L

U2o

+1

R o

)s[L2s2+(k pi2s+k ii2)U dc]

Δu dc(A7)

G uo(s)=

(k pi2s+k ii2)(k pu2s+k iu2)U dc

(k pi2s+k ii2)(k pu2s+k iu2)U dc+s2+(C2s?P L

U2o

+1

R o

)s[L2s2+(k pi2s+k ii2)U dc]

(A8)

???????????????????????????????????????????????????????????????????????????????????????????????????C

dΔu d c

dt

=

U s

U d c

Δi1?

U o

U d c

Δi2?

I2

U d c

Δu o?

2

R d c

Δu d c?

1.5U d

U d c

Δi d

L

dΔi d

dt

=?Δi d(R+k p i)+(Δu d c?Δu d cref)k p u k p i+Δu u d cr k iu k p i+Δu d r k ii+k p i

1

k

(Δz+l1Δu d c)+k p i

T fd s

k

Δz+k p i

T fd s

k

l1Δu d c dΔu d r

dt

=(Δu d c?Δu d cref)k p u+Δu u d cr k iu?Δi d+

1

k

(Δz+l1Δu d c)+

T fd s

k

Δz+

T fd s

k

l1Δu d c

dΔu u d cr

dt

=Δu d c?Δu d cref

L1

dΔi1

dt

=?(1?D1)Δu d c+[(Δi1ref?Δi1)k p i1+Δu1r k ii1]U d c

dΔu1r

dt

=Δi1ref?Δi1

L2

dΔi2

dt

=?Δu o+D2Δu d c+[((Δu oref?Δu o)k p u2+k iu2Δu2u r)k p i2?Δi2k p i2+k ii2Δu2r)]U d c

dΔu2r

dt

=(Δu oref?Δu o)k p u2+k iu2Δu2u r?Δi2

C2

dΔu o

dt

=Δi2?

Δu o

R o

+

P L

U o U o

Δu o

dΔu2u r

dt

=Δu oref?Δu o

dΔz

dt

=?

l1

C

Δz?

l21Δu d c

C

+

k

C

l1Δi d

(A9)

https://www.wendangku.net/doc/8f14019236.html,parison of the eigenvalues of in (A9)(“x”)and the loci of the characteristic equations in (A8)(“o”),(19)(“+”),and in (A4)(“?”),with the current loop gain k p i1of the boost dc–dc converter changed from 0.0005to

0.003.

https://www.wendangku.net/doc/8f14019236.html,parison of the eigenvalues of in (A9)(“x”)and the loci of the characteristic equations in (A8)(“o”),(19)(“+”),and in (A4)(“?”),with (a)the CPL of the buck dc–dc converter changed from 100W to 1000W and (b)the voltage loop gain k p u 2of the buck dc–dc converter changed from 0.2to

2.

https://www.wendangku.net/doc/8f14019236.html,parison of the eigenvalues of in (A9)(“x”)and the loci of the characteristic equations in (A8)(“o”),(19)(“+”),and in (A4)(“?”),with the NDO gain l 1changed from 1to 10.

A.Effect of the Boost DC–DC Converter on the System Stability

As seen from Fig.24,with the current loop gain k pi1of the dc–dc boost converter varies from 0.0005to 0.003,loci of the characteristic equation of the boost dc–dc converter in (A4)are

consistent with the eigenvalue trajectory of the characteristic matrix of the complete model in (A9).This means the dynamics of the dc-bus voltage control considering the full model under the variation of the dc–dc boost converter control parameters is similar to those for the boost converter control in (A4).There-fore,if the boost dc–dc converter control is designed properly,its effect on the dc-bus voltage control can be minimized,and the simpli?ed model in (19)can be used for the control scheme design.

B.Effect of the Buck DC–DC Converter on the System Stability

As shown in Fig.25(a),if the CPL of the buck dc–dc con-verter increased,the high-frequency loci of the characteristic equation of buck dc–dc converter in (A8)will move toward to the right,and the system will become more oscillatory with reduced damping,which have been validated in [5].Observing the eigenvalue trajectory of the characteristic matrix of the com-plete signal model in (A9),the same conclusion can be drawn.By comparison,the effect of the CPL on the dynamics of the dc-bus voltage control is similar to the buck dc–dc converter control system in (A8).Fig.25(b)shows the comparison when the voltage loop gain k pu2of the buck dc–dc converter changes from 0.2to 2.Both the variation trajectories denoted by “x”and “o”are consistent.Therefore,if the buck dc–dc converter con-trol is designed properly,its effect on the dc-bus voltage control can also be minimized,and the simpli?ed model in (19)can be used for the dc-bus control design.

C.Effect of the NDO on the System Stability

As seen from the loci comparison in Fig.26,if the gain l 1of the NDO has chosen to be too small,especially the triangle (denoted by “x”and “+”)and square (denoted by “x”and “?”)regions in the zoomed in part of Fig.26(b),the gain l 1of the NDO will affect the dynamics (not stability)of dc-bus voltage control and boost dc–dc control systems,e.g.,when a small gain (l 1=1)is used,the dc-bus voltage control becomes more oscillatory.On the other hand,if l 1is too large the system stability margin will be smaller with the poles moving toward the right.However,it is important to note that for the NDO design in Section III,to ensure the dynamic response of the observer is always faster than that of the feedback control system (l 1cannot be too small)and with the consideration that a too large l 1will cause saturation or noise during implementation,the gain l 1of the NDO also need to be design properly.As a result,this properly designed NDO gain should not affect the dc microgid stability margin and damping.

Through the analysis in this Appendix,it shows that as long as the NDO and dc/dc converter control are designed properly,the dc-bus voltage control system will have acceptable stability margin and good robustness against,and the simpli?ed analysis in Section III will be suf?cient for the design of the control scheme.However,if the detailed effects of dc/dc converter con-trol and the NDO design for the full system are desired,the methodology presented in the Appendix can be adopted.

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2012.

Chengshan Wang(SM’11)received the Ph.D.de-

gree in electrical engineering from Tianjin Univer-

sity,Tianjin,China,in1991.

He is currently a Professor with the School of

Electrical Engineering and Automation,Tianjin Uni-

versity.His current research interests include distribu-

tion system analysis and planning,distributed genera-

tion system and microgrid,and power system security

analysis.

Xialin Li was born in Hunan,China,in1986.He received the B.S.degree in electrical engineering in2009from Tianjin University,Tianjin,China, where he is currently working toward the Ph.D.de-gree in the Department of Electrical Engineering and Automation.

His current research interests include stability and

control of the distributed generations and

microgrids.

Li Guo(M’11)received the B.Sc.and Ph.D.degrees in electrical engineering from South China Univer-sity of Technology,Guangdong,China,in2002and 2007,respectively.

He is currently an Associate Professor at Tian-jin University,Tianjin,China.His current research interests include the optimal planning and design of microgrid,the coordinated operating strategy of microgrid,and the advanced energy management

system.

Yun Wei Li(S’04–M’05–SM’11)received the B.Sc.

degree in electrical engineering from Tianjin Univer-

sity,Tianjin,China,in2002,and the Ph.D.degree

from Nanyang Technological University,Singapore,

in2006.

In2005,Dr.Li was a Visiting Scholar with Aal-

borg University,Denmark.From2006to2007,he

was a Postdoctoral Research Fellow at Ryerson Uni-

versity,Canada.In2007,he worked at Rockwell Au-

tomation Canada and later joined the Department of

Electrical and Computer Engineering,University of

Alberta,Canada,in the same year.He is currently an Associate Professor at the

University of Alberta,Edmonton,Canada.His current research interests include

distributed generation,microgrid,renewable energy,high-power converters,and

electric motor drives.

Dr.Li is currently an Associate Editor for the IEEE T RANSACTIONS ON

P OWER E LECTRONICS and the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRON-ICS.He was also a Guest Editor for the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS Special Session on Distributed Generation and Microgrids.He

received the2013Richard M.Bass Outstanding Young Power Electronics En-

gineer Award from the IEEE Power Electronics Society.

变电所母线桥的动稳定校验

变电所母线桥的动稳定校验 随着用电负荷的快速增长,许多变电所都对主变进行了增容,并对相关设备进行了调换和校验,但往往会忽视主变母线桥的动稳定校验,事实上此项工作非常重要。当主变增容后,由于阻抗发生了变化,短路电流将会增大许多,一旦发生短路,产生的电动力有可能会对母线桥产生破坏。特别是户内母线桥由于安装时受地理位置的限制,绝缘子间的跨距较长,受到破坏的可能性更大,所以应加强此项工作。 下面以我局35kV/10kv胡店变电所#2主变增容为例来谈谈如何进行主变母线桥的动稳定校验和校验中应注意的问题。 1短路电流计算 图1为胡店变电所的系统主接线图。(略) 已知#1主变容量为10000kVA,短路电压为7.42%,#2主变容量为12500kVA,短路电压为7.48%(增容前短路电压为7.73%)。 取系统基准容量为100MVA,则#1主变短路电压标么值 X1=7.42/100×100×1000/10000=0.742, #2主变短路电压标么值 X2=7.48/100×100×1000/12500=0.5984 胡店变电所最大运行方式系统到35kV母线上的电抗标么值为0.2778。 ∴#1主变与#2主变的并联电抗为: X12=X1×X2/(X1+X2)=0.33125; 最大运行方式下系统到10kV母线上的组合电抗为: X=0.2778+0.33125=0.60875

∴10kV母线上的三相短路电流为:Id=100000/0.60875*√3*10.5,冲击电流:I sh=2.55I =23032.875A。 d 2动稳定校验 (1)10kV母线桥的动稳定校验: 进行母线桥动稳定校验应注意以下两点: ①电动力的计算,经过对外边相所受的力,中间相所受的力以及三相和二相电动力进行比较,三相短路时中间相所受的力最大,所以计算时必须以此为依据。 ②母线及其支架都具有弹性和质量,组成一弹性系统,所以应计算应力系数,计及共振的影响。根据以上两点,校验过程如下: 已知母线桥为8×80mm2的铝排,相间中心线间距离为210mm,先计算应力系数: ∵频率系数N f=3.56,弹性模量E=7×10.7 Pa,单位长度铝排质量M=1.568kg/m,绝缘子间跨距2m,则一阶固有频率: f’=(N f/L2)*√(EI/M)=110Hz 查表可得动态应力系数β=1.3。 ∴单位长度铝排所受的电动力为: f ph=1.73×10-7I sh2/a×β=568.1N/m ∵三相铝排水平布置,∴截面系数W=bh2/6=85333mm3,根据铝排的最大应力可确定绝缘子间允许的最大跨距为: L MAX=√10*σal*W/ f ph=3.24m ∵胡店变主变母线桥绝缘子间最大跨距为2m,小于绝缘子间的最大允许跨距。

华师秋《高等数学文》在线作业

华师16秋《高等数学(文)》在线作业

————————————————————————————————作者:————————————————————————————————日期:

一、单选题(共 20 道试题,共 40 分。) V 1. y=xsin3x,则y=( )。 . (-os3x+3sin3x)x . (sin3x+3xos3x)x . (os3x+sin3x)x . (sin3x+xos3x)x 标准答案: 2. f(x)在某点连续是f(x)在该点可微的() . 充分条件 . 必要条件 . 充分必要条件 . 既非充分又非必要条件 标准答案: 3. x→5时,函数|x-5|/(x-5)的极限是() . 0 . ∞ . 1 . 不存在 标准答案: 4. 当x→0时,ln(1+x)与x比较是()。 . 高阶无穷小量 . 等价无穷小量 . 非等价的同阶无穷小量 . 低阶无穷小量 标准答案: 5. 当x→0时,下列变量为无穷大量的是()。 . xsinx . sinx/x . ^x . (1+sinx)/x 标准答案: 6. 极值反映的是函数的()性质。 . 局部 . 全体 . 单调增加 . 单调减少 标准答案: 7. ()是函数f(x)=1/2x的原函数。 . F(x)=ln2x . F(x)=-1/x^2 . F(x)=ln(2+x) . F(x)=lnx/2 标准答案: 8. 若f(x)是奇函数,g(x)是偶函数,且f[g(x)]有意义,则f[g(x)]是()

. 奇函数 . 非奇非偶函数 . 偶函数或奇函数 标准答案: 9. 曲线y=(4+x)/(4-x)在点(2,3)的切线的斜率是()。 . 2 . -2 . 1 . -1 标准答案: 10. 曲线y=f(x)在点(x0,f(x0))的切线存在是函数y=f(x)在x0处可导的 . 充分条件 . 必要条件 . 充分必要条件 . 既非充分又非必要条件 标准答案: 11. 如果函数f(x)的定义域为(-1,0),则下列函数中,()的定义域为(0,1). f(1-x) . f(x-1) . f(x+1) . f(x2-1) 标准答案: 12. 偶函数的定义域一定是( )。 . 包含原点的区间 . 关于原点对称 . (-∞,+∞) . 以上说法都不对 标准答案: 13. 函数y=x^2+1在区间[-2,1]上的最大值是()。 . 1 . 2 . 5 . 不存在 标准答案: 14. 设函数f(x)=|x|,则函数在点x=0处() . 连续且可导 . 连续且可微 . 连续不可导 . 不连续不可微 标准答案: 15. 曲线y=xlnx-x在x=处的切线方程是()。 . y=-x- . y=x-

母线电动力及动热稳定性计算

母线电动力及动热稳定性计算 1 目的和范围 本文档为电气产品的母线电动力、动稳定、热稳定计算指导文件,作为产品结构设计安全指导文件的方案设计阶段指导文件,用于母线电动力、动稳定性、热稳定性计算的选型指导。 2 参加文件 表1 3 术语和缩略语 表2 4 母线电动力、动稳定、热稳定计算 4.1 载流导体的电动力计算 4.1.1 同一平面内圆细导体上的电动力计算

? 当同一平面内导体1l 和2l 分别流过1I 和2I 电流时(见图1),导体1l 上的电动力计 算 h F K I I 4210 π μ= 式中 F ——导体1l 上的电动力(N ) 0μ——真空磁导率,m H 60104.0-?=πμ; 1I 、2I ——流过导体1l 和2l 的电流(A ); h K ——回路系数,见表1。 图1 圆细导体上的电动力 表1 回路系数h K 表 两导体相互位置及示意图 h K 平 行 21l l = ∞=1l 时,a l K h 2= ∞≠1l 时,?? ? ???-+=l a l a a l K h 2)(12 21l l ≠ 22 2) ()(1l a m l a l a K h ++-+= 22)()1(l a m +-- l a m =

? 当导体1l 和2l 分别流过1I 和2I 电流时,沿1l 导体任意单位长度上各点的电动力计 算 f 124K f I I d μ= π 式中 f ——1l 导体任意单位长度上的电动力(m N ); f K ——与同一平面内两导体的长度和相互位置有关的系数,见表2。 表2 f K 系数表

4.1.2 两平行矩形截面导体上的电动力计算 两矩形导体(母线)在b <<a ,且b >>h 的情况下,其单位长度上的电动力F 的 计算见表3。 当矩形导体的b 与a 和h 的尺寸相比不可忽略时,可按下式计算 712 210x L F I I K a -=? 式中 F -两导体相互作用的电动力,N ; L -母线支承点间的距离,m ; a -导体间距,m ; 1I 、2I -流过两个矩形母线的电流,A ; x K -导体截面形状系数; 表3 两矩形导体单位长度上的电动力 4.1.3 三相母线短路时的电动力计算

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(续表)

(续表) (续表)

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