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74LVTH16245ADLRG4中文资料

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FEATURES

SN54LVTH16245A...WD PACKAGE

SN74LVTH16245A...DGG, DGV, OR DL PACKAGE

(TOP VIEW)

123456789101112131415161718192021222324

484746454443424140393837363534333231302928272625

1DIR 1B11B2GND 1B31B4V CC 1B51B6GND 1B71B82B12B2GND 2B32B4V CC 2B52B6GND 2B72B82DIR

1OE 1A11A2GND 1A31A4V CC 1A51A6GND 1A71A82A12A2GND 2A32A4V CC 2A52A6GND 2A72A82OE

DESCRIPTION/ORDERING INFORMATION

SN54LVTH16245A,SN74LVTH16245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS143Q–MAY 1992–REVISED OCTOBER 2005

?Members of the Texas Instruments Widebus?Family

State-of-the-Art Advanced BiCMOS

Technology (ABT)Design for 3.3-V Operation and Low Static-Power Dissipation

?Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V CC )?Support Unregulated Battery Operation Down to 2.7V

?Typical V OLP (Output Ground Bounce)<0.8V at V CC =3.3V,T A =25°C

?Distributed V CC and GND Pins Minimize High-Speed Switching Noise

?Flow-Through Architecture Optimizes PCB Layout

?I off and Power-Up 3-State Support Hot Insertion

?Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

?Latch-Up Performance Exceeds 500mA Per JESD 17

ESD Protection Exceeds JESD 22

–2000-V Human-Body Model (A114-A)–200-V Machine Model (A115-A)

ORDERING INFORMATION

T A

PACKAGE (1)

ORDERABLE PART NUMBER TOP-SIDE MARKING FBGA –GRD

SN74LVTH16245AGRDR Tape and reel LL245A FBGA –ZRD (Pb-free)SN74LVTH16245AZRDR 74LVTH16245ADLG4SSOP –DL

Tape and reel

LVTH16245A

74LVTH16245ADLRG4SN74LVTH16245ADGGR

–40°C to 85°C

TSSOP –DGG

Tape and reel

74LVTH16245ADGGRE4LVTH16245A

74LVTH16245ADGGRG4

SN74LVTH16245ADGVR TVSOP –DGV Tape and reel LL245A 74LVTH16245ADGVRE4VFBGA –GQL

SN74LVTH16245AKR Tape and reel LL245A

VFBGA –ZQL (Pb-free)

74LVTH16245AZQLR –55°C to 125°C CFP –WD

Tube

SNJ54LVTH16245AWD

SNJ54LVTH16245AWD (1)

Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at https://www.wendangku.net/doc/8f14576069.html,/sc/package.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

GQL OR ZQL PACKAGE

(TOP VIEW)

J H G F E D C B A 213465K

SN54LVTH16245A,SN74LVTH16245A

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS143Q–MAY 1992–REVISED OCTOBER 2005

The 'LVTH16245A devices are 16-bit (dual-octal)noninverting 3-state transceivers designed for low-voltage (3.3-V)V CC operation,but with the capability to provide a TTL interface to a 5-V system environment.

The devices are designed for asynchronous communication between two data buses.The logic levels of the direction-control (DIR)input and the output-enable (OE)input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode.The device transmits data from the A bus to the B bus when the B-port outputs are activated,and from the B bus to the A bus when the A-port outputs are activated.The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ .

Active bus-hold circuitry holds unused or undriven inputs at a valid logic https://www.wendangku.net/doc/8f14576069.html,e of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V CC is between 0and 1.5V,the devices are in the high-impedance state during power up or power down.However,to ensure the high-impedance state above 1.5V,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I off and power-up 3-state.The I off circuitry disables the outputs,preventing damaging current backflow through the devices when they are powered down.The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,which prevents driver conflict.

TERMINAL ASSIGNMENTS (1)(56-Ball GQL/ZQL Package)

23456A 1DIR NC NC NC NC 1OE B 1B21B1GND GND 1A11A2C 1B41B3V CC V CC 1A31A4D 1B61B5GND

GND

1A51A6E 1B81B71A71A8F 2B12B22A22A1G 2B32B4GND GND 2A42A3H 2B52B6V CC V CC 2A62A5J 2B72B8GND GND 2A82A7K

2DIR

2OE

(1)NC –No internal connection

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GRD OR ZRD PACKAGE

(TOP VIEW)

H G F E D C B A 21346

5To Seven Other Channels 1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

SN54LVTH16245A,SN74LVTH16245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS143Q–MAY 1992–REVISED OCTOBER 2005

TERMINAL ASSIGNMENTS (1)

(54-Ball GRD/ZRD Package)

23456A 1B1NC 1DIR 1OE NC 1A1B 1B31B2NC NC 1A21A3C 1B51B4V CC V CC 1A41A5D 1B71B6GND GND 1A61A7E 2B11B8GND GND 1A82A1F 2B32B2GND GND 2A22A3G 2B52B4V CC V CC 2A42A5H 2B72B6NC NC 2A62A7J

2B8

2DIR

2OE

2A8

(1)NC –No internal connection

FUNCTION TABLE (1)(EACH 8-BIT SECTION)

CONTROL OUTPUT CIRCUITS

INPUTS OPERATION

OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus

H X

Hi-Z

Isolation

(1)

Input circuits of the data I/Os always are active.

LOGIC DIAGRAM (POSITIVE LOGIC)

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Absolute Maximum Ratings (1)

Recommended Operating Conditions (1)

SN54LVTH16245A,SN74LVTH16245A

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS143Q–MAY 1992–REVISED OCTOBER 2005

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT V CC Supply voltage range –0.5 4.6V V I Input voltage range (2)

–0.57V V O Voltage range applied to any output in the high-impedance or power-off state (2)–0.57

V V O Voltage range applied to any output in the high state (2)–0.5

V CC +0.5

V SN54LVTH16245A 96I O Current into any output in the low state mA SN74LVTH16245A 128SN54LVTH16245A 48I O Current into any output in the high state (3)mA SN74LVTH16245A 64I IK Input clamp current V I <0–50mA I OK

Output clamp current

V O <0–50mA

DGG package 70DGV package

58θJA

Package thermal impedance (4)

DL package 63°C/W

GQL/ZQL package 42GRD/ZRD package

36T stg Storage temperature range

–65150

°C

(1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3)This current flows only when the output is in the high state and V O >V CC .(4)

The package thermal impedance is calculated in accordance with JESD 51-7.

SN54LVTH16245A

SN74LVTH16245A

UNIT MIN

MAX MIN MAX V CC Supply voltage 2.7 3.6

2.7

3.6

V V IH High-level input voltage 2

V V IL Low-level input voltage 0.80.8V V I Input voltage

5.5 5.5V I OH High-level output current –24–32mA I OL Low-level output current 4864mA ?t/?v Input transition rise or fall rate Outputs enabled

10ns/V ?t/?V CC Power-up ramp rate

200200μs/V T A Operating free-air temperature

–55

125

–40

°C

(1)

All unused control inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.

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Electrical Characteristics

SN54LVTH16245A,SN74LVTH16245A 3.3-V ABT16-BIT BUS TRANSCEIVERS

WITH3-STATE OUTPUTS SCBS143Q–MAY1992–REVISED OCTOBER2005

over recommended operating free-air temperature range(unless otherwise noted)

SN54LVTH16245A SN74LVTH16245A PARAMETER TEST CONDITIONS UNIT

MIN TYP(1)MAX MIN TYP(1)MAX

V IK V CC=2.7V,I I=–18mA–1.2–1.2V

V CC=2.7V to3.6V,I OH=–100μA V CC–0.2V CC–0.2

V CC=2.7V,I OH=–8mA 2.4 2.4

V OH V

I OH=–24mA2

V CC=3V

I OH=–32mA2

I OL=100μA0.20.2

V CC=2.7V

I OL=24mA0.50.5

I OL=16mA0.40.4

V OL V

I OL=32mA0.50.5

V CC=3V

I OL=48mA0.55

I OL=64mA0.55

V CC=3.6V,V I=V CC or GND±1±1 Control

inputs V

=0or3.6V,V I=5.5V1010

I I V I=5.5V2020μA

A or B

V CC=3.6V V I=V CC55 port(2)

V I=0–5–5

I off V CC=0,V I or V O=0to4.5V±100μA

V I=0.8V7575

V CC=3V

A or

B V I=2V–75–75

I I(hold)μA

port500

V CC=3.6V,(3)V I=0to3.6V

–750

V CC=0to1.5V,V O=0.5V to3V,

I OZPU±100(4)±100μA

OE=don't care

V CC=1.5V to0,V O=0.5V to3V,

I OZPD±100(4)±100μA

OE=don't care

Outputs high0.190.19

V CC=3.6V,

I CC I O=0,Outputs low55mA

V I=V CC or GND Outputs disabled0.190.19

V CC=3V to3.6V,One input at V CC–0.6V,

?I CC(5)0.20.2mA Other inputs at V CC or GND

C i V I=3V or044pF

C io V O=3V or01010pF

(1)All typical values are at V CC=3.3V,T A=25°C.

(2)Unused pins at V CC or GND

(3)This is the bus-hold maximum dynamic current.It is the minimum overdrive current required to switch the input from one state to

another.

(4)On products compliant to MIL-PRF-38535,this parameter is not production tested.

(5)This is the increase in supply current for each input that is at the specified TTL voltage level,rather than V CC or GND.

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Switching Characteristics

SN54LVTH16245A,SN74LVTH16245A

3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS143Q–MAY 1992–REVISED OCTOBER 2005

over recommended operating free-air temperature range,C L =50pF (unless otherwise noted)(see Figure 1)

SN54LVTH16245A

SN74LVTH16245A FROM TO V CC =3.3V V CC =3.3V PARAMETER

V CC =2.7V V CC =2.7V UNIT

(INPUT)

(OUTPUT)

±0.3V ±0.3V MIN

MAX MIN

MAX MIN TYP (1)MAX MIN

MAX t PLH 0.5 4.5 4.6 1.5 2.3 3.3 3.7A or B B or A ns t PHL 0.5 4.4 3.9 1.3 2.1 3.3 3.5t PZH 0.5 6.5 6.6 1.5 2.8 4.5 5.3OE A or B ns t PZL 0.5 5.4 6.2 1.6 2.9 4.6 5.2t PHZ 1 6.87 2.3 3.7 5.1 5.5OE

A or B

ns t PLZ 1

6.2

6.3

2.2

3.5

5.1 5.4t sk(o)

0.5

(1)

All typical values are at V CC =3.3V,T A =25°C.

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PARAMETER MEASUREMENT INFORMATION

From Output Under Test

C L LOA

D CIRCUIT

Open Data Input

Timing Input

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

Input

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS PULSE DURATION

V OH

V OL

2.7 V

0 V Input

Output Control

Output Waveform 1S1 at 6 V (see Note B)

Output Waveform 2S1 at GND (see Note B)

V OL

V OH 3 V

0 V

≈0 V

2.7 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING

Output

t PLH /t PHL t PLZ /t PZL t PHZ /t PZH

Open 6 V GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

D.The outputs are measured one at a time, with one transition per measurement.

SN54LVTH16245A,SN74LVTH16245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS143Q–MAY 1992–REVISED OCTOBER 2005

Figure 1.Load Circuit and Voltage Waveforms

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PACKAGING INFORMATION

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

5962-9668601QXA ACTIVE CFP WD481TBD Call TI Level-NC-NC-NC 5962-9668601VXA ACTIVE CFP WD481TBD Call TI Level-NC-NC-NC

74LVTH16245ADGGRE4ACTIVE TSSOP DGG482000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVTH16245ADGGRG4ACTIVE TSSOP DGG482000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVTH16245ADGVRE4ACTIVE TVSOP DGV482000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVTH16245ADLG4ACTIVE SSOP DL4825Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVTH16245ADLRG4ACTIVE SSOP DL481000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVTH16245ADGGR ACTIVE TSSOP DGG482000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVTH16245ADGVR ACTIVE TVSOP DGV482000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVTH16245ADL ACTIVE SSOP DL4825Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVTH16245ADLR ACTIVE SSOP DL481000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM SN74LVTH16245AGQLR ACTIVE VFBGA GQL561000TBD SNPB Level-1-240C-UNLIM SN74LVTH16245AGRDR ACTIVE LFBGA GRD541000TBD SNPB Level-1-240C-UNLIM SN74LVTH16245AZQLR ACTIVE VFBGA ZQL561000Green(RoHS&

no Sb/Br)

SNAGCU Level-1-260C-UNLIM

SN74LVTH16245AZRDR ACTIVE LFBGA ZRD541000Green(RoHS&

no Sb/Br)

SNAGCU Level-1-260C-UNLIM SNJ54LVTH16245AWD ACTIVE CFP WD481TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check https://www.wendangku.net/doc/8f14576069.html,/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI

to Customer on an annual basis.

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

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