Small-Scale Reconfigurability for Improved Performance and Double-Precision in Graphics Har

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Small-Scale Recon?gurability for Improved Performance and Double-Precision in Graphics Hardware

Kevin Dale?,Jeremy W.Shea?er?,Vinu Vijay Kumar?,David P.Luebke?,

Greg Humphreys?,and Kevin Skadron?

(submitted for review on November30,2006)

We explore the application of Small-Scale Recon?gurability(SSR)to graphics hardware.SSR is an architectural technique wherein functionality common to multiple subunits is reused rather than replicated,yielding high-performance recon?gurable hardware with reduced area requirements(Vi-jay Kumar and Lach2003).We show that SSR can be used e?ectively in programmable graphics architectures to allow double-precision computation without a?ecting the performance of single-precision calculations and to increase fragment shader performance with a minimal impact on chip area.

1Introduction

Every hardware system makes a tradeo?between performance and?exibility. At one end of the spectrum,general purpose processors provide maximum ?exibility at the expense of performance,area,power consumption,and price. Custom ASICs are the other extreme,providing maximum performance at a minimum cost,albeit for only a very narrow set of applications.

Modern graphics hardware requires both high performance and?exibility, placing it somewhere between these two extremes.Traditional intermediate hardware solutions like FPGAs are inappropriate for graphics processors be-cause of their large size and low performance relative to their?xed-logic coun-terparts.Small-scale recon?gurability(SSR)provides an attractive compro-mise;systems that use SSR components can approach the high speed and small size of ASICs while providing some specialized con?gurability(Vijay Kumar and Lach2003).In this paper,we explore the applicability of SSR to pro-grammable graphics hardware.

The simplest example of a recon?gurable component is two fully functional components connected with a multiplexer(see Fig.1).Although these two ?University of Virginia,{kdale,jws9c,vv6v,humper,skadron}@https://www.wendangku.net/doc/8316305976.html,

?NVIDIA Research,david@https://www.wendangku.net/doc/8316305976.html,

2SSR for Improved Performance and Double-Precision in Graphics Hardware

A B C D

A B

E F MUX

(a)Na¨?ve recon?gurable hardware

A B

C D E F

MUX

(b)A more e?cient solution

Figure1.A na¨?ve implementation of recon?gurable hardware can be built by simply multiplexing between two distinct,unmodi?ed units(a),but a more e?cient design would reuse common

substructure to avoid replication(b).

components are disjoint,in typical usage they will contain substantially sim-ilar redundant substructures,which is precisely the situation in which SSR performs best.Rather than replicate all of the redundant structure,one can instead reuse common substructure,and do so at a?ne granularity within a single component(Vijay Kumar and Lach2003,Chiricescu et al.2002).

A common SSR unit is the morphable multiplier.These multiplier-adders can be recon?gured into a multiplier or an adder in a single cycle.When used to create?xed-point units,morphable multipliers yield a nearly17%reduc-tion in total area when compared to the sum of the sizes of their constituent parts(Chiricescu et al.2002).

Graphics processors,like specialized multimedia processors and DSPs,are a particularly suitable target for SSR due to their vector-processor like oper-ations.When the same operation is performed repeatedly in SIMD fashion, recon?guration and its associated overhead is infrequently needed,and any cost can be amortized over many instructions.Furthermore,SSR-based com-ponents typically have lower static power requirements because less hardware goes unused.

2Related Work

Dynamically recon?gurable hardware has been a popular topic in recent com-puter architecture literature,especially in the FPGA and recon?gurable com-puting communities.The con?gurability of these systems serves myriad design

Dale et.al3 goals,among them improved performance,power,area,and fault tolerance characteristics.

Even et al.(1997)describe a dual mode IEEE multiplier—a pipelined unit capable of producing one double-precision or two single-precision multiplica-tions every clock cycle with a three cycle latency.The authors argue that the reuse of substructure yields a cheap device that performs well for both precisions.They further claim that the single precision mode is particularly useful for SIMD applications,like graphics,because it is conducive to systems on which the same operation is regularly repeated on large numbers of data points.

Guerra et al.(1998)explore built-in-self-repair(BISR)and its application to fault tolerance,manufacturability,and application-speci?c programmable processor design.Previous work in the area of dynamic repair had made use of specialized redundant units to replace damaged units;their paper describes the synthesis of more general units that can replace any of several units on a chip when damage is detected.The authors coin the term HBISR(heterogeneous BISR)for the technique.

A morphable multiplier is a device capable of performing either a?xed point multiply or add using the same hardware structure(Chiricescu et al.2002). Morphable multipliers require less area than the sum of the area needed for a separate multiplier and adder(in fact,they require only slightly more than a multiplier alone),while imposing negligible performance penalties.

Metrics like area,performance,and power are easily quanti?ed,but it is less obvious how to measure the increasingly important metric of hardware?https://www.wendangku.net/doc/8316305976.html,pton and Hauck have de?ned a testing method and quanti?cation metric for?exibility of recon?gurable hardware(Compton and Hauck2004). Other examples of relevant research in recon?gurable hardware include Kim et al.(1997),Chiou et al.(2005).

The work in this paper makes use of Brook(Buck et al.2004),a stream-based programming language which allows the programmer to write general-purpose applications for a GPU without worrying about the sometimes byzantine de-tails of GPU programming.Our experiments all use Chromium(Humphreys et al.2002)to intercept and analyze streams of graphics commands made by real applications.The primary advantage of using Chromium is that we ensure that our workloads are not contrived.Although we use Brook and Chromium without modi?cation,we have enhanced the Qsilver graphics architectural simulator(Shea?er et al.2004,2005)to model the necessary aspects of the fragment pipeline.A detailed description of our modi?cations to Qsilver and our experimental setup are presented in Sect.3and Sect.4.

4SSR for Improved Performance and Double-Precision in Graphics Hardware

Fragment processor

Stage 2

Stage 1 (+ Texture)

Branch Processor

Rasterizer

(a)Fragment processor

Crossbar

MUL

MUL

MUL

MUL

Texture Operations

SFU

(b)Stage1

ADD

ADD

ADD

ADD

Crossbar

Crossbar

SFU

MUL

MUL

MUL

MUL

Crossbar

(c)Stage2

Figure2.Baseline fragment units used for comparison.Stage2can take up to three4-channel operands,one of which directly feeds the ADD units and whose data path is represented here by dashed lines.Note the additional data paths that cascade the ADD units;these allow for a

single-pass dot product(Seifert2004).

3Simulation Setup

3.1The Qsilver Simulator

Qsilver is a simulation framework for graphics architectures that can simu-late low-level GPU activity for any existing OpenGL application(Shea?er et al.2004).Qsilver uses Chromium(Humphreys et al.2002)to intercept and transform an OpenGL application’s API calls and create an annotated trace that encapsulates geometry,timing,and state information.This trace serves as input to the Qsilver simulator core,which performs an accurate timing simulation of the graphics hardware and produces detailed statistics. Qsilver is con?gured at runtime with a description of its pipeline.In these experiments we simulate an NV4x-like architecture,with a pipeline con?gura-tion similar to that of NVIDIA’s6800GT,so we con?gure Qsilver to model a system with6vertex pipelines and16fragment pipelines.The fragments are tiled in blocks of2×2,so we e?ectively have4tile pipelines,each of which can process4fragments simultaneously.NV4x GPUs use a similar tiled con?guration in the fragment engine(Kilgari?and Fernando2005).

To account for modi?cations to the fragment pipeline,we enhanced Qsilver to track fragment shader activity.Our modi?ed Qsilver simulator stores a per-triangle identi?er which uniquely speci?es which,if any,fragment shader was bound when that triangle was being rendered.We also store the text of the fragment shaders so that they can be analyzed by the Qsilver simulator core.

Dale et.al5 3.2Baseline Architecture

Both of the following experiments hold?xed the graphics pipeline described above and focus on the programmable path of the fragment engine.While the NV4x vertex engine follows a MIMD architecture,its fragment engine is truly SIMD in nature.Additionally,in many modern games the majority of fragments are shaded by fragment programs(see Fig.3),so we focus our e?orts on the programmable path in the fragment engine.

Our baseline fragment pipeline,depicted in Fig.2,is similar to that found in NV4x GPUs1.A single fragment unit contains two stages;four-channel frag-ments(RGBA)reach stage1from either the rasterizer or fragment pipeline loopback.Stage2can execute instructions in parallel with stage1in dual-issue mode as well sequentially,taking its operands from the output of stage 1.Crossbars route operands to the appropriate functional units,and Special Function Units(SFUs)are used to perform special scalar operations like re-ciprocal square root.The fragment units can also operate in co-issue mode, whereby a single4-channel data path functions as two distinct data paths, with independent instructions executing in parallel,on the same unit,across these two data paths—e.g.,a3-vector and a scalar,or two2-vectors(Kilgari?and Fernando2005).

NVShaderPerf2—a utility that displays shader scheduling information for NVIDIA hardware—is used to schedule programs for our baseline architec-ture.While NV4x GPUs have dedicated hardware for performing common half-precision operations in parallel with full-precision operations,none of the fragment programs tested included any half-precision operations.However,to be sure of a legitimate comparison of performance along the full-precision path, NVShaderPerf is con?gured to schedule programs for our NV4x-like architec-ture using the full-precision path only.

3.3Benchmarks

For benchmarking,we use the recent game Doom III(see Fig.3),as well as four demo programs included with the Brook distribution.We use Chromium to intercept the fragment programs used in each benchmark and to generate traces for simulation under Qsilver.Each benchmark,along with its fragment programs,is summarized below.

(i)doom3,a representative50-frame demo from the game.Includes a shader

for general per–pixel lighting and a special e?ects shader.

1Based on those details that have been made available to the public or indirectly obtained via patents and extensive benchmark tests(see Kilgari?and Fernando2005,Seifert2004,for additional details). 2Uni?ed compiler version77.80.

6SSR for Improved Performance and Double-Precision in Graphics Hardware

(a)(b)

Figure3.Screen captures from the doom3benchmark.On the left,the color of each pixel is modulated to indicate which fragment program generated it.The right image is the unmodi?ed rendering from the game.Notice that the majority of pixels are generated by programmable

fragment shaders.

(ii)bitonic sort,a parallel sorting network.Includes a main sorting kernel and simple pass-thru kernel.

(iii)image proc(25,25),an image convolution shader.Includes a main con-volution kernel and pass–thru kernel.

(iv)particle cloth(5,10,15),a cloth simulation.Includes six kernels that im-plement the simulation.

(v)volume division(100),a volume isosurface extractor.Includes ten ker-nels for various stages of the extraction.

4Experiments and Results

In this section,we describe two experiments we performed to validate our hy-pothesis that using SSR components in a modern GPU architecture can bene?t certain applications.We show improved performance across a set of test ap-plications with only a minimal impact on GPU die area and also demonstrate that double-precision?oating point capabilities can be added to the fragment pipeline without a?ecting the performance of single-precision applications. 4.1Increased Throughput

We?rst compared the simulated performance of the NV4x-like fragment pipeline to that of an SSR fragment pipeline architecture,whose fragment units are depicted in Fig.4.

Dale et.al7 Crossbar

FAC

FAC

FAC

FAC

Texture Operations

SFU (a)Stage1

FAC

FAC

FAC

FAC

Crossbar

Crossbar

SFU

FAC

FAC

FAC

FAC

Crossbar

(b)Stage2

Figure4.Proposed SSR fragment units for the?rst experiment.FAC modules are Flexible Arithmetic Units,and they replace each of the ADD and MUL units in our baseline architecture.

4.1.1Target SSR architecture.The fragment units in our target SSR ar-chitecture are similar to those in the baseline architecture;however,we replace both the multipliers and adders in stages1and2with single-precision Flexible Arithmetic Units(FACs).An FAC can be very quickly recon?gured to per-form either a multiplication or an addition and uses only slightly more gates than a multiplier.With current technology,these FACs can produce a result every cycle and can be recon?gured between cycles,assuming a400MHz clock and a two-stage pipeline(Vijay Kumar and Lach2003).Finally,in the?rst set of FACs in our SSR architecture,we duplicate the accumulate data paths from the baseline architecture’s ADD units.These data paths require a trivial amount of additional area overhead.

In addition to supporting all the existing functionality of our baseline units, the modi?ed SSR units provide new scheduling opportunities beyond those of the baseline.First,the baseline fragment pipe is only capable of performing a single full-precision4-vector addition per pass in stage2(Seifert2004),while the SSR pipeline is capable of performing three in one pass—one in stage1and two chained additions in stage2(see Fig.5a).Moreover,there is more freedom to schedule dot product and multiply-accumulate operations,both of which are extremely common in fragment programs.For example,the SSR pipeline can execute a32-bit3-channel dot product(DP3)and dependent scalar-vector multiplication—e.g.,the expression( a· b) c—in a single pass by computing the per-channel multiply of a and b in stage1,accumulating the channel products to obtain a· b in the?rst set of FACs in stage2,and performing a scalar-vector multiply in its second set of FACs(Fig.5b).Extending this scheduling approach to co-issue con?gurations is straightforward.

8SSR for Improved Performance and Double-Precision in Graphics Hardware Stage 2Stage 1 (+ Texture)FAC x 4 (1)FAC x 4 (3)FAC x 4 (2)+++

(a)Single-pass con?guration for multi-ple 4-vector additions.Stage 2

Stage 1 (+ Texture)

FAC x 4 (1)

FAC x 4 (3)

FAC x 4 (2)x x +(b)Single-pass con?guration to com-

pute ( a · b ) c .

Figure 5.Two example con?gurations that provide additional scheduling opportunities for the

SSR fragment pipeline.

4.1.2Shader analysis.Considering the additional scheduling opportunities provided by the SSR architecture,as well as the known scheduling constraints of NV4x GPUs,we hand-scheduled each fragment program for our SSR frag-ment engine.As was done for the fragment program schedules on the baseline architecture,we limited program schedules for the SSR architecture to the full-precision path as well.

With 16fragment pipelines and a 400Mz clock,both architectures have a maximum throughput of 6GP/s (gigapixels per second).This assumes a 1-cycle texture lookup.Results for the benchmarks and their constituent shaders are given in Table 1.For most of the shaders,the SSR architecture provides an improvement over the baseline.The amount of improvement of course varies from shader to shader,depending upon the mix of instructions and corre-sponding scheduling advantages for the SSR architecture.Frequent dot prod-uct and multiply-accumulate instructions across the benchmarks led to the performance improvements for the SSR architecture seen in Table 1.

4.1.3Full pipeline simulation.There are a number of possible bottlenecks in the full graphics pipeline,however,that can prevent performance improve-ments in the fragment engine core from being realized across the full pipeline.First,available memory bandwidth and cache performance in the texture units can prevent the pipeline from achieving maximum pixel throughput.GPUs typically incorporate a high degree of multithreading to hide the latency in-troduced by texture memory accesses.For example,when a shader unit arrives at a texture memory instruction,the memory access is initialized and the frag-

Dale et.al9 Table 1.Per-pixel execution time and pixel throughput,in megapixels per-second(MP/s),for the baseline and target fragment units,assuming a1-cycle texture lookup.

Benchmark Shader Execution time(cycles)Throughput(MP/s)

Baseline SSR Baseline SSR bitonic sort01514426.67457.14

1116400.006400.00 doom301211533.33581.82

177914.29914.29 image proc02826228.57246.15

1116400.006400.00 particle cloth0661066.671066.67

11615400.00426.67

21817355.56376.47

3108640.00800.00

4119581.82711.11

5223200.003200.00 volume division0223200.003200.00

1116400.006400.00

22220290.91320.00

33026213.33246.15

41916336.84400.00

55752112.28123.08

61513426.67492.31

71313492.31492.31

85652114.29123.08

9116400.006400.00 ment is temporarily banked until the memory operation is complete.A context switch occurs immediately,at which point the shader unit can continue doing useful work on another fragment’s thread.In a SIMD environment,the thread pool is su?ciently large to e?ectively hide memory latency in this manner, provided that there is also su?cient memory bandwidth and a large ratio of arithmetic instructions to memory instructions.While texture access patterns vary across the benchmarks included here,all of their shaders contain a large percentage of arithmetic instructions,enabling e?ective latency-hiding.Qsil-ver employs a simple probabilistic cache model that can reasonably capture this phenomenon(Shea?er et al.2004)in the full pipeline simulation.

The vertex processor can also be a system bottleneck,particularly for scenes with a large number of extremely small(in screen-space)polygons.However, for many GPGPU applications,and for all of those included in the suite of benchmarks here,the vertex processor is relatively inactive.A typical GPGPU application only renders screen-?lling quadrilaterals;this makes for an ex-tremely low polygon-to-fragment ratio and a nearly-idle vertex processor. Qsilver’s queue-based simulation architecture models the graphics pipeline at a resolution su?cient to capture the relative amounts of activity between the fragment and vertex engines.This is accomplished by aggregating architectural performance counter data across the course of the simulation.Counters for pre-transform-and-lighting vertex queues,as well as those for fragment creation,

10SSR for Improved Performance and Double-Precision in Graphics Hardware 0 0.2

0.4

0.6 0.8 1 0 100 200 300 400 500 600 700 800 900 1000

N o r m a l i z e d F u n c t i o n a l U n i t A c t i v i t y Tens of Thousands of Cycles

Vertex Processor Fragment Processor

Figure 6.Traces of pre-transform-and-lighting vertex queue writes and fragments created during a single frame of doom3,generated from Qsilver counter data.Fragment activity is at its maximum for a substantial portion of the frame,while vertex activity reaches its peak only once.This frame is representative of all frames across the doom3benchmark,indicating that the benchmark is

predominantly fragment-bound.

are among Qsilver’s counters.Full queues block earlier stages in the pipeline and so imply vertex-or fragment-bound behavior,respectively (Shea?er et al.2004).Fig.6was generated from these Qsilver counters and indicates that,like the Brook benchmarks,the Doom III benchmark is also predominantly fragment-bound.

For doom3,there is also the possibility that the ?xed-function path in the fragment engine is used almost exclusively,given that the benchmark only uses two shaders across the entire 50-frame trace.However,the game per-forms per-pixel lighting with a fragment shader for most objects in the game,using OpenGL ?xed-function lighting rarely.The 1-cycle improvement in this heavily-used shader should likely show a signi?cant performance increase over the entire pipeline as well.

Fig.7shows performance results from full-pipeline simulations under Qsil-ver,using the fragment program schedules discussed in the previous section.For all benchmarks,speedup over the entire graphics pipeline for the SSR ar-chitecture does indeed correspond with the fragment processor performance results in Table 1.This indicates that all benchmarks are su?ciently frag-ment processor-bound for the performance increase in the fragment units to translate to a corresponding improvement over the full pipeline.

Equally as important,based on conservative inverter-equivalent gate count

Dale et.al

11

Benchmark F u l l p i p e l i n e s p e e d u p Figure 7.Speedup for the target SSR architecture over the baseline for a full pipeline simulation

under Qsilver.

estimates 1,each FAC requires 12,338gates,only 710more than a single-precision multiplier (11,628gates).Replacing the adders (7,782gates)requires 4,556additional gates.This additionally requires the small overhead of a mul-tiplexer to con?gure the FACs.Given these gate estimates,with 16fragment pipelines,the cost of our proposed use of SSR is 382,464gates,which is less than 0.2%of the total area of NVIDIA’s 6800GT (an estimated 222million transistors(Medvedev and Budankov 2004)).

4.2Dual-Mode IEEE Adders and Multipliers

The GPGPU and scienti?c computing communities would like to have the ability to perform double-precision calculations on the GPU.Unfortunately for them,the gaming industry drives the graphics hardware industry,and games do not currently require double-precision.We present a method here that can satisfy the demands of the scienti?c community without compromising the performance of the single-precision path so crucial to video game performance.A dual-mode ?oating point unit is a small-scale recon?gurable unit capa-ble of performing two simultaneous single-precision operations or one double-precision operation.Dual-mode units can be fully pipelined to produce results every cycle.Like other SSR units,dual-mode multipliers and adders require internal multiplexers for path selection.Additionally,they require a rounding unit capable of ?exible rounding modes.The total additional structure for this modi?cation is insigni?cant (Even et al.1997).These units are also capable of operating at the modest 400MHz clock speed of our baseline architecture.1All area estimates are given in terms of inverter-equivalent gate area unless otherwise speci?ed.

12SSR for Improved Performance and Double-Precision in Graphics Hardware

4.2.1Target SSR architecture.We simulate a pipeline in Qsilver that uses dual-mode multipliers and adders in the fragment engine,where we replace pairs of single-precision FPUs in the baseline architecture with a single corre-sponding dual-mode FPU.This e?ectively gives us an8-wide double-precision fragment engine with approximately half the throughput of the single-precision con?guration.Double-precision con?guration also requires that we retask pairs of32-bit registers as single64-bit registers.With half as many fragment pipelines,each double-precision pipe has the same number of available64-bit registers as each single-precision pipe has32-bit registers(four32-bit registers per fragment in the case of NV4x GPUs(Kilgari?and Fernando2005)).By a similar argument,the bandwidth requirements for the memory and register bus systems in8-wide double-precision mode should not exceed those of the original16-wide single-precision con?guration.

We have conservative area estimates for a double-precision adder and mul-tiplier of13,456gates and37,056gates,respectively.The real overhead here comes from replacing each pair of single-precision FPUs with one dual-mode FPU,at an approximate cost of815,744gates over the entire fragment en-gine,or0.4%of the6800GT’s total area.Note that we have modi?ed only the multiplication and addition units,so additional precision is not available for specialized operations such as logarithms or square roots.Although many scienti?c applications would bene?t greatly from high precision addition and multiplication alone,a full double-precision arithmetic engine would be ideal. Dual-mode reciprocal,square-root,logarithm,and other specialized units are a topic for future exploration.

Table 2.Single-and double-precision GPGPU computations using SSR.Each application comes with the Brook distribution.The32-bit cycles row shows the GPU cycle count for our NV4x-like architecture.Note that these timings are identical whether we are using a dual-mode unit con?gured in single-precision mode or a dedicated single-precision unit.The64-bit cycles row shows the cycles required for double-precision after recon?guration.As expected,none of the programs takes more than twice as long with double-precision than with single-precision.

Benchmark bitonic sort image proc particle cloth volume division 32-bit cycles6201,25219,504254,923,418

64-bit cycles11772,44538,959509,846,783

32→64-bit speedup.527.512.501.500

4.2.2Full pipeline simulation.To validate our SSR-based graphics archi-tecture capable of both single-and double-precision,we traced the four Brook benchmarks through Qsilver.Results are summarized in Table2.This table lists the cycle counts for each application in both single-and double-precision modes.Note that the double-precision calculations never require more than twice as long as the corresponding single-precision calculation.Because the

Dale et.al13 timing results are identical for dual-mode units con?gured in single-precision mode and dedicated single-precision units,we have shown that by using SSR we can add double-precision addition and multiplication to the graph-ics pipeline with only a modest increase in gate count and without a?ecting the performance of the commonly-used single-precision path.

5Conclusions

We have extended Qsilver to record information on fragment program state in its annotated trace.Our modi?ed Qsilver core then uses this new informa-tion,along with fragment program listings and timing information,to model the programmable fragment engine of an NV4x-like architecture.With this framework in place,we have demonstrated the applicability of Small-Scale Recon?gurability to graphics architectures.We have shown that it is possible to increase the throughput of the fragment engine with only a small increase in die area.In addition,we have demonstrated that dual-mode multipliers and adders can provide double-precision in the fragment engine to support scien-ti?c computing in the GPGPU community with no detriment to the gamers who drive the market.The vector-like operations performed on GPUs make them a particularly good target for such techniques,since need for recon?gu-ration is rare in SIMD environments,and since the cost of recon?guration is amortized over many operations.

6Future Work

The fragment engine is one of many elements of the graphics pipeline.Ap-plications of SSR will likely yield similar performance improvements in other units as well.Another area of exploration that is likely to be fruitful for SSR is power consumption.Whenever portions of a chip are unused,they use no dynamic power,but they leak static power.By their very nature,SSR com-ponents are rarely idle,and should therefore leak a minimum of static power. Power leakage is currently a major issue with GPUs,and reducing leakage be-comes crucial as continuing improvements in chip manufacturing technology exacerbate this problem(Shea?er et al.2004).

7Acknowledgments

We would like to thank John Lach for his input on SSR and Peter Djeu for his collaboration on Chromium extensions.This work was funded by NSF grants CCF-0429765,CCR-0306404,and CCF-0205324.

14REFERENCES

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Vijay Kumar,V.and Lach,J.(2003),Designing,scheduling,and allocating?exible arithmetic components,in‘Proceedings of the International Conference on Field Programmable Logic and Applications’.

to与for的用法和区别

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延时子程序计算方法

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上表中e=-1的行（共11行）满足（2*R5*R6*R7+3*R5*R6+3*R5+3）=999，999 e=1的行（共2行）满足（2*R5*R6*R7+3*R5*R6+3*R5+3）=1，000，001 假如单片机晶振为12M，一个机器周期为10-6S，若要得到精确的延时一秒的子程序，则可以在之程序的Ret返回指令之前加一个机器周期为1的指令（比如nop指令）， data1,data2,data3选择e=-1的行。比如选择第一个e=-1行，则精确的延时一秒的子程序可以写成： delay:mov R5,#167 d1:mov R6,#171 d2:mov R7,#16 d3:djnz R7,d3 djnz R6,d2

djnz R5,d1 nop ；注意不要遗漏这一句 Ret 附： #include"iostReam.h" #include"math.h" int x=1,y=1,z=1,a,b,c,d,e(999989),f(0),g(0),i,j,k; void main() { foR(i=1;i<255;i++) { foR(j=1;j<255;j++) { foR(k=1;k<255;k++) { d=x*y*z*2+3*x*y+3*x+3-1000000; if(d==-1) { e=d;a=x;b=y;c=z; f++; cout<<"e="<

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For的用法 1. 表示“当作、作为”。如: I like some bread and milk for breakfast. 我喜欢把面包和牛奶作为早餐。 What will we have for supper? 我们晚餐吃什么? 2. 表示理由或原因,意为“因为、由于”。如: Thank you for helping me with my English. 谢谢你帮我学习英语。 3. 表示动作的对象或接受者,意为“给……”、“对…… (而言)”。如: Let me pick it up for you. 让我为你捡起来。 Watching TV too much is bad for your health. 看电视太多有害于你的健康。 4. 表示时间、距离,意为“计、达”。如: I usually do the running for an hour in the morning. 我早晨通常跑步一小时。 We will stay there for two days. 我们将在那里逗留两天。 5. 表示去向、目的,意为“向、往、取、买”等。如: Let’s go for a walk. 我们出去散步吧。 I came here for my schoolbag.我来这儿取书包。 I paid twenty yuan for the dictionary. 我花了20元买这本词典。 6. 表示所属关系或用途,意为“为、适于……的”。如: It’s time for school. 到上学的时间了。 Here is a letter for you. 这儿有你的一封信。 7. 表示“支持、赞成”。如: Are you for this plan or against it? 你是支持还是反对这个计划? 8. 用于一些固定搭配中。如: Who are you waiting for? 你在等谁? For example, Mr Green is a kind teacher. 比如,格林先生是一位心地善良的老师。 尽管for 的用法较多，但记住常用的几个就可以了。 to的用法: 一：表示相对，针对 be strange (common, new, familiar, peculiar) to This injection will make you immune to infection. 二：表示对比，比较 1：以-ior结尾的形容词，后接介词to表示比较，如：superior ,inferior,prior,senior,junior 2: 一些本身就含有比较或比拟意思的形容词，如equal，similar，equivalent，analogous A is similar to B in many ways.

曹操《短歌行》其二翻译及赏析

曹操《短歌行》其二翻译及赏析 引导语：曹操(155—220)，字孟德，小名阿瞒，《短歌行 二首》 是曹操以乐府古题创作的两首诗， 第一首诗表达了作者求贤若渴的心 态，第二首诗主要是曹操向内外臣僚及天下表明心迹。 短歌行 其二 曹操 周西伯昌，怀此圣德。 三分天下，而有其二。 修奉贡献，臣节不隆。 崇侯谗之，是以拘系。 后见赦原，赐之斧钺，得使征伐。 为仲尼所称，达及德行， 犹奉事殷，论叙其美。 齐桓之功，为霸之首。 九合诸侯，一匡天下。 一匡天下，不以兵车。 正而不谲，其德传称。 孔子所叹，并称夷吾，民受其恩。 赐与庙胙，命无下拜。 小白不敢尔，天威在颜咫尺。 晋文亦霸，躬奉天王。 受赐圭瓒，钜鬯彤弓， 卢弓矢千，虎贲三百人。 威服诸侯，师之所尊。 八方闻之，名亚齐桓。 翻译 姬昌受封为西伯，具有神智和美德。殷朝土地为三份，他有其中两分。 整治贡品来进奉，不失臣子的职责。只因为崇侯进谗言，而受冤拘禁。 后因为送礼而赦免， 受赐斧钺征伐的权利。 他被孔丘称赞， 品德高尚地位显。 始终臣服殷朝帝王，美名后世流传遍。齐桓公拥周建立功业，存亡继绝为霸 首。

聚合诸侯捍卫中原，匡正天下功业千秋。号令诸侯以匡周室，主要靠的不是 武力。 行为磊落不欺诈，美德流传于身后。孔子赞美齐桓公，也称赞管仲。 百姓深受恩惠，天子赐肉与桓公，命其无拜来接受。桓公称小白不敢，天子 威严就在咫尺前。 晋文公继承来称霸，亲身尊奉周天王。周天子赏赐丰厚，仪式隆重。 接受玉器和美酒，弓矢武士三百名。晋文公声望镇诸侯，从其风者受尊重。 威名八方全传遍，名声仅次于齐桓公。佯称周王巡狩，招其天子到河阳，因 此大众议论纷纷。 赏析 《短歌行》 (“周西伯昌”)主要是曹操向内外臣僚及天下表明心 迹，当他翦灭群凶之际，功高震主之时，正所谓“君子终日乾乾，夕惕若 厉”者，但东吴孙权却瞅准时机竟上表大说天命而称臣，意在促曹操代汉 而使其失去“挟天子以令诸侯”之号召， 故曹操机敏地认识到“ 是儿欲据吾著炉上郁!”故曹操运筹谋略而赋此《短歌行 ·周西伯 昌》。 西伯姬昌在纣朝三分天下有其二的大好形势下， 犹能奉事殷纣， 故孔子盛称 “周之德， 其可谓至德也已矣。 ”但纣王亲信崇侯虎仍不免在纣王前 还要谗毁文王，并拘系于羑里。曹操举此史实，意在表明自己正在克心效法先圣 西伯姬昌，并肯定他的所作所为，谨慎惕惧，向来无愧于献帝之所赏。 并大谈西伯姬昌、齐桓公、晋文公皆曾受命“专使征伐”。而当 今天下时势与当年的西伯、齐桓、晋文之际颇相类似，天子如命他“专使 征伐”以讨不臣，乃英明之举。但他亦效西伯之德，重齐桓之功，戒晋文 之诈。然故作谦恭之辞耳，又谁知岂无更讨封赏之意乎 ?不然建安十八年(公元 213 年)五月献帝下诏曰《册魏公九锡文》，其文曰“朕闻先王并建明德， 胙之以土，分之以民，崇其宠章，备其礼物，所以藩卫王室、左右厥世也。其在 周成，管、蔡不静，惩难念功，乃使邵康公赐齐太公履，东至于海，西至于河， 南至于穆陵，北至于无棣，五侯九伯，实得征之。 世祚太师，以表东海。爰及襄王，亦有楚人不供王职，又命晋文登为侯伯， 锡以二辂、虎贲、斧钺、禾巨 鬯、弓矢，大启南阳，世作盟主。故周室之不坏， 系二国是赖。”又“今以冀州之河东、河内、魏郡、赵国、中山、常 山，巨鹿、安平、甘陵、平原凡十郡，封君为魏公。锡君玄土，苴以白茅，爰契 尔龟。”又“加君九锡，其敬听朕命。” 观汉献帝下诏《册魏公九锡文》全篇，尽叙其功，以为其功高于伊、周，而 其奖却低于齐、晋，故赐爵赐土，又加九锡，奖励空前。但曹操被奖愈高，心内 愈忧。故曹操在曾早在五十六岁写的《让县自明本志令》中谓“或者人见 孤强盛， 又性不信天命之事， 恐私心相评， 言有不逊之志， 妄相忖度， 每用耿耿。

2008年浙师大《外国文学名著鉴赏》期末考试答案

（一）文学常识 一、古希腊罗马 1．（1）宙斯(罗马神话称为朱庇特)，希腊神话中最高的天神，掌管雷电云雨，是人和神的主宰。 （2）阿波罗，希腊神话中宙斯的儿子，主管光明、青春、音乐、诗歌等，常以手持弓箭的少年形象出现。 （3）雅典那，希腊神话中的智慧女神，雅典城邦的保护神。 （4）潘多拉，希腊神话中的第一个女人，貌美性诈。私自打开了宙斯送她的一只盒子，里面装的疾病、疯狂、罪恶、嫉妒等祸患，一齐飞出，只有希望留在盒底，人间因此充满灾难。“潘多拉的盒子”成为“祸灾的来源”的同义语。 （5）普罗米修斯，希腊神话中造福人间的神。盗取天火带到人间，并传授给人类多种手艺，触怒宙斯，被锁在高加索山崖，受神鹰啄食，是一个反抗强暴、不惜为人类牺牲一切的英雄。 （6）斯芬克司，希腊神话中的狮身女怪。常叫过路行人猜谜，猜不出即将行人杀害；后因谜底被俄底浦斯道破，即自杀。后常喻“谜”一样的人物。与埃及狮身人面像同名。 2．荷马，古希腊盲诗人。主要作品有《伊利亚特》和《奥德赛》，被称为荷马史诗。《伊利亚特》叙述十年特洛伊战争。《奥德赛》写特洛伊战争结束后，希腊英雄奥德赛历险回乡的故事。马克思称赞它“显示出永久的魅力”。 3．埃斯库罗斯，古希腊悲剧之父，代表作《被缚的普罗米修斯》。6．阿里斯托芬，古希腊“喜剧之父”代表作《阿卡奈人》。 4．索福克勒斯，古希腊重要悲剧作家，代表作《俄狄浦斯王》。5．欧里庇得斯，古希腊重要悲剧作家，代表作《美狄亚》。 二、中世纪文学 但丁，意大利人，伟大诗人，文艺复兴的先驱。恩格斯称他是“中世纪的最后一位诗人，同时又是新时代的最初一位诗人”。主要作品有叙事长诗《神曲》，由地狱、炼狱、天堂三部分组成。《神曲》以幻想形式，写但丁迷路，被人导引神游三界。在地狱中见到贪官污吏等受着惩罚，在净界中见到贪色贪财等较轻罪人，在天堂里见到殉道者等高贵的灵魂。 三、文艺复兴时期 1．薄迦丘意大利人短篇小说家，著有《十日谈》拉伯雷，法国人，著《巨人传》塞万提斯，西班牙人,著《堂?吉诃德》。 2．莎士比亚，16-17世纪文艺复兴时期英国伟大的剧作家和诗人，主要作品有四大悲剧——《哈姆雷特》、《奥赛罗》《麦克白》、《李尔王》，另有悲剧《罗密欧与朱丽叶》等，喜剧有《威尼斯商人》《第十二夜》《皆大欢喜》等，历史剧有《理查二世》、《亨利四世》等。马克思称之为“人类最伟大的戏剧天才”。 四、17世纪古典主义 9．笛福，17-18世纪英国著名小说家，被誉为“英国和欧洲小说之父”，主要作品《鲁滨逊漂流记》，是英国第一部现实主义长篇小说。10．弥尔顿，17世纪英国诗人，代表作：长诗《失乐园》，《失乐园》，表现了资产阶级清教徒的革命理想和英雄气概。 25．拉伯雷，16世纪法国作家，代表作：长篇小说《巨人传》。 26．莫里哀，法国17世纪古典主义文学最重要的作家，法国古典主义喜剧的创建者，主要作品为《伪君子》《悭吝人》（主人公叫阿巴公）等喜剧。 五、18世纪启蒙运动 1）歌德，德国文学最高成就的代表者。主要作品有书信体小说《少年维特之烦恼》，诗剧《浮士德》。 11．斯威夫特，18世纪英国作家，代表作：《格列佛游记》，以荒诞的情节讽刺了英国现实。 12．亨利·菲尔丁，18世纪英国作家，代表作：《汤姆·琼斯》。 六、19世纪浪漫主义 （1拜伦， 19世纪初期英国伟大的浪漫主义诗人，代表作为诗体小说《唐璜》通过青年贵族唐璜的种种经历，抨击欧洲反动的封建势力。《恰尔德。哈洛尔游记》 （2雨果，伟大作家，欧洲19世纪浪漫主义文学最卓越的代表。主要作品有长篇小说《巴黎圣母院》、《悲惨世界》、《笑面人》、《九三年》等。《悲惨世界》写的是失业短工冉阿让因偷吃一片面包被抓进监狱，后改名换姓，当上企业主和市长，但终不能摆脱迫害的故事。《巴黎圣母院》 弃儿伽西莫多，在一个偶然的场合被副主教克洛德.孚罗洛收养为义子，长大后有让他当上了巴黎圣母院的敲钟人。他虽然十分丑陋而且有多种残疾，心灵却异常高尚纯洁。 长年流浪街头的波希米亚姑娘拉.爱斯梅拉达，能歌善舞，天真貌美而心地淳厚。青年贫诗人尔比埃尔.甘果瓦偶然同她相遇，并在一个更偶然的场合成了她名义上的丈夫。很有名望的副教主本来一向专心于"圣职"，忽然有一天欣赏到波希米亚姑娘的歌舞，忧千方百计要把她据为己有，对她进行了种种威胁甚至陷害，同时还为此不惜玩弄卑鄙手段，去欺骗利用他的义子伽西莫多和学生甘果瓦。眼看无论如何也实现不了占有爱斯梅拉达的罪恶企图，最后竟亲手把那可爱的少女送上了绞刑架。 另一方面，伽西莫多私下也爱慕着波希米亚姑娘。她遭到陷害，被伽西莫多巧计救出，在圣母院一间密室里避难，敲钟人用十分纯朴和真诚的感情去安慰她，保护她。当她再次处于危急中时，敲钟人为了援助她，表现出非凡的英勇和机智。而当他无意中发现自己的"义父"和"恩人"远望着高挂在绞刑架上的波希米亚姑娘而发出恶魔般的狞笑时，伽西莫多立即对那个伪善者下了最后的判决，亲手把克洛德.孚罗洛从高耸入云的钟塔上推下，使他摔的粉身碎骨。 （3司汤达，批判现实主义作家。代表作《红与黑》，写的是不满封建制度的平民青年于连，千方百计向上爬，最终被送上断头台的故事。“红”是将军服色，指“入军界”的道路；“黑”是主教服色，指当神父、主教的道路。 14．雪莱，19世纪积极浪漫主义诗人，欧洲文学史上最早歌颂空想社会主义的诗人之一，主要作品为诗剧《解放了的普罗米修斯》，抒情诗《西风颂》等。 15．托马斯·哈代，19世纪英国作家，代表作：长篇小说《德伯家的苔丝》。 16．萨克雷，19世纪英国作家，代表作：《名利场》 17．盖斯凯尔夫人，19世纪英国作家，代表作：《玛丽·巴顿》。 18．夏洛蒂?勃朗特，19世纪英国女作家，代表作：长篇小说《简?爱》19艾米丽?勃朗特，19世纪英国女作家，夏洛蒂?勃朗特之妹，代表作：长篇小说《呼啸山庄》。 20．狄更斯，19世纪英国批判现实主义文学的重要代表，主要作品为长篇小说《大卫?科波菲尔》、《艰难时世》《双城记》《雾都孤儿》。21．柯南道尔，19世纪英国著名侦探小说家，代表作品侦探小说集《福尔摩斯探案》是世界上最著名的侦探小说。 七、19世纪现实主义 1、巴尔扎克，19世纪上半叶法国和欧洲批判现实主义文学的杰出代表。主要作品有《人间喜剧》，包括《高老头》、《欧也妮·葛朗台》、《贝姨》、《邦斯舅舅》等。《人间喜剧》是世界文学中规模最宏伟的创作之一，也是人类思维劳动最辉煌的成果之一。马克思称其“提供了一部法国社会特别是巴黎上流社会的卓越的现实主义历史”。

单片机C延时时间怎样计算

C程序中可使用不同类型的变量来进行延时设计。经实验测试，使用unsigned char类型具有比unsigned int更优化的代码，在使用时 应该使用unsigned char作为延时变量。以某晶振为12MHz的单片 机为例，晶振为12M H z即一个机器周期为1u s。一. 500ms延时子程序 程序: void delay500ms(void) { unsigned char i,j,k; for(i=15;i>0;i--) for(j=202;j>0;j--) for(k=81;k>0;k--); } 计算分析: 程序共有三层循环 一层循环n:R5*2 = 81*2 = 162us DJNZ 2us 二层循环m:R6*(n+3) = 202*165 = 33330us DJNZ 2us + R5赋值 1us = 3us 三层循环: R7*(m+3) = 15*33333 = 499995us DJNZ 2us + R6赋值 1us = 3us

循环外: 5us 子程序调用 2us + 子程序返回2us + R7赋值 1us = 5us 延时总时间 = 三层循环 + 循环外 = 499995+5 = 500000us =500ms 计算公式:延时时间=[(2*R5+3)*R6+3]*R7+5 二. 200ms延时子程序 程序: void delay200ms(void) { unsigned char i,j,k; for(i=5;i>0;i--) for(j=132;j>0;j--) for(k=150;k>0;k--); } 三. 10ms延时子程序 程序: void delay10ms(void) { unsigned char i,j,k; for(i=5;i>0;i--) for(j=4;j>0;j--) for(k=248;k>0;k--);

for和to区别

1.表示各种“目的”，用for （1）What do you study English for 你为什么要学英语？ （2）went to france for holiday. 她到法国度假去了。 （3）These books are written for pupils. 这些书是为学生些的。 （4）hope for the best, prepare for the worst. 作最好的打算，作最坏的准备。 2．“对于”用for （1）She has a liking for painting. 她爱好绘画。 （2）She had a natural gift for teaching. 她对教学有天赋/ 3．表示“赞成、同情”，用for （1）Are you for the idea or against it 你是支持还是反对这个想法？ （2）He expresses sympathy for the common people.. 他表现了对普通老百姓的同情。 （3）I felt deeply sorry for my friend who was very ill. 4. 表示“因为，由于”（常有较活译法），用for （1）Thank you for coming. 谢谢你来。

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