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SN65lvds93

FEATURES

DESCRIPTION

V CC D5D6D7GND D8D9D10V CC D11D12D13GND D14D15D16CLKSEL

D17D18D19GND D20D21D22D23V CC D24D25

D4D3D2GND D1D0D27

LVDSGND Y1M Y1P Y2M Y2P

LVDSV CC LVDSGND Y3M Y3P

CLKOUTM CLKOUTP Y4M Y4P

LVDSGND PLLGND PLLV CC PLLGND SHTDN CLKIN D26GND

DGG PACKAGE (TOP VIEW)

SN65LVDS93

https://www.wendangku.net/doc/8518742429.html, .................................................................................................................................................................SLLS302G–MAY 1998–REVISED MAY 2009

LVDS SERDES TRANSMITTER

When transmitting,data bits D0through D27are each loaded into registers upon the edge of the input ?28:4Data Channel Compression at up to clock signal (CLKIN).The rising or falling edge of the 1.904Gigabits per Second Throughput clock can be selected via the clock select (CLKSEL)?Suited for Point-to-Point Subsystem pin.The frequency of CLKIN is multiplied seven times Communication With Very Low EMI

and then used to serially unload the data registers in 7-bit slices.The four serial streams and a ?

28Data Channels Plus Clock in Low-Voltage phase-locked clock (CLKOUT)are then output to TTL and 4Data Channels Plus Clock Out LVDS output drivers.The frequency of CLKOUT is Low-Voltage Differential

the same as the input clock,CLKIN.

?Selectable Rising or Falling Clock Edge Triggered Inputs

?Bus Pins Tolerate 6-kV HBM ESD

?Operates From a Single 3.3-V Supply and 250mW (Typ)

?5-V Tolerant Data Inputs

?Packaged in Thin Shrink Small-Outline Package With 20Mil Terminal Pitch ?Consumes <1mW When Disabled

?Wide Phase-Lock Input Frequency Range 20MHz to 68MHz

?No External Components Required for PLL ?Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644Standard

?Industrial Temperature Qualified T A =–40°C to 85°C

Replacement for the DS90CR285

The SN65LVDS93LVDS serdes (serializer/deserializer)transmitter contains four 7-bit parallel-load serial-out shift registers,a 7?clock synthesizer,and five low-voltage differential signaling (LVDS)drivers in a single integrated circuit.These functions allow 28bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver,such as the SN65LVDS94.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION (CONTINUED)

FUNCTIONAL BLOCK DIAGARAM

SHTDN

CLKIN D16, D17, D23

D24, D25, D26

D14, D15, D18

D0, D1, D2, D3,

D4, D6, D7

Y0P Y0M

Y1P Y1M

Y2P Y2M

Y3P Y3M

CLKOUTP CLKOUTM

CLKSEL

SN65LVDS93

SLLS302G–MAY 1998–REVISED MAY https://www.wendangku.net/doc/8518742429.html,

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The SN65LVDS93requires no external components and little or no control.The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption.A low level on this signal clears all internal registers at a low level.

The SN65LVDS93is characterized for operation over ambient air temperatures of –40°C to 85°C.

CLKOUT

CLKIN

or CLKIN

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

V Dn or SHTDN

V YnP or YnM

INPUT OUTPUT

SN65LVDS93

Figure 1.Typical 'LVDS93Load and Shift Sequences

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

RECOMMENDED OPERATING CONDITIONS

SN65LVDS93

SLLS302G–MAY 1998–REVISED MAY https://www.wendangku.net/doc/8518742429.html,

over operating free-air temperature range (unless otherwise noted)(1)

UNIT

V CC Supply voltage range (2)

–0.5V to 4V V O Voltage range at any output terminal -0.5V to V CC +0.5V V I

Voltage range at any input terminal

–0.5V to 5.5V

Bus Pins (Class 3A)

6KV Bus Pins (Class 2B)400V Electrostatic discharge (3)

Bus Pins (Class 2A)6KV Bus Pins (Class 2B)

200V

Continuous total power dissipation

See Dissipation Rating Table

T A Operating free-air temperature range –40°C to 85°C T stg

Storage temperature range

–65°C to 150°C

Lead temperature 1,6mm (1/16inch)from case for 10seconds

260°C

(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)All voltage values are with respect to the GND terminals.

(3)

This rating is measured using MIL-STD-883C Method,3015.7.

T A ≤25°C DERATING FACTOR (1)

T A =70°C T A =85°C PACKAGE POWER RATING

ABOVE T A =25°C

POWER RATING

DGG 1377mW

11mW/°C

882mW

717mW

(1)

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

MIN

NOM MAX UNIT V CC Supply voltage 3 3.3

3.6

V V IH High-level input voltage 2

V V IL Low-level input voltage 0.8V Z L Differential load impedance 90132?T A

Operating free-air temperature

–4085

°C

ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS

SN65LVDS93

https://www.wendangku.net/doc/8518742429.html,

.................................................................................................................................................................SLLS302G–MAY 1998–REVISED

MAY 2009

over recommended operating free-air temperature range (unless otherwise noted)

(1)

All typical values are at V CC =3.3V,T A =25°C.

SWITCHING CHARACTERISTICS

PARAMETER MEASUREMENT INFORMATION

CLKIN CLKSEL LOW CLKSEL HIGH

SN65LVDS93

SLLS302G–MAY 1998–REVISED MAY https://www.wendangku.net/doc/8518742429.html,

over recommended operating conditions (unless otherwise noted)

(1)All typical values are at V CC =3.3V,T A =25°C.

(2)Input clock jitter is the magnitude of the charge in the input clock period

(3)

The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000cycles.

note:

All input timing is defined at 1.4V on an input signal with a 10%to 90%rise or fall time of less than 5ns.

Figure 2.Setup and Hold Time Definition

SN65LVDS93 https://www.wendangku.net/doc/8518742429.html,.................................................................................................................................................................SLLS302G–MAY1998–REVISED MAY2009

PARAMETER MEASUREMENT INFORMATION(continued)

49.9 ?± 1% (2 Places)

NOTE A:The lumped instrumentation capacitance for any

single-ended voltage measurement is less than or equal

to 10 pF. When making measurements at YP or YM, the

complementary output is similarly loaded.

(a) SCHEMATIC

Figure3.Test Load and Voltage Definitions for LVDS Outputs

CLKIN

Even Dn

Odd Dn

NOTE A:The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with CLKSEL low shown.

Figure4.Worst-Case Test Pattern(CLKSEL Low Shown)

CLKIN

CLKOUT

V OD(H)V OD(L)

0.00 V t d0 – t d6

≈ 0.5 V

1.4 V t d7

CLKIN

≈ 2.5 V

CLKOUT

or Yn

Reference

VCO

Device Under Test

Modulation

∑

V(t) = A sin (2 π f (mod) t)

HP8656B Signal Generator 0.1 MHz – 990 MHz

HP8665A

Synthesized Signal

Generator

0.1 MHz – 4200 MHz

RF Output

Modulation Input

Device Under Test

DTS2070C Digital Time Scope

OUTPUT

CLKIN CLKOUT Input

SN65LVDS93

SLLS302G–MAY 1998–REVISED MAY https://www.wendangku.net/doc/8518742429.html,

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 5.Timing Definitions

Figure 6.Output Clock Jitter Test Setup

CLKIN

SHTDN

CLKIN

CLKOUT

SHTDN TYPICAL CHARACTERISTICS

I C C 30

5060

f ? Frequency ? MHz

? S u p p l y C u r r e n t ? m A

SN65LVDS93

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 7.Enable Time Waveforms (CLKSEL low shown)

Figure 8.Disable Time Waveforms (CLKSEL low shown)

WORST-CASE SUPPLY CURRENT

Figure 9.

APPLICATION INFORMATION

16-BIT BUS EXTENSION

LVDS Interface 0 To 10 Meters (Media Dependent)

TTL Interface 16-Bit BTL Bus Interface

Bus

TTL

Interface 16-Bit BTL Bus Interface

16-BIT BUS EXTENSION WITH PARITY

SN65LVDS93

SLLS302G–MAY 1998–REVISED MAY https://www.wendangku.net/doc/8518742429.html,

In a 16-bit bus application (Figure 10),TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the inputs of the LVDS serdes transmitter.The clock associated with the bus is also connected to the device.The on-chip PLL synchronizes this clock with the parallel data at the input.The data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion.The clock is also converted to LVDS and presented to a separate driver.This synchronized LVDS data and clock at the receiver,which recovers the LVDS data and clock,performs a conversion back to TTL.Data is then demultiplexed into a parallel format.An on-chip PLL synchronizes the received clock with the parallel data,and then all are presented to the parallel output port of the receiver.

Figure 10.16-Bit Bus Extension

In the previous application we did not have a checking bit that would provide assurance that the data crosses the link.If we add a parity bit to the previous example,we would have a diagram similar to the one in Figure 11.The device following the SN74FB2032is a low-cost parity generator.Each transmit-side takes the LVTTL data from the corresponding transceiver,performs a parity calculation over the byte,and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter.Again,the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16data +2parity)at the input.The synchronized LVDS data/parity and clock arrive at the receiver.

The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the parity calculations.These devices compare their corresponding input bytes with the value received on the parity bit.The transceiver/parity generator will assert its parity error output if a mismatch is detected.

LVDS Interface 0 To 10 Meters (Media Dependent)

TTL Interface W/Parity 16-Bit BTL Bus Interface

Bus

TTL Interface

16-Bit BTL Bus Interface

TTL Interface

TTL Interface W/Parity

low cost virtual backplane transceiver

Backplane

Bus

Backplane Bus

SN65LVDS93

Figure 11.16-Bit Bus Extension With Parity

Figure 12represents LVDS serdes in an application as a virtual backplane transceiver (VBT).The concept of a be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem serialized links.

Depending on the application,the designer will face varying choices when implementing a VBT.In addition to the devices shown in Figure 12,functions such as parity and delay lines for control signals could be https://www.wendangku.net/doc/8518742429.html,ing additional or full-duplex operation can be achieved by configuring the clock and control lines properly.

The designer may choose to implement an independent clock oscillator at each end of the link and then use a PLL to synchronize LVDS serdes's parallel I/O to the backplane bus.Resynchronizing FIFOs may also be required.

Figure 12.Virtual Backplane Transceiver

PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)

Lead/Ball Finish MSL Peak Temp (3)SN65LVDS93DGG ACTIVE TSSOP DGG 5635Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SN65LVDS93DGGG4ACTIVE TSSOP DGG 5635

Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1YEAR SN65LVDS93DGGR ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SN65LVDS93DGGRG4

ACTIVE

TSSOP

DGG

2000Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1YEAR

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/8518742429.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases

its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

https://www.wendangku.net/doc/8518742429.html,

14-May-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Type Package Drawing Pins SPQ

Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN65LVDS93DGGR TSSOP

DGG

2000

330.0

24.4

8.6

15.6

1.8

12.0

24.0

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm)

SN65LVDS93DGGR TSSOP DGG562000367.0367.045.0

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