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AD8349AREZ中文资料

700 MHz to 2700 MHz

Quadrature Modulator

AD8349 Rev.A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: https://www.wendangku.net/doc/9b4925562.html, Fax: 781.326.8703? 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Output frequency range: 700 MHz to 2700 MHz Modulation bandwidth: dc to 160 MHz (large signal BW) 1 dB output compression: 5.6 dBm @ 2140 MHz

Output disable function: output below –50 dBm in < 50 ns Noise floor: –156 dBm/Hz

Phase quadrature error: 0.3 degrees @ 2140 MHz Amplitude balance: 0.1 dB

Single supply: 4.75 V to 5.5 V

Pin compatible with AD8345/AD8346s

16-lead, exposed-paddle TSSOP package APPLICATIONS

Cellular/PCS communication systems infrastructure WCDMA/CDMA2000/PCS/GSM/EDGE

Wireless LAN/wireless local loop

LMDS/broadband wireless access systems FUNCTIONAL BLOCK DIAGRAM

QBBP

QBBN

COM3

VPS2

VOUT

COM3

COM2

Figure 1.

PRODUCT DESCRIPTION

The AD8349 is a silicon, monolithic, RF quadrature modulator that is designed for use from 700 MHz to 2700 MHz. Its excellent phase accuracy and amplitude balance enable high performance direct RF modulation for communication systems. The differential LO input signal is buffered, and then split into an in-phase (I) signal and a quadrature-phase (Q) signal using a polyphase phase splitter. These two LO signals are further buffered and then mixed with the corresponding I channel and Q channel baseband signals in two Gilbert cell mixers. The mixers’ outputs are then summed together in the output amplifier. The output amplifier is designed to drive 50 ? loads. The RF output can be switched on and off within 50 ns by applying a control pulse to the ENOP pin. The AD8349 can be used as a direct-to-RF modulator in digital communication systems such as GSM, CDMA, and WCDMA base stations, and QPSK or QAM broadband wireless access transmitters. Its high dynamic range and high modulation accuracy also make it a perfect IF modulator in local multipoint distribution systems (LMDS) using complex modulation formats.

The AD8349 is fabricated using Analog Devices’ advanced complementary silicon bipolar process, and is available in a 16-lead, exposed-paddle TSSOP package. Its performance is specified over a –40°C to +85°C temperature range.

AD8349

Rev. A | Page 2 of 28

TABLE OF CONTENTS

Specifications.....................................................................................3 Absolute Maximum Ratings............................................................5 ESD Caution..................................................................................5 Pin Configuration and Functional Descriptions..........................6 Equivalent Circuits...........................................................................7 Typical Performance Characteristics.............................................8 Circuit Description.........................................................................14 Overview......................................................................................14 LO Interface.................................................................................14 V-to-I Converter.........................................................................14 Mixers..........................................................................................14 D-to-S Amplifier.........................................................................14 Bias Circuit..................................................................................14 Output Enable.............................................................................14 Basic Connections..........................................................................15 Baseband I and Q Inputs...........................................................15 Single-Ended Baseband Drive..................................................15 LO Input Drive Level.................................................................16 Frequency Range........................................................................16 LO Input Impedance Matching................................................16 Single-Ended LO Drive..............................................................17 RF Output....................................................................................17 Output Enable.............................................................................17 Baseband DAC Interface...........................................................18 AD9777 Interface.......................................................................18 Biasing and Filtering..................................................................18 Reducing Undesired Sideband Leakage..................................19 Reduction of LO Feedthrough.................................................19 Sideband Suppression and LO Feedthrough vs. Temperature .......................................................................................................20 Applications.....................................................................................21 3GPP WCDMA Single-Carrier Application...........................21 WCDMA MultiCarrier Application........................................21 GSM/EDGE Application...........................................................22 Soldering Information...............................................................23 LO Generation Using PLLs.......................................................23 Transmit DAC Options.............................................................23 Evaluation Board............................................................................24 Characterization Setups.................................................................26 SSB Setup.....................................................................................26 Outline Dimensions.......................................................................27 Ordering Guide.. (27)

REVISION HISTORY

11/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Figure 25 through Figure 30................................11 Changes to Figure 37 through Figure 39................................13 Change to WCDMA MultiCarrier Application section.......21 Change to Figure 60 and Figure 61.........................................21 11/03—Revision 0: Initial Version

AD8349

Rev. A | Page 3 of 28

SPECIFICATIONS

V S = 5 V; ambient temperature (T A ) = 25°C; LO = –6 dBm; I/Q inputs = 1.2 V p-p differential sine waves in quadrature on a 400 mV dc bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 ?, unless otherwise noted. Table 1.

Parameter Conditions M in Typ M ax Unit Operating Frequency 700 2700 MHz LO = 900 MHz Output Power 1.5 4 6 dBm Output P1 dB 7.6 dBm Carrier Feedthrough –45 –30 dBm Sideband Suppression –35 –31 dBc

Third Harmonic 1

P OUT – (F LO + (3 × F BB )), P OUT = 4 dBm –39 –36 dBc Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P OUT = -4.2 dBm 21 dBm Quadrature Error 1.9 degree I/Q Amplitude Balance 0.1 dB Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –155 dBm/Hz 20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –150 dBm/Hz GSM Sideband Noise LO = 884.8 MHz, 6 MHz offset from LO, P OUT = 2 dBm –152 dBc/Hz LO = 1900 MHz Output Power 0 3.8 6 dBm Output P1dB 6.8 dBm Carrier Feedthrough –38 dBm Sideband Suppression –40 –36 dBc

Third Harmonic 1

P OUT – (F LO + (3 × F BB )), P OUT = 3.8 dBm –37 –36 dBc Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P OUT = –4.5 dBm 22 dBm Quadrature Error 0.7 degree I/Q Amplitude Balance 0.1 dB Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –156 dBm/Hz 20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –150 dBm/Hz GSM Sideband Noise LO = 1960 MHz, 6 MHz offset from LO, P OUT = 2 dBm –151 dBc/Hz LO = 2140 MHz Output Power –2 2.4 5.1 dBm Output P1dB 5.6 dBm Carrier Feedthrough –42 –30 dBm Sideband Suppression –43 –36 dBc

Third Harmonic 1

P OUT – (F LO + (3 × F BB )), P OUT = 2.4 dBm –37 –36 dBc Output IP3 F1BB = 3 MHz, F2BB = 4 MHz, P OUT = –6.5 dBm 19 dBm Quadrature Error 0.3 degree I/Q Amplitude Balance 0.1 dB Noise Floor 20 MHz offset from LO, all BB inputs 400 mV dc bias only –156 dBm/Hz 20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc –151 dBm/Hz WCDMA Noise Floor LO = 2140 MHz. 30 MHz offset from LO, P CHAN = –17.3 dBm –156 dBm/Hz LO INPUTS Pins LOIP and LOIN LO Drive Level Characterization performed at typical level –10 –6 0 dBm Nominal Impedance 50 ? Input Return Loss Drive via 1:1 balun, LO = 2140 MHz –8.6 dB BASEBAND INPUTS Pins IBBP, IBBN, QBBP, QBBN I and Q Input Bias Level 400 mV Input Bias Current 11 μA Input Offset Current 1.8 μA Bandwidth (0.1 dB) LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc 10 MHz LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc 24 MHz

AD8349

Rev. A | Page 4 of 28

Parameter Conditions M in Typ M

ax Unit Bandwidth (3 dB) LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc 160 MHz LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc 340 MHz OUTPUT ENABLE Pin ENOP Off Isolation ENOP Low –78 –50 dBm Turn-On Settling Time ENOP Low to High (90% of envelope) 20 ns Turn-Off Settling Time ENOP High to Low (10% of envelope) 50 ns ENOP High Level (Logic 1) 2.0 V ENOP Low Level (Logic 0) 0.8 V POWER SUPPLIES Pins VPS1 and VPS2 Voltage 4.75 5.5 V Supply Current ENOP = High 135 150 mA ENOP = Low 130 145 mA

The amplitude of the third harmonic relative to the single sideband power decreases with decreasing baseband drive level (see Figure 19, Figure 20, and Figure 21).

AD8349

Rev. A | Page 5 of 28

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating Supply Voltage VPOS 5.5 V IBBP, IBBN, QBBP, QBBN 0 V, 2.5 V LOIP and LOIN 10 dBm Internal Power Dissipation 800 mW θJA (Exposed Paddle Soldered Down) 30°C/W Maximum Junction Temperature 125°C Operating Temperature Range ?40°C to +85°C Storage Temperature Range ?65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD8349

Rev. A | Page 6 of 28

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

IBBP IBBN COM1COM1LOIN QBBP QBBN

COM3COM3VPS2

LOIP VPS1ENOP VOUT

COM3COM2

03570-0-002

Figure 2.

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

Equivalent Circuit 1, 2, 15, 16

IBBP, IBBN, QBBN, QBBP

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to approximately 400 mV dc, and must be driven from a low impedance source. Nominal characterized ac signal swing is 600 mV p-p on each pin (100 mV to 700 mV). This results in a differential drive of 1.2 V p-p with a 400 mV dc bias. These inputs are not self-biased and must be externally biased.

Circuit A

3, 4 COM1 Common Pin for LO Phase Splitter and LO Buffers. COM1, COM2, and COM3 should all be

connected to a ground plane via a low impedance path.

5, 6 LOIN, LOIP Differential Local Oscillator Inputs. Internally dc-biased to approximately 1.8 V when V S = 5.0 V.

Pins must be ac-coupled. Single-ended drive is possible with degradation in performance.

Circuit B 7 VPS1 Positive Supply Voltage (4.75 V to 5.5 V) for the LO Bias-Cell and Buffer. VPS1 and VPS2 should

be connected to the same supply. To ensure adequate external bypassing, connect 0.1 μF and 100 pF capacitors between VPS1 and ground.

8 ENOP Output Enable. This pin can be used to enable or disable the RF output. Connect to high logic

level for normal operation. Connect to low logic level to disable output.

Circuit C 9 COM2 Common Pin for the Output Amplifier. COM1, COM2, and COM3 should all be connected to a

ground plane via a low impedance path.

10, 13, 14 COM3 Common Pin for Input V-to-I Converters and Mixer Cores. COM1, COM2, and COM3 should all

be connected to a ground plane via a low impedance path.

11 VOUT Device Output. Single-ended, 50 ? internally biased RF output. Pin must be ac-coupled to the

load.

Circuit D 12 VPS2 Positive Supply Voltage (4.75 V to 5.5 V) for the Baseband Input V-to-I Converters, Mixer Core,

Band Gap Reference, and Output Amplifer. VPS1 and VPS2 should be connected to the same supply. To ensure adequate external bypassing, connect 0.1 μF and 100 pF capacitors between VPS2 and ground.

AD8349

Rev. A | Page 7 of 28

EQUIVALENT CIRCUITS

IBBP

03570-0-003

Figure 3. Circuit A

VPS1

LOIN

LOIP

COM1

03570-0-004

Figure 4. Circuit B

VPS2

ENOP

COM3

Figure 5. Circuit C

03570-

0-006

VOUT

VPS2

Figure 6. Circuit D

AD8349

Rev. A | Page 8 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

–4–20–1–3

21S S B O U T P U T P O W E R (d B m )

436

587700

900110013001500170019002100230025002700

LO FREQUENCY (MHz)

03570-0-007

Figure 7. Single Sideband (SSB) Output Power (P OUT ) vs. LO Frequency (F LO ) (I and Q Inputs Driven in Quadrature at Baseband Frequency (F BB ) = 1 MHz,

I and Q Inputs at 1.2 V p-p Differential, T A = 25°C)

–10

–9–7–3–11–5–8–4–20

–6O U T P U T P O W E R V A R I A T I O N (d B )

03570-0-00

BASEBAND FREQUENCY (MHz)

1000

100

Figure 8. I and Q Input Bandwidth Normalized to Gain @ 1 MHz

(F LO = 1500 MHz, T A = 25°C)

0.5

1.01.5

2.02.5

3.03.5

4.0S S B O U T P U T P O W E R (d B m )

–40–30–20–10

010203040TEMPERATURE (°C)

60507080

03570-0-00

Figure 9. SSB P OUT vs. Temperature (F LO = 2140 MHz, F BB = 1 MHz, I and Q

Inputs Driven in Quadrature at 1.2 V p-p Differential) –4–3–1357810

1–224601d B O U T P U T C O M P R E S S I O N (d B m )

700

900110013001500170019002100230025002700

LO FREQUENCY (MHz)

03570-0-01

Figure 10. SSB Output 1 dB Compression Point (OP1dB) vs. F LO (F BB = 1 MHz,

I and Q Inputs Driven in Quadrature , T A = 25°C)

–60–55–50–45–40–35–30–25–20–15–10C A R R I E R F E E D T H R O U G H (d B m )

700

900

110013001500170019002100230025002700

LO FREQUENCY (MHz)

03570-0-011

Figure 11. Carrier Feedthrough vs. F LO (F BB = 1 MHz, I and Q Inputs Driven in

Quadrature at 1.2 V p-p Differential, T A = 25°C)

–50

–48–46

–20C A R R I E R F E E D T H R O U G H (d B m )

–44–42–40–38–36–34–32–30–28–26–24–22–40–30–20–10

010203040TEMPERATURE (°C)

60507080

03570-0-0

Figure 12. Carrier Feedthrough vs. Temperature (F LO = 2140 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

AD8349

Rev. A | Page 9 of 28

S I D E B A N D S U P P R E S S I O N (d B c )

–60–55

–50–45–40

–35–30–25–20–15–10700

900110013001500170019002100230025002700

LO FREQUENCY (MHz)

03570-0013

Figure 13. Sideband Suppression vs. F LO (F BB = 1 MHz, I and Q Inputs

Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

–60–55

–50–45–40–35–30–25–20–15–10S I D E B A N D S U P P R E S S I O N (d B c )

BASEBAND FREQUENCY (MHz)

100

03570-0-014

Figure 14. Sideband Suppression vs. F BB (F LO = 2140 MHz, I and Q Inputs

Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C) –60

–55–50

–45

–40–35

–30S I D E B A N D S U P P R E S S I O N (d B c )

–40–30–20–10010203040TEMPERATURE (°C)

60507080

03570-

0-015

Figure 15. Sideband Suppression vs. Temperature (F LO = 2140 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential) T H I R D O R D E R D I S T O R T I O N (d B c )

–60

–55

–50–45–40–35–30–25–20–15–10700

900110013001500170019002100230025002700

LO FREQUENCY (MHz)

03570-0016

Figure 16. Third Order Distortion vs. F LO (F BB = 1 MHz, I and Q Inputs

Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

–60

–55

–50–45–40–35–30–25–20–15–10

T H I R D O R D E R D I S T O R T I O N (d B c )

BASEBAND FREQUENCY (MHz)

100

03570-0

-017

Figure 17. Third Order Distortion vs. F BB (F LO = 2140 MHz, I and Q Inputs

Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

–60

–55

–50

–45

–40

–35

–30

T H I R D O R D E R D I S T O R T I O N (d B c )

–40–30–20–10

010203040TEMPERATURE (°C)

60507080

0357

0-0-018

Figure 18. Third Order Distortion vs. Temperature (F LO = 2140 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential)

AD8349

Rev. A | Page 10 of 28

–70–60–50–55–65

–40–45–30–35–20–25–10–15–14

–10–6–8–12

–2–4206

41080.20.40.60.8 1.0 1.4 2.41.2 1.6 1.8 2.0 2.6 2.8 3.0BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)

2.203570-0-019

Figure 19. Third Order Distortion (3USB), Carrier Feedthrough, Sideband

Suppression, and SSB P OUT vs. Baseband Differential Input Level

(F LO = 900 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature, T A = 25°C)

–70–60–50–55–65

–40–45–30–35–20–25–10–15–14

–10–6–8–12

–2–420641080.20.40.60.8 1.0 1.4 2.41.2 1.6 1.8 2.0 2.6 2.8 3.0

BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)

2.203570-0-02

Figure 20. Third Order Distortion (3USB), Carrier Feedthrough, Sideband

Suppression, and SSB P OUT vs. Baseband Differential Input Level

(F LO = 1900 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature, T A = 25°C)

–70

–60–50–55–65

–40–45–30–35–20–25–10–15–14–10–6–8–12

–2–420641080.20.40.60.8 1.0 1.4 2.41.2 1.6 1.8 2.0 2.6 2.8 3.0

BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)

2.203570-0-02

Figure 21. Third Order Distortion (3USB), Carrier Feedthrough, Sideband

Suppression, and SSB P OUT vs. Baseband Differential Input Level

(F LO = 2140 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature, T A = 25°C)

110

115

120125130135160S U P P L Y C U R R E N T (m A )

140145150155–40–30–20–10

010203040TEMPERATURE (°C)

6050

7080

03570-0-022

Figure 22. Power Supply Current vs. Temperature

03570-

0023

Figure 23. Smith Chart of LOIP Port S 11 (LOIN Pin AC-Coupled to Ground). Curves with Balun and External Termination

Resistors Also Shown (T A = 25°C)

03570-0-024

R E T U R N L O S S (d B )

700

900110013001500170019002100230025002700

FREQUENCY (MHz)

Figure 24. Return Loss ?S 22?of V OUT Output (T A = 25°C)

AD8349

Rev. A | Page 11 of 28

024622242628302081012141618P E R C E N T A G E

NOISE FLOOR (dBm/Hz)

03570-0-025

Figure 25. 20 MHz Offset Noise Floor Distribution at F LO = 900 MHz (BB Inputs at a Bias of 400 mV with no AC signal, T A = 25°C)

462224262830P E R C E N T A G E

2081012141618

NOISE FLOOR (dBm/Hz)

03570-0-026

Figure 26. 20 MHz Offset Noise Floor Distribution at F LO = 1900 MHz

(BB Inputs at a Bias of 400 mV with no AC signal, T A = 25°C)

2462224262830P E R C E N T A G E

208101214

1618NOISE FLOOR (dBm/Hz)

03570-0-027

Figure 27. 20 MHz Offset Noise Floor Distribution at F LO = 2140 MHz

(BB Inputs at a Bias of 400 mV with no AC signal, T A = 25°C) 0

468101214161820P E R C E N T A G E

–152.0

–151.5

–151.0

–150.5

–150.0

–149.5

–149.0

–148.5

–148.0

–147.5

–147.0

NOISE FLOOR (dBm/Hz)

03570-0-028

Figure 28. 20 MHz Offset Noise Floor Distribution at F LO = 940 MHz (F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, T A = 25°C)

4681012141618

28P E R C E N T A G E

–152.5

–151.5

–151.0

–150.5

–150.0

–149.5

–149.0

–148.5

–152.0

–148.0

NOISE FLOOR (dBm/Hz)

03570-0-029

24222620

Figure 29. 20 MHz Offset Noise Floor Distribution at F LO = 1960 MHz (F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, T A = 25°C)

46222426283020810121416

18P E R C E N T A G E

–153.0

–151.5

–151.0

–150.5

–150.0

–149.5

–149.0

–152.0

–152.5

NOISE FLOOR (dBm/Hz)

03570-0-030

Figure 30. 20 MHz Offset Noise Floor Distribution at F LO = 2140 MHz (F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, T A = 25°C)

AD8349

Rev. A | Page 12 of 28

–160

–158

–154

–146–142–140–150–156–148–144

–152N O I S E F L O O R (d B m /H z )

LO INPUT (dBm)

–10

203570-0-031

–8–6–4

–20

Figure 31. 20 MHz Offset Noise Floor vs. LO Input Power

(F LO = 2140 MHz, T A = 25°C)

–60–50–40–45–55–30–35C A R R I E R F E E D T H R O U G H (d B m )

–20–25–10–15

–6

–4

–10

–8

–2

LO INPUT (dBm)

03570-0032

Figure 32. Carrier Feedthrough vs. LO Input Power (F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

–60–50–40–45–55

–30–35S I D E B A N D S U P P R E S S I O N (d B c )

–25–20–10

–15

–6

–4

–10

–8

–2

LO INPUT (dBm)

03570-0033

Figure 33. Sideband Suppression vs. LO Input Power (F BB = 1 MHz, I and Q

Inputs Driven in Quadrature at 1.2 V p-p Differential, T A

= 25°C) 0

10152025

3035P E R C E N T A G E

–0.100–0.125–0.175–0.150–0.200–0.075–0.050–0.025

MAGNITUDE IMBALANCE (dB)

03570-0-034

Figure 34. I and Q Inputs Quadrature Phase Imbalance Distribution

(F LO = 2140 MHz, F BB

= 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

0510152025

35P E R C E N T A G E

0.50

0.75

0.25

1.00

1.25

1.50

PHASE (I-Q) IMBALANCE (Degrees)

03570-0-035

Figure 35. I and Q Inputs Amplitude Imbalance Distribution (F LO = 2140 MHz, F BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, T A = 25°C)

0510152025

35P E R C E N T

A G E

OP1dB (dBm)

5.04.5

5.5

6.0 6.5

03570-0-036

Figure 36. OP1dB Distribution. (F LO = 2140 MHz, F BB = 1 MHz, I and Q Inputs

Driven in Quadrature, T A = 25°C)

AD8349

Rev. A | Page 13 of 28

468101214

161820P E R C E N T A G E

–80

–70–60–50–40–30

CARRIER FEEDTHROUGH (dBm)

03570-0-03

Figure 37. Carrier Feedthrough Distribution at F LO = 900 MHZ (F BB = 1 MHz,

I and Q Inputs Driven in Quadrature at 1.2 V p-p, T A = 25°C)

1015202530

3540P E R C E N T A G E

–60

–45–40–35–30–25

CARRIER FEEDTHROUGH (dBm)

–55–5003570-0-04

Figure 38. Carrier Feedthrough Distribution at F LO = 1900 MHz (F BB = 1 MHz,

I and Q Inputs Driven in Quadrature at 1.2 Vp-p, T A = 25°C)

CARRIER FEEDTHROUGH (dBm)

P E R C E N T A G E

24222018

161412108642

0–70

–65

–60

–55

–50

–45

–40

–35

–30

03570-0-04

Figure 39. Carrier Feedthrough Distribution at F LO = 2140 MHz (F BB = 1 MHz,

I and Q Inputs Driven in Quadrature at 1.2 V p-p, T A

= 25°C)

0510152025

3035

P E R C E N T A G E

CARRIER FEEDTHROUGH (dBm)AFTER NULLING TO <–65dBm AT +25°C

03570-0-037

Figure 40. Carrier Feedthrough Distribution at Temperature Extremes, After Carrier Feedthrough Nulled to < - 65 dBm at T A = 25°C. (F LO = 2140 MHz,

I and Q Inputs at a bias of 400 mV)

P E R C E N T A G E

04812162024302610141822

2826–35

SIDEBAND SUPPRESSION (dBc)AFTER NULLING TO <–50dBc AT +25°C

03570-0-038

Figure 41. Sideband Suppression Distribution at Temperature Extremes, After Sideband Suppression Nulled to < -50 dBc at T A = 25°C. (F LO = 2140 MHz,

F BB = 1 MHz, I and Q Inputs biased at 0.4 V)

AD8349

Rev. A | Page 14 of 28

CIRCUIT DESCRIPTION

OVERVIEW

The AD8349 can be divided into five sections: the local oscil-lator (LO) interface, the baseband voltage-to-current (V-to-I) converter, the mixers, the differential-to-single-ended (D-to-S) amplifier, and the bias circuit. A detailed block diagram of the device is shown in Figure 42.

OUT

LOIP LOIN

IBBP IBBN

QBBP QBBN

03570-0-043

Figure 42. Block Diagram

The LO interface generates two LO signals at 90 degrees of phase difference to drive two mixers in quadrature. Baseband signals are converted into currents by the V-to-I converters, which feed into the two mixers. The outputs of the mixers combine to feed the differential-to-single-ended amplifier, which provides a 50 ? output interface. Reference currents to each section are generated by the bias circuit. Additionally, the RF output is controlled by an output enable pin (ENOP), which is capable of switching the output on and off within 50 ns. A detailed description of each section follows.

LO INTERFACE

The LO interface consists of interleaved stages of buffer amplifiers and polyphase phase splitters. An input buffer provides a 50 ? termination to the LO signal source driving LOIP and LOIN. The buffer also increases the LO signal amplitude to drive the phase splitter. The phase splitter is formed by an R-C polyphase network that splits the buffered LO signal into two parts in precise quadrature phase relation with each other. Each LO signal then passes through a buffer amplifier to compensate for the signal loss through the phase splitter. The two signals pass through another polyphase network to enhance the quadrature accuracy over the full operating frequency range. The outputs of the second phase splitter are fed into the driver amplifiers for the mixers’ LO inputs. V-TO-I CONVERTER

The differential baseband input voltages that are applied to the baseband input pins are fed to two op amps that perform a differential voltage-to-current conversion. The differential output currents of these op amps then feed each of their respective mixers.

MIXERS

The AD8349 has two double-balanced mixers, one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). Both mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers sum together in a pair of resistor-inductor (R-L) loads. The signals developed across the R-L loads are sent to the D-to-S amplifier.

D-TO-S AMPLIFIER

The output D-to-S amplifier consists of two emitter followers driving a totem pole output stage. Output impedance is estab-lished by the emitter resistors in the output transistors. The output of this stage connects to the output (VOUT) pin.

BIAS CIRCUIT

A band gap reference circuit generates the proportional-to-absolute-temperature (PTAT) reference currents used by

different sections. The band gap reference circuit also generates a temperature stable current in the V-to-I converters to produce a temperature independent slew rate.

OUTPUT ENABLE

During normal operation (ENOP = high), the output current from the V-to-I converters feeds into the mixers, where they mix with the two phases of LO signals. When ENOP is pulled low, the V-to-I output currents are steered away from the

mixers, thus turning off the RF output. Power to the final stage of LO drivers is also removed to minimize LO feedthrough. Even when the output is disabled, the differential-to-single-ended stage is still powered up to maintain constant output impedance.

AD8349

Rev. A | Page 15 of 28

BASIC CONNECTIONS

The basic connections for operating the AD8349 are shown in Figure 43. A single power supply of between 4.75 V and 5.5 V is applied to pins VPS1 and VPS2. A pair of ESD protection diodes connect internally between VPS1 and VPS2, so these must be tied to the same potential. Both pins should be individually decoupled using 100 pF and 0.1 μF capacitors to ground. These capacitors should be located as close as possible to the device. For normal operation, the output enable pin, ENOP , must be pulled high. The turn-on threshold for ENOP is 2 V . Pins COM1, COM2, and COM3 should all be tied to the same ground plane through low impedance paths.

BASEBAND I AND Q INPUTS

The I and Q inputs should be driven differentially. The typical differential drive level (as used for characterization measure-ments) for the I and Q baseband signals is 1.2 V p-p, which is equivalent to 600 mV p-p on each baseband input. The base-band inputs have to be externally biased to a level between 400 mV and 500 mV . The optimum level for the best perfor-mance is 400 mV . The recommended drive level of 1.2 V p-p does not indicate a maximum drive level. If operation closer to compression is desired, the 1.2 V p-p differential limit can be exceeded.

For baseband signals with a high peak-to-average ratio (e.g., CDDA or WCDMA), the peak signal level will have to be below the AD8349’s compression level in order to prevent clipping of the signal peaks. Clipping of signal peaks increases distortion. In the case of CDMA and WCDMA inputs, clipping results in an increase of signal leakage into adjacent channels. In general, the baseband drive should be at a level where the peak signal

power of the output signal is at least a crest factor below the AD8349’s output compression point. Refer to the Applications section for drive-level considerations in WCDMA and GSM/EDGE systems.

Reducing the baseband drive level also has the benefit of increasing the bandwidth of the baseband input. This would allow the AD8349 to be used in applications requiring a high modulation bandwidth, e.g., as the IF modulator in high data-rate microwave radios.

SINGLE-ENDED BASEBAND DRIVE

Where only single-ended I and Q signals are available, a differential amplifier, such as the AD8132 or AD8138, can be used to generate the required differential drive signal for the AD8349.

Figure 44 shows an example of a circuit that converts a ground-referenced, single-ended signal to a differential signal, and adds the required 400 mV bias voltage.

The baseband inputs can also be driven with a single-ended signal biased to 400 mV , with the unused inputs biased to 400 mV dc. This mode of operation is not recommended, however, because any dc level difference between the bias level of the drive signal and the dc level on the unused input (including the effect of temperature drift), can result in increased LO feedthrough. Additionally, the maximum low distortion output power will be reduced by 6 dB.

03570-0-044

S +V S

Figure 43. Basic Connections

AD8349

Rev. A | Page 16 of 28 0 3 5 7 0 -0 -0 4 5

μF I IN

Q IN

Figure 44. Single-Ended IQ Drive Circuit

LO INPUT DRIVE LEVEL

The local oscillator inputs are designed to be driven differen-tially. The device is specified with an LO drive level of –6 dBm. This level was chosen to provide the best noise performance. Increasing the LO drive level degrades sideband suppression and increases carrier feedthrough, while improving noise performance. Reducing the LO drive level creates the opposite effect: improved sideband suppression and reduced carrier feedthrough.

FREQUENCY RANGE

The LO frequency range is from 700 MHz to 2700 MHz. These limits are defined by the nature of the LO phase splitter circuitry. The phase splitter generates LO drive signals for the internal mixers, which are 90 degrees out of phase from each other. Outside of the specified frequency range (700 MHz to 2700 MHz), this quadrature accuracy degrades, resulting in poor sideband rejection performance. Figure 45 and Figure 46 show the sideband suppression of a typical device operating outside the specified LO frequency range. The level of sideband suppression and degradation is also influenced by manufac-turing process variations. LO INPUT IMPEDANCE MATCHING

Single-ended LO sources are transformed into a differential signal via a 1:1 balun (ETC1-1-13). A 200 ? shunt resistor to GND on each LO input on the device side of the balun reduces the return loss for the LO input port. Because the LO input pins are internally dc-biased, ac coupling capacitors must be used on each LO input pin.

AD8349

Rev. A | Page 17 of 28

03570-0-046

1.01.5

2.02.5

3.0

3.5

4.0

LO FREQUENCY (MHz)

S S B O U T P U T P O W E R (d B m )

–60–50

–40

–30

–20

–10

S I D E B A N D S U P P R E S S I O N (d B c )

Figure 45. Sideband Suppression below 700 MHz

0357

0-0-047

–1

0LO FREQUENCY (MHz)

S S B O U T P U T P O W E R (d B m )

–44

–43–42–41

–40S I D E B A N D S U P P R E S S I O N (d

B c )

–8–7–6–5–4

–3–2–45–46–48–47

2700

27502800285029002950

3000

Figure 46. Sideband Suppression above 2700 MHz

SINGLE-ENDED LO DRIVE

The LO input can be driven single-ended at the expense of higher LO feedthrough at most frequencies (see Figure 48). LOIN is ac-coupled to ground, and LOIP is driven through a coupling capacitor from a single-ended 50 ? source (see Figure 47).

A 400 ? shunt resistor on the signal-source side of the ac coupling capacitor was used for the measurement.

Figure 47. Schematic for Single-Ended LO Drive

–60–55

–50

–45–40–35–30–25–20–15

–10C A R R I E R F E E D T H

R O U G H (d B m )

700

900110013001500170019002100230025002700

LO FREQUENCY (MHz)

03570-0-049

Figure 48. LO Feedthrough vs. Frequency, Single-Ended vs. Differential LO

Drive (Single-Sideband Modulation)

RF OUTPUT

The RF output is designed to drive a 50 ? load, but should be ac-coupled, as shown in Figure 43, because of internal dc

biasing. The RF output impedance is close to 50 ? and provides fairly good return loss over the specified operating frequency range (see Figure 24). As a result, no additional matching circuitry is required if the output is driving a 50 ? load. The output power of the AD8349 under nominal conditions (1.2 V p-p differential baseband drive, 400 mV dc baseband bias, and a 5 V supply) is shown in Figure 7.

OUTPUT ENABLE

The ENOP pin can be used to turn the RF output on and off. This pin should be held high (greater than 2 V) for normal operation. Taking ENOP low (less than 800 mV) disables the output power and provides an off-isolation level of < –50 dBm at the output.

Figure 49 and Figure 50 show the enable and disable time domain responses of the ENOP function at 900 MHz. Typical enable and disable times are approximately 20 ns and 50 ns, respectively.

03570-0-050

–8

–4

–2

–60V E N O P (V )

86–800–400–200–600

0V V O U T (m V )

400200800600TIME (ns)

100

Figure 49. ENOP Enable Time, 900 MHz

AD8349

Rev. A | Page 18 of 28

03570-0-051

–8

–4–2–60V E N O P (V )

86–800–400–200–6000V V O U T (m V )

400200800600

TIME (ns)

100

Figure 50. ENOP Disable Time, 900 MHz

BASEBAND DAC INTERFACE

The recommended baseband input swing and bias levels of the AD8349’s differential baseband inputs allow for direct

connection to most baseband DACs without the need for any external active components. Typically these DACs have a differential full-scale output current from 0 mA to 20 mA on each differential output. These currents can be easily converted to voltages using ground-referenced shunt resistors. Most baseband DACs for transmit chains are designed with two DACs in a single package.

AD9777 INTERFACE

The AD977x family of dual DACs is well suited to driving the baseband inputs of the AD8349. The AD9777 is a dual 16-bit DAC that can generate either a baseband output or a complex IF using the device’s complex modulator.

The basic interface between the AD9777’s I OUT outputs and the AD8349’s differential baseband inputs is shown in Figure 51. The Resistors R1 and R2 set the dc bias level, and R3 sets the amplitude of the baseband input voltage swing.

Figure 51. Basic AD9777 to AD8349 Interface

0.15

0.30

0.450.600.750.901.051.201.351.50D I F F E R E N T I A L I Q S W I N G (V p -p )

R3 (?)

10100 1.103

03570-0-053

Figure 52. Relationship Between R3 in Figure 51 and Peak

Baseband Input Voltage

BIASING AND FILTERING

A value of 40 ? on R1 and R2 in Figure 51 will generate the required 400 mV dc bias. Note that this is independent of the value of R3. Figure 52 shows the relationship between the value of R3 and the peak baseband input voltage with the 40 ?

resistors in place. From Figure 52, it can be seen that a value of 240 ? will provide a peak-to-peak swing of approximately 1.2 V p-p differential into the AD8349’s baseband inputs. The closest available resistor values are 40.2 ? and 240 ?, and these values were used in the characterization of the AD8349 when the DAC was used as a signal source.

When using a DAC, low-pass image reject filters are typically used to eliminate images that are produced by the DAC. They provide the added benefit of eliminating broadband noise that might feed into the modulator from the DAC.

Figure 53 shows a single sideband spectrum at 2140 MHz. The baseband sine and cosine signals come from the digital output of a Rohde & Schwarz AMIQ arbitrary waveform generator. These signals drive the AD9777 dual DAC, which in turn drives the AD8349’s baseband inputs. Note that the AD9777’s complex modulator is not being used.

Due to offset voltages, internal device mismatch, and imperfect quadrature over the AD8349’s operating range, the SSB

spectrum has a number of undesirable components such as LO feedthrough and undesired sideband leakage. When the

AD8349 is driven by a modulated baseband signal, (e.g. 8-PSK, GMSK, QPSK, or QAM), these nonidealities will manifest themselves as degraded error vector magnitude (EVM) and degraded spectral purity.

AD8349

Rev. A | Page 19 of 28

–90

–80–70

–60–50–40–30–20–10

010A M P L I

T U D E (d B m )

03570-0-054

CENTER 2.14GHz

Figure 53. AD8349 Single Sideband Spectrum at 2140 MHz

REDUCING UNDESIRED SIDEBAND LEAKAGE

Undesired sideband leakage is the result of phase and amplitude imbalances between the I and Q channel baseband signals. Therefore, to reduce the undesired sideband leakage, the amplitude and phase of the baseband signals have to be matched at the mixer cores. Because of mismatches in the baseband input paths leading to the mixers, perfectly matched baseband signals at the pins of the device may not be perfectly matched when they reach the mixers. Therefore, slight

adjustments have to be made to the phase and amplitudes of the baseband signals to compensate for these mismatches. Begin by making one of the inputs, say the I channel, the reference signal. Then adjust the amplitude and phase of the Q channel’s signal until the unwanted sideband power reaches a trough. The AD9777 has built-in gain adjust registers that allow this to be performed easily. If an iterative adjustment is

performed between the amplitude and the phase, the undesired sideband leakage can be minimized significantly.

Note that the compensated sideband rejection performance degrades as the operating baseband frequency is moved away from the frequency at which the compensation was performed. As a result, the frequency of the I and Q sine waves should be approximately half the baseband bandwidth of the modulated carrier. For example, if the modulator is being used to transmit a single WCDMA carrier whose baseband spectrum spans from dc to 3.84/2 MHz, the calibration could be effectively performed with 1 MHz I and Q sine waves.

REDUCTION OF LO FEEDTHROUGH

Because the I and Q signals are being multiplied with the LO, any internal offset voltages on these inputs will result in leakage of the LO to the output. Additionally, any imbalance in the LO to RF in the mixers will also cause the LO signal to leak through the mixer to the RF output. The LO feedthrough is clearly visible in the single sideband spectrum. The nominal LO feedthrough of –42 dBm can be reduced further by applying offset compensation voltages on the I and Q inputs. Note that

the LO feedthrough is reduced by varying the differential offset voltages on the I and Q inputs (xBBP – xBBN), not by varying the nominal bias level of 400 mV . This is easily accomplished by programming and then storing the appropriate DAC offset code required to minimize the LO feedthrough. This, however,

requires a dc-coupled path from the DAC to the I and Q inputs. The procedure for reducing the LO feedthrough is simple. A differential offset voltage is applied from the I DAC until the LO feedthrough reaches a trough. With this offset level held, a differential offset voltage is applied to the Q DAC until a lower trough is reached (This is an iterative process).

Figure 54 shows a plot of LO feedthrough vs. I channel offset (in mV) after the Q channel offset has been nulled. This suggests that the compensating offset voltage should have a resolution of at least 100 μV to reduce the LO feedthrough to be less than –65 dBm. Figure 55 shows the single sideband spectrum at 2140 MHz after the nulling of the LO. The reduced LO feedthrough can clearly be seen when compared with the performance shown in Figure 53.

Compensated LO feedthrough degrades somewhat as the LO frequency is moved away from the frequency at which the compensation was performed. This variation is very small across a 30 MHz or 60 MHz cellular band, however. This small variation is due to the effects of LO-to-RF output leakage around the package and on the board.

–70

–60–58–56–54

–52C A R R I E R F E E D T H R O U G H (d B m )

–62–68

–66–643.0

4.0 4.5

5.0 5.5

3.5IOPP-IOPN (mV)

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Figure 54. Plot of LO Feedthrough vs. I Channel Baseband Offset

(Q Channel Offset Nulled)

AD8349

Rev. A | Page 20 of 28

–90

–80–70

–60–50–40–30–20–10

010A M P L I T U D E (d B m )

CENTER 2.14GH z

03570-0-077

Figure 55. AD8349 Single Sideband Spectrum at 2140 MHz after LO Nulling

SIDEBAND SUPPRESSION AND LO FEEDTHROUGH VS. TEMPERATURE

In practical applications, reduction of LO feedthrough and

undesired sideband suppression can be performed as a one time calibration, with the required correction factors being stored in nonvolatile RAM. These compensation schemes hold up well over temperature. Figure 40 and Figure 41 show the variation in LO feedthrough and sideband suppression over temperature after compensation is performed at 25°C.

SINGLE SIDEBAND PERFORMANCE VS. BASEBAND DRIVE LEVEL

Figure 56 shows the SSB output power and noise floor in

dBc/100 kHz versus baseband drive level at LO frequencies of 940 MHz, 1960 MHz, and 2140 MHz. IMPROVING THIRD HARMONIC DISTORTION

While sideband suppression can be improved by adjusting the relative baseband amplitudes and phase, the only means

available to reduce the third harmonic is to reduce the output power. (See Figure 19, Figure 20, and Figure 21). It is worth noting, however, that as the output power is reduced, the noise floor, in dBc, stays fairly constant at the higher end of the power curve (Figure 56). This indicates that the output power can be reduced to a level that yields an acceptable third harmonic without incurring a signal-to-noise ratio penalty. The constant SNR vs. output power relationship also indicates that baseband voltage variations can be effectively used to control system output power and/or regulate signal chain gain.

–14

–10–6–8–12–2–44

260–104–90–86–88–84–102

–100–98–96–94–920.2

0.3

0.4

0.5

0.8

0.6

0.9

1.0

1.2

1.1

0.7

03570-0-056

DIFFERENTIAL BASEBAND DRIVE (V p-p)

S S B O U T P U T P O W E R (d B m )

20 M H z N O I S E F L O O R (d B C /100k H z )

Figure 56. SSB P OUT and 20 MHz Noise Floor vs. Baseband Drive Level

(F LO = 940 MHz, 1960 MHz, and 2140 MHz)