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KK74HC74AN中文资料

TECHNICAL DATA

KK 74HC74A

The KK compatible with LS/ALSTTL outputs.

asynchronous.

? Outputs Directly Interface to CMOS, NMOS, and TTL

? Operating Voltage Range: 2.0 to 6.0 V

? Low Input Current: 1.0 μA

? High Noise Immunity Characteristic of CMOS Devices

and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don’t care

LOGIC DIAGRAM

PIN 14 =V CC

PIN 7 = GND

MAXIMUM RATINGS*

Symbol Parameter Value

Unit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

V IN DC Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V

V OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 V

I IN DC Input Current, per Pin ±20 mA

I OUT DC Output Current, per Pin ±25 mA

I CC DC Supply Current, V CC and GND Pins ±50 mA

P D Power Dissipation in Still Air, Plastic DIP** SOIC Package**750

500

Tstg Storage Temperature -65 to +150 °C

T L Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min

Max

Unit V CC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V

T A Operating Temperature, All Package Types -55 +125 °C

t r, t f Input Rise and Fall Time (Figure 1) V CC =2.0 V

V CC =4.5 V

V CC =6.0 V 0

1000

500

400

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or V OUT)≤V CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

V CC

Guaranteed Limit Symbol Parameter

Test Conditions V

25 °C

to -55°C ≤85 °C ≤125 °C Unit

V IH

Minimum High-Level Input Voltage V OUT =0.1 V or V CC -0.1 V ?I OUT ?≤ 20 μA

2.04.56.0 1.5

3.15

4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V IL Maximum Low -Level Input Voltage

V OUT =0.1 V or V CC -0.1 V ?I OUT ? ≤ 20 μA

2.04.56.00.5 1.351.8 0.5 1.35 1.8 0.5 1.35 1.8 V

V OH

Minimum High-Level Output Voltage V IN =V IH or V IL

?I OUT ? ≤ 20 μA 2.04.56.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V

V IN =V IH or V IL ?I OUT ? ≤ 4.0 mA ?I OUT ? ≤ 5.2 mA

4.56.0 3.98

5.48 3.84 5.34 3.7 5.2

V OL

Maximum Low-Level Output Voltage V IN =V IH or V IL

?I OUT ? ≤ 20 μA 2.04.56.00.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V

V IN =V IH or V IL ?I OUT ? ≤ 4.0 mA ?I OUT ? ≤ 5.2 mA 4.56.0 0.260.26 0.33 0.33 0.4 0.4

I IN Maximum Input Leakage Current V IN =V CC or GND 6.0±0.1

±1.0

μA

I CC

Maximum Quiescent Supply Current (per Package)

V IN =V CC or GND I OUT =0μA

6.0

2.0 20 80 μA

Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,V CC=5.0 V C PD

Used to determine the no-load dynamic power consumption:

P D=C PD V CC2f+I CC V CC 39

TIMING REQUIREMENTS (C L=50pF,Input t r=t f=6.0 ns)

V CC Guaranteed Limit Symbol Parameter

V 25 °C

to-

55°C ≤85°C ≤125°C

Unit

t su Minimum Setup Time, Data to Clock (Figure 3) 2.0

4.5

6.080

100

120

t h Minimum Hold Time, Clock to Data (Figure 3) 2.0

4.5

6.03.0

3.0

t rec Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) 2.0

4.5

6.0

8.0

t w Minimum Pulse Width, Clock (Figure 1) 2.0

4.5

6.060

t w Minimum Pulse Width, Set or Reset (Figure 2) 2.0

4.5

6.060

t r, t f Maximum Input Rise and Fall Times (Figure 1) 2.0

4.5

6.01000

500

400

1000

500

400

1000

500

400

Figure 1. Switching Waveform Figure 2. Switching Waveform

EXPANDED LOGIC DIAGRAM