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5962-9753401QDA中文资料

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FEATURES

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1413121110981A 1B 1Y 2A 2B 2Y GND

V CC 4B 4A 4Y 3B 3A 3Y

SN54LVC08A...J OR W PACKAGE

SN74LVC08A...D, DB, NS, OR PW PACKAGE

(TOP VIEW)

12019

910111213

4567818

1716

1514

4A NC 4Y NC 3B

1Y NC 2A NC 2B

1B 1A N C 3Y 3A

V 4B

2Y G N D N C SN54LVC08A...FK PACKAGE

(TOP VIEW)

C C

NC - No internal connection

SN74LVC08A...RGY PACKAGE

(TOP VIEW)1

23456

1312111094B 4A 4Y 3B 3A

1B 1Y 2A 2B 2Y

V G N D

C C

DESCRIPTION/ORDERING INFORMATION

The 'LVC08A devices perform the Boolean function Y +A ?B or Y +A )B in positive logic.

SN54LVC08A,SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P–JANUARY 1993–REVISED AUGUST 2005

?Operate From 1.65V to 3.6V

?Latch-Up Performance Exceeds 250mA Per JESD 17

?Specified From –40°C to 85°C,–40°C to 125°C,and –55°C to 125°C

ESD Protection Exceeds JESD 22

?Inputs Accept Voltages to 5.5V –2000-V Human-Body Model (A114-A)?Max t pd of 4.1ns at 3.3V

–200-V Machine Model (A115-A)

?Typical V OLP (Output Ground Bounce)–1000-V Charged-Device Model (C101)

<0.8V at V CC =3.3V,T A =25°C

Typical V OHV (Output V OH Undershoot)>2V at V CC =3.3V,T A =25°C

The SN54LVC08A quadruple 2-input positive-AND gate is designed for 2.7-V to 3.6-V V CC operation,and the SN74LVC08A quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V V CC operation.Inputs can be driven from either 3.3-V or 5-V devices.This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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A B

SN54LVC08A,SN74LVC08A

QUADRUPLE2-INPUT POSITIVE-AND GATES

SCAS283P–JANUARY1993–REVISED AUGUST2005

ORDERING INFORMATION

T A PACKAGE(1)ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to85°C QFN–RGY Reel of1000SN74LVC08ARGYR LC08A

Tube of50SN74LVC08AD

SOIC–D Reel of2500SN74LVC08ADR LVC08A

Reel of250SN74LVC08ADT

SOP–NS Reel of2000SN74LVC08ANSR LVC08A

–40°C to125°C

SSOP–DB Reel of2000SN74LVC08ADBR LC08A

Tube of90SN74LVC08APW

TSSOP–PW Reel of2000SN74LVC08APWR LC08A

Reel of250SN74LVC08APWT

CDIP–J Tube of25SNJ54LVC08AJ SNJ54LVC08AJ

–55°C to125°C CFP–W Tube of150SNJ54LVC08AW SNJ54LVC08AW

LCCC–FK Tube of55SNJ54LVC08AFK SNJ54LVC08AFK (1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at

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FUNCTION TABLE

(EACH GATE)

INPUTS OUTPUT

A B

H H H

L X L

X L L

LOGIC DIAGRAM,EACH GATE(POSITIVE LOGIC)

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Absolute Maximum Ratings(1)

SN54LVC08A,SN74LVC08A QUADRUPLE2-INPUT POSITIVE-AND GATES SCAS283P–JANUARY1993–REVISED AUGUST2005

over operating free-air temperature range(unless otherwise noted)

MIN MAX UNIT V CC Supply voltage range–0.5 6.5V

V I Input voltage range(2)–0.5 6.5V

V O Output voltage range(2)(3)–0.5V CC+0.5V

I IK Input clamp current V I<0–50mA I OK Output clamp current V O<0–50mA I O Continuous output current±50mA

Continuous current through V CC or GND±100mA

D package(4)86

DB package(4)96

θJA Package thermal impedance NS package(4)76°C/W

PW package(4)113

RGY package(5)47

T stg Storage temperature range–65150°C

P tot Power dissipation(6)(7)T A=–40°C to125°C500mW (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3)The value of V CC is provided in the recommended operating conditions table.

(4)The package thermal impedance is calculated in accordance with JESD51-7.

(5)The package thermal impedance is calculated in accordance with JESD51-5.

(6)For the D package:above70°C,the value of P tot derates linearly with8mW/K.

(7)For the DB,NS,and PW packages:above60°C,the value of P tot derates linearly with5.5mW/K.

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Recommended Operating Conditions (1)

SN54LVC08A,SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P–JANUARY 1993–REVISED AUGUST 2005

SN54LVC08A –55°C to 125°C

UNIT

MIN

MAX Operating

2 3.6

V CC Supply voltage V Data retention only 1.5V IH High-level input voltage V CC =2.7V to 3.6V 2

V V IL Low-level input voltage V CC =2.7V to 3.6V

0.8V V I Input voltage 0 5.5V V O Output voltage

0V CC V V CC =2.7V –12I OH High-level output current mA V CC =3V –24V CC =2.7V 12I OL Low-level output current mA V CC =3V 24?t/?v Input transition rise or fall rate

8ns/V (1)

All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.

SN74LVC08A

T A =25°C –40°C to 85°C –40°C to 125°C UNIT

MIN

MAX MIN MAX MIN MAX Operating

1.65 3.6

V CC

Supply voltage V Data retention only 1.5

1.5

V CC =1.65V to 1.95V 0.65×V CC

0.65×V CC

High-level V IH

V CC =2.3V to 2.7V 1.7 1.7 1.7V

input voltage

V CC =2.7V to 3.6V

V CC =1.65V to 1.95V 0.35×V CC

0.35×V CC

Low-level V IL V CC =2.3V to 2.7V 0.70.70.7V input voltage V CC =2.7V to 3.6V

0.80.80.8V I Input voltage 0 5.50 5.50 5.5V V O

Output voltage

0V CC 0

V CC 0

V CC V V CC =1.65V

–4–4–4V CC =2.3V –8–8–8High-level I OH

mA output current

V CC =2.7V –12–12–12V CC =3V –24–24–24V CC =1.65V

444V CC =2.3V 888Low-level I OL

mA output current

V CC =2.7V 121212V CC =3V

242424?t/?v Input transition rise or fall rate 8

ns/V (1)

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Electrical Characteristics Electrical Characteristics

SN54LVC08A,SN74LVC08A QUADRUPLE2-INPUT POSITIVE-AND GATES SCAS283P–JANUARY1993–REVISED AUGUST2005

over recommended operating free-air temperature range(unless otherwise noted)

SN54LVC08A

PARAMETER TEST CONDITIONS V CC–55°C to125°C UNIT

MIN TYP(1)MAX

I OH=–100μA 2.7V to3.6V V CC–0.2

2.7V 2.2

V OH I OH=–12mA V

3V 2.4

I OH=–24mA3V 2.2

I OL=100μA 2.7V to3.6V0.2

V OL I OL=12mA 2.7V0.4V

I OL=24mA3V0.55

I I V I=5.5V or GND 3.6V±5μA

I CC V I=V CC or GND,I O=0 3.6V10μA

?I CC One input at V CC–0.6V,Other inputs at V CC or GND 2.7V to3.6V500μA

C i V I=V CC or GN

D 3.3V5pF

(1)T A=25°C

over recommended operating free-air temperature range(unless otherwise noted)

SN74LVC08A

PARAMETER TEST CONDITIONS V CC T A=25°C–40°C to85°C–40°C to125°C UNIT

MIN TYP MAX MIN MAX MIN MAX

I OH=–100μA 1.65V to3.6V V CC–0.2V CC–0.2V CC–0.3

I OH=–4mA 1.65V 1.29 1.2 1.05

I OH=–8mA 2.3V 1.9 1.7 1.55

V OH V

2.7V 2.2 2.2 2.05

I OH=–12mA

3V 2.4 2.4 2.25

I OH=–24mA3V 2.3 2.22

I OL=100μA 1.65V to3.6V0.10.20.3

I OL=4mA 1.65V0.240.450.6

V OL I OL=8mA 2.3V0.30.70.75V

I OL=12mA 2.7V0.40.40.6

I OL=24mA3V0.550.550.8

I I V I=5.5V or GND 3.6V±1±5±20μA

I CC V I=V CC or GND,I O=0 3.6V11040μA

One input at V CC–0.6V,

?I CC 2.7V to3.6V5005005000μA Other inputs at V CC or GND

C i V I=V CC or GN

D 3.3V5pF

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Switching Characteristics

Operating Characteristics

SN54LVC08A,SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P–JANUARY 1993–REVISED AUGUST 2005

over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1)

SN54LVC08A

FROM TO PARAMETER

V CC –55°C to 125°C

UNIT

(INPUT)(OUTPUT)

MIN

MAX 2.7V 4.8t pd

A or B

ns 3.3V ±0.3V

1 4.1

over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1)

SN74LVC08A

FROM TO PARAMETER

V CC

T A =25°C –40°C to 85°C –40°C to 125°C UNIT

(INPUT)

(OUTPUT)

MIN TYP MAX MIN MAX MIN MAX 1.8V ±0.15V

159.319.8111.32.5V ±0.2V

1 2.9 6.41 6.919t pd

A or B

ns 2.7V 13 4.61 4.8163.3V ±0.3V

2.6

3.9

4.11

5.5t sk(o)

3.3V ±0.3V

1.5

ns T A =25°C

TEST PARAMETER

V CC TYP UNIT

CONDITIONS 1.8V

7C pd

Power dissipation capacitance per gate

f =10MHz

2.5V 9.8pF

3.3V

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PARAMETER MEASUREMENT INFORMATION

From Output Under Test

LOAD CIRCUIT

Open Data Input

Timing Input

V I

0 V

V I

0 V

Input

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS PULSE DURATION

V OH

V OL

V I

0 V Input

Output Waveform 1S1 at V LOAD (see Note B)

Output Waveform 2S1 at GND (see Note B)

V OL

V OH V LOAD /2

0 V

≈0 V

V I

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING

Output

t PLH /t PHL t PLZ /t PZL t PHZ /t PZH

Open V LOAD GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .

H.All parameters and waveforms are not applicable to all devices.

Output Control V I

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

3.3 V ± 0.3 V

1 k ?500 ?500 ?500 ?

V CC R L 2 × V CC 2 × V CC 6 V 6 V

V LOAD C L 30 pF 30 pF 50 pF 50 pF

0.15 V 0.15 V 0.3 V 0.3 V

V ?V CC V CC 2.7 V 2.7 V

V I V CC /2V CC /21.5 V 1.5 V

V M t r /t f ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns

INPUTS SN54LVC08A,SN74LVC08A

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCAS283P–JANUARY 1993–REVISED AUGUST 2005

Figure 1.Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

5962-9753401Q2A ACTIVE LCCC FK201TBD POST-PLATE N/A for Pkg Type 5962-9753401QCA ACTIVE CDIP J141TBD A42SNPB N/A for Pkg Type 5962-9753401QDA ACTIVE CFP W141TBD A42N/A for Pkg Type SN74LVC08AD ACTIVE SOIC D1450Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADBLE OBSOLETE SSOP DB14TBD Call TI Call TI

SN74LVC08ADBR ACTIVE SSOP DB142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADBRE4ACTIVE SSOP DB142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADBRG4ACTIVE SSOP DB142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADE4ACTIVE SOIC D1450Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADG4ACTIVE SOIC D1450Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADR ACTIVE SOIC D142500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADRE4ACTIVE SOIC D142500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADRG4ACTIVE SOIC D142500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADT ACTIVE SOIC D14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADTE4ACTIVE SOIC D14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ADTG4ACTIVE SOIC D14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ANSR ACTIVE SO NS142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ANSRE4ACTIVE SO NS142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ANSRG4ACTIVE SO NS142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APW ACTIVE TSSOP PW1490Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APWE4ACTIVE TSSOP PW1490Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APWG4ACTIVE TSSOP PW1490Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM SN74LVC08APWLE OBSOLETE TSSOP PW14TBD Call TI Call TI

SN74LVC08APWR ACTIVE TSSOP PW142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APWRE4ACTIVE TSSOP PW142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APWRG4ACTIVE TSSOP PW142000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APWT ACTIVE TSSOP PW14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

SN74LVC08APWTE4ACTIVE TSSOP PW14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08APWTG4ACTIVE TSSOP PW14250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC08ARGYR ACTIVE QFN RGY141000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-2-260C-1YEAR

SN74LVC08ARGYRG4ACTIVE QFN RGY141000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-2-260C-1YEAR SNJ54LVC08AFK ACTIVE LCCC FK201TBD POST-PLATE N/A for Pkg Type SNJ54LVC08AJ ACTIVE CDIP J141TBD A42SNPB N/A for Pkg Type SNJ54LVC08AW ACTIVE CFP W141TBD A42N/A for Pkg Type (1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check https://www.wendangku.net/doc/9f9384291.html,/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.

Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVC08A,SN74LVC08A:

?Automotive:SN74LVC08A-Q1

?Enhanced Product:SN74LVC08A-EP

NOTE:Qualified Version Definitions:

?Automotive-Q100devices qualified for high-reliability automotive applications targeting zero defects

?Enhanced Product-Supports Defense,Aerospace and Medical Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Type Package Drawing Pins SPQ

Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)

P1(mm)W (mm)Pin1Quadrant SN74LVC08ADBR SSOP DB 142000330.016.48.2 6.6 2.512.016.0Q1SN74LVC08ADR SOIC D 142500330.016.4 6.59.0 2.18.016.0Q1SN74LVC08ANSR SO NS 142000330.016.48.210.5 2.512.016.0Q1SN74LVC08APWR TSSOP PW 142000330.012.47.0 5.6 1.68.012.0Q1SN74LVC08ARGYR

QFN

RGY

1000

180.0

12.4

3.85

1.35

8.0

12.0

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74LVC08ADBR SSOP DB142000346.0346.033.0 SN74LVC08ADR SOIC D142500346.0346.033.0 SN74LVC08ANSR SO NS142000346.0346.033.0 SN74LVC08APWR TSSOP PW142000346.0346.029.0 SN74LVC08ARGYR QFN RGY141000190.5212.731.8

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