V260H1-LE2
TFT LCD Preliminary Specification MODEL NO.: V260H1- LE2
TV Product Marketing & Management Div Approved By
Chao-Chun Chung
QA Dept. Product Development Div. Reviewed By
Hsin-nan Chen WT Lin
LCD TV Marketing and Product Management Div. Prepared By
CY Chang Delia Lin
CONTENTS -
1. GENERAL DESCRIPTION (5)
1.1 OVERVIEW (5)
1.2 FEATURES (5)
1.3 APPLICATION (5)
1.4 GENERAL SPECIFICATI0NS (5)
1.5 MECHANICAL SPECIFICATIONS (5)
2. ABSOLUTE MAXIMUM RATINGS (6)
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (6)
2.2 ELECTRICAL ABSOLUTE RATINGS (6)
2.2 ELECTRICAL ABSOLUTE RATINGS (7)
3. ELECTRICAL CHARACTERISTICS (7)
3.1 TFT LCD MODULE (7)
3.2 BACKLIGHT UNIT (9)
4. BLOCK DIAGRAM OF INTERFACE (10)
4.1 TFT LCD MODULE (10)
5. INTERFACE PIN CONNECTION (11)
5.1 TFT LCD MODULE (11)
5.2 BACKLIGHT UNIT (13)
5.3 BLOCK DIAGRAM OF INTERFACE (14)
5.4 LVDS INTERFACE (16)
5.5 COLOR DATA INPUT ASSIGNMENT (17)
6. INTERFACE TIMING (18)
6.1 INPUT SIGNAL TIMING SPECIFICATIONS (18)
6.2 POWER ON/OFF SEQUENCE (21)
7. OPTICAL CHARACTERISTICS (22)
7.1 TEST CONDITIONS (22)
7.2 OPTICAL SPECIFICATIONS (22)
8. DEFINITION OF LABELS (26)
8.1 CMO MODULE LABEL (26)
9. PACKAGING (27)
9.1 PACKING SPECIFICATIONS (27)
9.2 PACKING METHOD (27)
10. PRECAUTIONS (29)
10.1 ASSEMBLY AND HANDLING PRECAUTIONS (29)
10.2 SAFETY PRECAUTIONS (29)
10.3 STORAGE PRECAUTIONS (29)
11. REGULATORY STANDARDS (30)
11.1 SAFETY (30)
12. MECHANICAL CHARACTERISTIC (31)
REVISION HISTORY
Version Date Page
(New)Section Description Ver 1.0Jan. 28,’10All All Preliminary Specification was first issued.
2. ABSOLUTE MAXIMUM RATINGS 2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value Item
Symbol Min. Max. Unit Note Storage Temperature T ST -20 +60 oC (1) Operating Ambient Temperature
T OP 0 50 oC (1), (2) ±X, ±Y 30 Shock (Non-Operating)
S NOP ±Z - 30 G (3), (5) Vibration (Non-Operating)
V NOP - 1.0 G (4), (5) Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 oC).?
(b) Wet-bulb temperature should be 39 oC Max. (Ta > 40 oC). (c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 oC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 oC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 30 min, 1 time each X, Y , Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so
that the module would not be twisted or bent by the fixture.
Operating Range 40
60
20
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Value Item
Symbol Min. Max. Unit Note Power Supply Voltage Vcc -0.3 13.5 V Input Signal Voltage V IN -0.3 3.6 V (1)
2.2.2 BACKLIGHT CONVERTER UNIT
Item
Symbol Test Condition Min. Type Max. Unit Note Light Bar Voltage
V W Ta = 25 к - - 60 V RMS Converter Input Voltage
V BL
- 0 - 30 V
Control Signal Level - - -0.3 - 7 V
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function
operation should be restricted to the conditions described under Normal Operating Conditions.
3. ELECTRICAL CHARACTERISTICS 3.1 TFT LCD MODULE Ta = 25 ± 2 oC
Value Parameter
Symbol Min. Typ. Max. Unit Note Power Supply Voltage
V CC 10.8 12 13.2 V (1) Rush Current
I RUSH Ё Ё 3.5 A (2) White Pattern
Ё Ё 0.29 Ё A Horizontal Stripe
Ё Ё 0.47 Ё A Power Supply Current Black Pattern
Ё Ё 0.48 0.60 A (3) Differential Input High Threshold Voltage
V LVTH +100 Ё Ё mV Differential Input Low Threshold Voltage V LVTL Ё Ё -100 mV
Common Input Voltage V CM 1.0 1.2 1.4 V
Differential input voltage |V ID | 200 Ё 600 mV
LVDS interface Terminating Resistor R T Ё 100 Ё ohm
(4) Input High Threshold Voltage V IH 2.7 Ё 3.3 V
CMOS interface
Input Low Threshold Voltage V IL 0 Ё 0.7 V
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 oC, f v = 60
Hz, whereas a power dissipation check pattern below is displayed.
Active Area Active Area a. White Pattern b. Black Pattern
Vcc rising time is 470us
SW Vcc +12.0V
c. Horizontal Pattern
Note (4) The LVDS input characteristics are as follows:
3.2 BACKLIGHT UNIT
3.2.1 LED LIGHT BARCHARACTERISTICS (Ta = 25 ± 2 oC)
Value
Unit Note Parameter Symbol
Min. Typ. Max.
Light Bar Voltage V W- - 45.5 V RMS I L =120mA Forward Voltage V f 3.0 - 3.5 V RMS I L =120mA LED Current I L112.8 120 127.2 mA RMS
4. BLOCK DIAGRAM OF INTERFACE 4.1 TFT LCD MODULE
5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment
Pin Name Description Note
1 VCC +12V power supply
2 VCC +12V power supply
3 VCC +12V power supply
4 VCC +12V power supply
5 VCC +12V power supply
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
11 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
12 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
13 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
14 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
15 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2 (1)
16 GND Ground
17 OCLK- Odd pixel Negative LVDS differential clock input
18 OCLK+ Odd pixel Positive LVDS differential clock input. (1)
19 GND Ground
20 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
21 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3 (1)
22 N.C. No Connection
23 N.C. No Connection (3)
24 GND Ground
25 ERX0- Even pixel Negative LVDS differential data input. Channel 0
26 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
27 ERX1- Even pixel Negative LVDS differential data input. Channel 1
28 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
29 ERX2- Even pixel Negative LVDS differential data input. Channel 2
30 ERX2+ Even pixel Positive LVDS differential data input. Channel 2 (1)
31 GND Ground
32 ECLK- Even pixel Negative LVDS differential clock input.
33 ECLK+ Even pixel Positive LVDS differential clock input. (1)
34 GND Ground
35 ERX3- Even pixel Negative LVDS differential data input. Channel 3
36 ERX3+ Even pixel Positive LVDS differential data input. Channel 3 (1)
37 N.C. No Connection
38 N.C. No Connection (3)
39 GND Ground
40 N.C. No Connection
41 N.C. No Connection
42 N.C. No Connection
43 N.C. No Connection
44 N.C. No Connection (3)
45 SELLVDS High(3.3V) or open for VESA, Low (GND) for JEIDA (4)(5)
46 N.C. No Connection
47 N.C. No Connection
48 N.C. No Connection
49 N.C. No Connection
50 N.C. No Connection
51 N.C. No Connection
(3)
System side
R1 < 1K
LCM side System side Note (1) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
Note (2) LVDS connector pin order defined as follows
Note (3) Reserved for internal use. Please leave it open. Note (4) Low: JEIDA LVDS Format (Connect to GND), High or open: VESA Format. (Connect to +3.3V)
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below. CN: 51281-1094 (Molex) or equivalent
Pin № Symbol Feature 1
VLED- 2 VLED- 3 VLED- 4 VLED- 5 VLED- 6 VLED- Negative of LED String 7 NC NC 8 VLED+3 9 VLED+2 10 VLED+1 Positive of LED String
5.3 BLOCK DIAGRAM OF INTERFACE
CNF1
ER0-ER7 EG0-EG7 EB0-EB7
DE
Host Graphics Controller TxIN
PLL PLL
ER0-ER7
EG0-EG7
EB0-EB7
DE
Timing
Controller
ERx0+
ERx0-
ERx1+
ERx1-
ERx2+
ERx2-
ECLK+
ECLK-
RxOUT
100?
100?
100?
100?
100?
100?
100?
100?
100?
100?
100pF
100pF
100pF
100pF
100pF
ERx3-
ERx3+
PLL PLL
LVDS Transmitter THC63LVDM83A (LVDF83A)
LVDS Receiver ORx0+
ORx0-
ORx1+
ORx1-
ORx2+
ORx2-
OCLK+
OCLK-
100?
100?
100?
100?
100?
100?
100?
100?
100?
100pF
100pF
100pF
100pF
100pF
ORx3-
ORx3+
OR0-OR7 OG0-OG7 OB0-OB7
DCLK OR0-OR7 OG0-OG7 OB0-OB7 DCLK
ER0~ER7: Even pixel R data
EG0~EG7: Even pixel G data
EB0~EB7: Even pixel B data
OR0~OR7: Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7: Odd pixel B data
DE: Data enable signal
DCLK: Data clock signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the second pixel is even pixel.
5.4 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=H or open)
RXCLK?
JEDIA LVDS formatΚ(SELLVDS pin=L)
RXCLK?
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color. The higher the binary input, the brighter the color. The table below provides the assignment of the color versus data input.
Data Signal
Red Green Blue Color
R7R6R5R4R3R2R1R0G7G6G5G4G3G2G1G0B7B6B5B4B3B2B1B0
Basic Colors Black
Red
Green
Blue
Cyan
Magenta
Yellow
White
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Gray Scale Of Red Red(0) / Dark
Red(1)
Red(2)
:
:
Red(253)
Red(254)
Red(255)
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
1
:
:
1
1
1
:
:
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Gray Scale Of Green Green(0) / Dark
Green(1)
Green(2)
:
:
Green(253)
Green(254)
Green(255)
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
1
:
:
1
1
1
:
:
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Gray Scale Of Blue Blue(0) / Dark
Blue(1)
Blue(2)
:
:
Blue(253)
Blue(254)
Blue(255)
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
:
:
1
1
1
1
:
:
1
1
1
:
:
1
1
Note (1) 0: Low Level Voltage, 1: High Level Voltage
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS The input signal timing specifications are shown as the following table and timing diagram.
Signal Item
Symbol Min. Typ. Max. Unit Note Frequency
F clkin (=1/TC) 60 74.25 80 MHz
Input cycle to cycle jitter T rcl Ё Ё 200 ps (3) Spread spectrum modulation range F clkin_mod F clkin -2% Ё F clkin +2%
MHz LVDS Receiver Clock Spread spectrum modulation frequency F SSM 200
KHz (4) Setup Time Tlvsu 600 Ё Ё
ps LVDS Receiver Data Hold Time Tlvhd 600 Ё Ё ps
(5) F r5 47 50 53 Hz
Frame Rate F r6 57 60 63 Hz
Total Tv 1115 1125 1135 Th
Tv=Tvd+Tvb Display Tvd 1080 1080 1080 Th
Ё Vertical Active Display Term Blank Tvb 35 45 55 Th
Ё Total Th 1050 1100 1150 Tc
Th=Thd+Thb Display Thd 960 960 960 Tc
Ё Horizontal Active Display Term Blank Thb 90 140 190 Tc Ё
Note (1) Please make sure the range of pixel clock has follow the below equation Κ
Fclkin(max) Fr6 Tv Th ???
Fr5 Tv Th Fclkin(min)???
Note (2) This module is operated in DE only mode and please follow the input signal timing diagram
below Κ
INPUT SIGNAL TIMING DIAGRAM
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T
1
– TI
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
RXCLK+/-
RXn+/-
141T 143T 145T 147T 149T 1411T 14
13T Tc