JX-H42 Datasheet v1_3
JX-H42: HD CMOS Image Sensor With MIPI Interface General Description:
JX-H42 is an HD CMOS image sensor designed with a superior 3.0μm pixel with excellent low-light sensitivity and low dark current performance. It features a 60fps native high definition (HD) 720p video capability for camera applications in PC multimedia, security, and entertainment devices. The JX-H42 consists of a 1292x732 active pixel sensor (APS) array with an on-chip 10-bit ADC, programmable gain control (PGA), and correlated double sampling (CDS) to significantly reduce fixed pattern noise (FPN). The sensor also has many standard programmable and automatic functions. It has both the industry compliant DVP parallel and MIPI CSI2 serial interfaces. The external host controller can access this device through a standard serial interface. It is available in wafer-level packaged CSP.
Key Specifications:
Optical format Active Pixels Pixel size Color filter array Chief Ray Angle Shutter type Maximum Frame Rate Digital Supply voltage Power consumption Output Formats Sensitivity Max SNR Dynamic Range Dark Current Operating temperature Stable image temperature Analog I/O Active Standby 1/4” 1292H x 732V 3.0 x 3.0 μm RGB Bayer pattern 17.5 degrees linear Electronic rolling shutter 60fps 2.6 – 3.0V (2.8V nominal) 2.6 – 3.0V (2.8V nominal) 1.7 – 3.0V (2.8V nominal) 65 mA @30fps < 10 μA 10-bit RGB Raw Data 3300 mV/lux-sec 37 db 64 db
? Automatic functions: o ABLC – Automatic Black Level Calibration ? Programmable controls: o Gain, exposure, frame rate and size o Image mirror and flip o Window panning and cropping o I2C slave ID ? Output formats: o DVP parallel interface o MIPI CSI2 1 Lane ? Data formats: o 10-bit RAW RGB ? Others o Register group write capability o Frame synchronization o Black sun spot cancellation
Functional Block:
Component Order Information:
Part Number JX-H42-C1 Description CSP
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JX-H42: HD CMOS Image Sensor With MIPI Interface
Contents
Pin Diagram: ............................................................................................................................................................ 3 Functional Overview: ............................................................................................................................................... 5 Pixel Array Format: .................................................................................................................................................. 6 Data Output Format: ............................................................................................................................................... 7 Test Pattern Output: ................................................................................................................................................ 8 MIPI interface: ......................................................................................................................................................... 9 Frame Synchronization: ........................................................................................................................................... 9 Serial Interface: ..................................................................................................................................................... 10 Register Group Write Function: ............................................................................................................................. 11 Power on/off sequence: ........................................................................................................................................ 12 CRA Specifications: ................................................................................................................................................ 15 Mechanical Specifications: ..................................................................................................................................... 16 CSP Module Schematic (Reference): ...................................................................................................................... 17 Register Descriptions: ............................................................................................................................................ 18 Document Revision Control ................................................................................................................................... 23
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JX-H42: HD CMOS Image Sensor With MIPI Interface Pin Diagram:
JX-H42’s pin diagram is shown in Figure 1 and each pin’s description is shown in Table 1:
Figure 1. H42’s Top View CSP Pin Diagram
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JX-H42: HD CMOS Image Sensor With MIPI Interface
Table 1: Pin Description
Pin number A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 D5 D6 D7 E1 Pin name AGND HREF RSTB DOVDD SDA VH AVDD AVDD PCLK PWDN DOGND SCL DVDD VN D8/SID0 VSYNC Pin type Supply I/O Input Supply I/O reference Supply Supply I/O Input Supply I Supply Reference I/O I/O Description Analog ground Line data valid signal output. System synchronize reset when driven low, it resumes normal operation with all configuration register set to factory default Digital I/O supply voltage. Serial data, pull to DOVDD with a 4.3k ? resistor Internal analog reference. Analog supply voltage. Analog supply voltage. Pixel clock. Chip power down initiate pin. High active. Digital I/O ground Serial interface clock input. Digital core supply voltage. DVDD>=DOVDD Internal analog reference. DVP data output bit 8; I2C Slave ID programming bit<0>, default pull down internally. Vertical synchronize signal, drive high when last frame end and drive low before next frame start. Also can be programmed as frame synchronize input
AGND DVDD D6 D4 EXCLK MVDD D2/MDN D0/MCN D9/SID1
Supply Supply I/O I/O Input Supply I/O I/O I/O
E2 E3 E4 E5 E6 E7
D7 D5 DOGND DOVDD D3/MDP D1/MCP
I/O I/O Supply Supply I/O I/O
Analog ground Digital core supply voltage. DVDD>=DOVDD DVP data output bit 6. DVP data output bit 4. System clock input. MIPI block supply voltage, connect to DVDD pin. DVP data output bit 2 or MIPI data lane negative output. DVP data output bit 0 or MIPI clock lane negative output. DVP data output bit 9; I2C Slave ID programming bit<1>, default pull down internally. I2C slave ID can be programmed as “60/61”, “64/65”, “68/69” or ”6C/6D” for write and read. DVP data output bit 7. DVP data output bit 5. Digital I/O ground Digital I/O supply voltage. DVP data output bit 3 or MIPI data lane positive output. DVP data output bit 1 or MIPI clock lane positive output.
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JX-H42: HD CMOS Image Sensor With MIPI Interface
Functional Overview:
The JX-H42 is a progressive-scan CMOS image sensor. It has an on-chip, phase-locked loop (PLL) to generate internal clocks from a single master input clock running between 6 and 27MHz. Its analog data process and digital data process can handle up to 72Mp/s at corresponding pixel clock 72MHz. Figure 2 illustrates a block diagram of the sensor.
Figure 2. Functional Block Diagram
User can access and program JX-H42 sensor internal registers through the two-wire serial bus. The core of the sensor is a 1292x732 active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting and reading that row, the pixels in the row integrate the incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal path to apply gain and analog signal to digital signal converter (ADC). The ADC output passes through a digital processing path for black level calibration. Then the data will output though a DVP port or MIPI CSI2 standard interface.
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