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MAX5206ACUB中文资料

General Description

The MAX5204–MAX5207 serial input, voltage-output 16-bit digital-to-analog converters (DACs) provide monotonic 16-bit output over temperature without any adjustments.The MAX5204/MAX5205 operate from a +5V single power supply and use an external reference ranging from +4V to V DD , while the MAX5206/MAX5207 operate from a +3V or +3.3V single power supply and use an external reference ranging from +2V to V DD . The MAX5204–MAX5207 DAC output range is typically from 0 to V DD .

The MAX5204–MAX5207 feature a hardware reset input (CLR ) that when pulled low clears the output to zero code 0000 hex (MAX5205/MAX5207) or resets the out-put to midscale code 8000 hex (MAX5204/MAX5206). The 3-wire serial interface is compatible with SPI ?/QSPI ?/MI CROWI RE?. All devices have a low-power shutdown mode that reduces the supply current consumption to 1μA.

The MAX5204–MAX5207 are available in a space-sav-ing 10-pin μMAX ?package and are guaranteed over the extended temperature range (-40°C to +105°C).Refer to the MAX5200–MAX5203 data sheet for internal reference versions.

Applications

Low-Cost VCO/VCXO Frequency Control Industrial Process Control High-Resolution Offset Adjustment

Features

?Guaranteed 16-Bit Monotonic ?10-Pin 5mm ?3mm μMAX Package ?Rail-to-Rail Output Amplifier ?Single-Supply Operation

+5V (MAX5204/MAX5205)

+3V, +3.3V (MAX5206/MAX5207)?Low Power Consumption: 0.5mA

?Shutdown Mode Reduces Supply Current to 1μA ?SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface ?Power-On-Reset Sets Output to

Midscale (MAX5204/MAX5206)Zero-Scale (MAX5205/MAX5207)

MAX5204–MAX5207

Low-Cost, Voltage-Output, 16-Bit DACs in μMAX

________________________________________________________________Maxim Integrated Products 1

Pin Configuration

Ordering Information

19-2658; Rev 1; 10/04

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/9a15206266.html,.

Selector Guide appears at end of data sheet.SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.μMAX is a registered trademark of Maxim Integrated Products, Inc.

M A X 5204–M A X 5207

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V DD to AGND, DGND...............................................-0.3V to +6V AGND to DGND.........................................……….-0.3V to +0.3V REF, OUT to AGND.................................…-0.3V to (V DD + 0.3V)CLR , LDAC , SCLK, DIN, CS to DGND.......-0.3V to (V DD + 0.3V)Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (T A = +70°C)

10-Pin μMAX (derate 5.6mW/°C above +70°C).........444.4mW

Operating Temperature Ranges

MAX520_CUB......................................................0°C to +70°C MAX520_EUB.........................................…….-40°C to +105°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-60°C to +150°C Lead Temperature (soldering, 10s).................................+300°C

ELECTRICAL CHARACTERISTICS—MAX5204/MAX5205

(V DD = +4.75V to +5.25V, f SCLK = 10MHz (50% duty cycle), V REF = 4.096V, output load = 10k ?in parallel with 250pF, T A = T MIN to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX5204–MAX5207

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ELECTRICAL CHARACTERISTICS—MAX5204/MAX5205 (continued)

M A X 5204–M A X 5207

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ELECTRICAL CHARACTERISTICS—MAX5206/MAX5207

(V DD = +2.7V to +3.6V, f SCLK = 10MHz (50% duty cycle),V REF = 2.048V,output load = 10k ?in parallel with 250pF, T A = T MIN to T MAX ,unless otherwise noted. Typical values are at T A = +25°C.)

MAX5204–MAX5207

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Note 2:INL and DNL are guaranteed for outputs between 0.5V to (V DD - 0.5V).Note 3:Guaranteed monotonic.

Note 4:V REF = 4.096V (MAX5204/MAX5205) and V REF = 2.048V (MAX5206/MAX5207).Note 5:R L = ∞, digital inputs are at V DD or DGND.

ELECTRICAL CHARACTERISTICS—MAX5206/MAX5207 (continued)

(V DD = +2.7V to +3.6V, f SCLK = 10MHz (50% duty cycle),V REF = 2.048V,output load = 10k ?in parallel with 250pF, T A = T MIN to T MAX ,unless otherwise noted. Typical values are at T A = +25°C.)

GAIN ERROR vs. TEMPERATURE

M A X 5204 t o c 04

TEMPERATURE (°C)

G A I N E R R O R (%F S R )

-20

-0.08-0.06-0.04-0.0200.020.040.060.080.10

-0.10

-40

OFFSET ERROR vs. TEMPERATURE

M A X 5204 t o c 05

TEMPERATURE (°C)

O F F S E T E R R O R (m V )

-20

-0.30-0.20

-0.1000.100.200.300.40

-0.40

-40

100

10,000

100,000

OUTPUT NOISE DENSITY

vs. FREQUENCY

FREQUENCY (Hz)

V O L T A G E N O I S E D E N S I T Y (n V /√H z )

1000

700

0100200300400600

500M A X 5204–M A X 5207

SUPPLY CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

S U P P

L Y C U R R E N T (m A

)

7550

-40-25

0.6

0.7

0.8

0.91.0

0.5

INTEGRAL NONLINEARITY vs. CODE (A GRADE)

M A X 5204 t o c 02

DAC CODE

I N L (L S B )

600005000010000200003000040000-12

-8-4048

1216-16

70000

DIFFERENTIAL NONLINEARITY

vs. CODE

M A X 5204 t o c 03

DAC CODE

D N L (L S B )

-0.75-0.50-0.2500.250.500.751.00

-1.00

60000500001000020000300004000070000

HALF-SCALE OUTPUT SETTLING TIME (CODE FROM 4000H TO C000H)

4μs/div

OUT 1V/div

OUT 1mV/div

HALF-SCALE OUTPUT SETTLING TIME (CODE FROM C000H TO 4000H)

4μs/div

OUT 1V/div OUT 1mV/div

LARGE SIGNAL (1V/div)

SMALL SIGNAL (1mV/div)

R LOAD = 10k ?C LOAD = 250pF

Typical Operating Characteristics

(V DD = +5V, V REF = 4.096V, T A = +25°C, unless otherwise noted.)

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SHUTDOWN CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

S H U T D O W N C U R R E N T (μA )

-20

-0.75-0.50-0.2500.250.500.751.00

-1.00

-40

MAX5204–MAX5207

SOURCE-CURRENT CAPABILITY

SOURCE CURRENT (mA)O U T P U T V O L T A G E (V )

0.51.01.52.02.53.03.54.04.500

SINK-CURRENT CAPABILITY

SINK CURRENT (mA)

O U T P U T V O L T A G E (V )

0.51.01.52.02.53.03.54.04.50

MAJOR-CARRY OUTPUT GLITCH (CODE FROM 8000H TO 7FFFH)

MAX5204 toc11

1μs/div

OUT

(AC-COUPLED,5mV/div)

MAJOR-CARRY OUTPUT GLITCH (CODE FROM 7FFFH TO 8000H)

MAX5204 toc12

1μs/div

OUT

(AC-COUPLED,5mV/div)

Typical Operating Characteristics (continued)

(V DD = +5V, V REF = 4.096V, T A = +25°C, unless otherwise noted.)

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M A X 5204–M A X 5207

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Detailed Description

The MAX5204–MAX5207 serial 16-bit, voltage-output DACs are easily configured with a 3-wire serial interface.These devices offer full 16-bit performance with less than ±20LSB integral linearity error and less than ±1LSB dif-ferential linearity error, thus ensuring monotonic perfor-mance. Serial data transfer minimizes the number of package pins required. The MAX5204–MAX5207 include control-logic circuitry, a 16-bit data-in shift register, and a DAC register. The MAX5204–MAX5207 output is buffered and the full-scale output voltage is V REF (typ).The MAX5204–MAX5207 feature a hardware reset input (CLR ) that when pulled low clears the DAC output to zero code 0000 hex (MAX5205/MAX5207) or resets the DAC output to midscale code 8000 hex (MAX5204/MAX5206). For normal operation, connect CLR to V DD .

Reference Input

The MAX5204/MAX5205 (+5V supply) use an external reference between 4V to V DD , while the MAX5206/MAX5207 (+3V supply) use an external reference from 2V to V DD . The DAC output range is from 0 to V REF .

Digital Interface

The MAX5204–MAX5207 digital interface is a standard 3-wire connection compatible with SP I /QSP I

/MICROWIRE and most DSP interfaces. All of the digital input pins (CS , SCLK, DI N, CLR , and LDAC ) are TTL compatible. SCLK can accept clock frequencies as high as 10MHz for a +5V supply and 10MHz for a +3V or +3.3V supply.

One of two methods can be used when interfacing and updating the MAX5204–MAX5207. The first requires

Pin Description

Figure 1. MAX5204–MAX5207 Simplified Functional Diagram

MAX5204–MAX5207

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three digital inputs: CS , DIN, and SCLK (Figure 2). The active-low chip-select input (CS ) enables the serial data loading at the data input (DI N). Pull CS low and clock in each bit of the 16-bit digital word on the rising edge of the serial clock (SCLK). Two eight-bit bytes can be used, and do not require any additional time between them. Pulling CS high after loading the 16-bit word transfers that code into the DAC register and then updates the output. I f CS is not kept low during the entire loading of the 16-bit word, data will be corrupted.In this case, a new 16-bit word must be loaded. LDAC must be kept low at all times for the above instructions.An alternate method of interfacing and updating the MAX5204–MAX5207 can be done with a fourth digital input, the active-low load DAC (LDAC ). LDAC allows the output to update asynchronously after CS goes high. I t is useful when updating multiple MAX5204–MAX5207s synchronously when sharing a single LDAC and CS line. LDAC must be kept high at all times dur-ing the data loading sequence and must only be asserted when CS is high. Asserting LDAC when CS is low can cause corrupted data. To operate the MAX5204–MAX5207 using LDAC , pull LDAC high, pull CS low, load the 16-bit word as described in the previ-ous paragraph, and pull CS high again. Following these commands, the DAC output only updates when LDAC is asserted low (Figure 3).

Shutdown Mode

The low-power shutdown mode reduces supply current to typically 1μA and a maximum of 10μA. Shutdown mode is not activated through command words, as is common among D/A converters. These devices require careful manipulation of CS and SCLK (Figure 4).Shutting Down

To shut down the MAX5204–MAX5207, change the state of SCLK (either a high to low or low to high transi-tion can be used) and pulse two falling CS edges. I n order to keep the device in shutdown mode, SCLK must not change state. SCLK must remain in the state it is in after the two CS pulses.

Waking Up

There are two methods to wake up the MAX5204–MAX5207. Pulse one falling CS edge or transition SCLK.It takes 50μs typically from the CS falling edge or SCLK transition for the DAC to return to normal operation.

Power-On Reset

The MAX5204–MAX5207 have a power-on reset circuit to set the DAC’s output to a known state when V DD is first applied. The MAX5204/MAX5206 reset to midscale (code 8000 hex) upon power-up. The MAX5205/MAX5207 reset to zero-scale (code 0000 hex) upon power-up. This ensures that unwanted output voltages do not occur immediately following a system power-up,such as a loss of power. It is required to apply V DD first before any other input (DI N, SCLK, CLR , LDAC , CS ,and REF).

Figure 2. 3-Wire Interface Timing Diagram

M A X 5204–M A X 5207

10______________________________________________________________________________________

Applications Information

Power Supply and Bypassing

Considerations

Bypass the power supply with a 10μF capacitor in par-allel with a 0.1μF capacitor to AGND. Minimize lead lengths to reduce lead inductance. I f noise becomes an issue, use shielding and/or ferrite beads to increase isolation.

Output Buffer

The MAX5204–MAX5207 include low-offset, low-noise buffers enabling the output to source 15mA or sink 5mA. The output buffer operates at a slew rate of 0.6V/μs. With a 1/4 FS to 3/4 FS output transition, the buffer output typically settles to 1LSB in about 25μs.The MAX5204–MAX5207 output buffers provide a low 0.2?typical output impedance. The MAX5204–MAX5207 buffer amplifiers typically produce 120nV/√Hz noise at 10kHz.

Figure 4. Shutdown Timing

Figure 3. 4-Wire Interface Timing Diagram

MAX5204–MAX5207

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Bipolar Configuration

The MAX5204–MAX5207 are designed for unipolar opera-tion, but can be used in bipolar applications with an exter-nal amplifier and resistors. Figure 5 shows the MAX5204–MAX5207 configured for bipolar operation. The op amp is set for unity gain. Table 1 lists the offset binary code for this circuit. Output voltage range is ±V REF .

Layout Considerations

Digital and AC transient signals coupling to AGND can

create noise at the output. Connect AGND to the high-est quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards with sep-arate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pins together at the I C. The best ground connection is achieved by connecting the DAC’s DGND and AGND together, and then connecting that point to the system analog ground plane. If the DAC’s DGND is connected to the system digital ground, digital noise can get through the DAC’s analog portion.

Chip Information

TRANSISTOR COUNT: 8764PROCESS: BiCMOS

Figure 5. MAX5204–MAX5207 Typical Operating Circuit—Bipolar Output

M A X 5204–M A X 5207

12______________________________________________________________________________________

Selector Guide

MAX5204–MAX5207

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________13?2004 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to https://www.wendangku.net/doc/9a15206266.html,/packages .)