JPEG2000 Decoder Architecture for Mobile Applications

1 JPEG2000Decoder Architecture for Mobile

Applications

Maurizio Martina,Student Member,IEEE,Guido Masera,Member,IEEE,Gianluca Piccinini,

Fabrizio Vacca,Maurizio Zamboni,Member,IEEE

Abstract—This paper proposes a novel decoder architec-ture for the brand-new image coding standard JPEG2000. Innovative technologies involved in JPEG2000framework will lead to rapid development of new mobile multimedia applications.In this scenario a well known critical factor is that computational resources available on tetherless ter-minals are limited and valuable.Dedicated hardware units can completely ful?ll elaboration tasks,joining high system performance with reasonable power supply requirements. Starting from a preliminary overview of standard’s architec-ture and capabilities,a?exible DSP/FPGA based solution, obtained as a result of computational pro?ling analisys,is described.Then?nite precision e?ects are addressed,in order to implement an e?cient Wavelet?xed point copro-cessor.Finally,FPGA logic synthesis results are presented for most critical units.

I.Introduction

Thanks to innovative technologies involved in JPEG2000 framework[1],new interactive multimedia applications will be soon developed[2].Particularly in mobile environments, whose concern is growing more and more,only limited computational resources are available.E?cient hardware implementations can signi?cantly contribute to the wide integration of heterogeneous technologies,respecting the requirements of power consumption and performance im-posed by this scenario.

It is known that to achieve high performance with low complexity architectures,the use of?xed point data rep-resentation is strongly required.However this choice has the drawback that systems performance might be tackled by the e?ect of?nite precision representation.One of the ?rst steps in hardware design?ow is to describe target ar-chitecture using an high level programming language,in order to estimate how numerical errors could a?ect over-all system behavior.Whatever will be the implementation strategy followed,ASIC/FPGA or even DSP based,this class of problems oughts to be faced.It is worth noticing that?xed point based architectures grant noteworthy low-power?gures,which are particularly desirable in wireless environments.

In this paper a novel JPEG2000decoder hardware im-plementation is proposed,resorting to DSP/FPGA based design partitioning approach.Then interesting experimen-tal results of preliminary studies on?nite representation e?ects in JPEG2000environment are addressed.

The authors are with Dipartimento di Elettronica,Po-litecnico di Torino,Corso Duca degli Abruzzi24-10129 Torino-Italy-Ph:+39-011-5644102-FAX:+39-011-5644099-E-mail:masera(piccinini,zamboni)@polito.it,mar-tina(vacca)@vlsilab01.polito.it.

To best of our knowledge,no research works,focused on ?nite precision e?ects related to hardware issues,has been developed yet.In fact?nite precision e?ects have been commonly faced from algorithmical performance point of view,without emphasizing related hardware implementa-tion impact.Recently some works have been developed concerning DWT?nite precision representation sensitivity [3].However it is not yet known how the entropy encod-ing algorithm[4],employed by JPEG2000standard,could interact with DWT related issues.

II.JPEG2000standard overview

As far as the standard is concerned a Final Committee Draft became public in April2000[1]and?rst software implementations then available[5],[6]:?nal ISO document will be probably available since second quarter of2001. However such a challenging project has as a counterpart a noticeable complexity,even if it has been designed and developed with very much care from the implementation point of view.

As most of image compression algorithms,JPEG2000is composed by a transform stage followed by a quantization stage and an entropy coding stage.

A.The transform stage

While the current JPEG standard is based on the Dis-crete Cosine Transform(DCT),JPEG2000is based on the Discrete Wavelet Transform(DWT),which has very good decorrelation properties and yields excellent compression performance,also providing progressive transmission capa-bilities.In spite of making use of traditional?lter bank implementation(FB),a new technology based on Lifting Scheme(LS)[7]is employed as default mode.

Moreover two kinds of transforms can be considered: lossy or lossless(integer).The integer version of the DWT is often called Integer Wavelet Transform(IWT).It is no-ticeable that JPEG2000is able to support both the FB and the LS kernel,each of which can be used to evaluate either the DWT or the IWT.

The wavelet transform has to be performed both on im-age rows and columns in order to obtain a sub-band de-composition.

It has been demonstrated that synthesis?lters H(z) (low-pass)and G(z)(high-pass)can be expressed through their polyphase matrix P(z)representation[7].

P(z)elements are Laurent polynomials and,as the set of all Laurent polynomials,exhibit a commutative ring struc-ture,admitting polynomial division with remainder:long

2 division between two Laurent polynomials is not a unique

operation[7].To decompose P(z)the Euclidean algorithm

can be used to obtain:

P(z)=

m

i=1

1s i(z)

01

10

t i(z)1

K0

01/K

where s i(z)(primary lifting steps)and t i(z)(dual lifting steps)are?lters and K is a constant(see?g.1).As this factorization is not unique,several{s i(z)},{t i(z)}and K are admissible.

Even if the LS leads to a reduction of total computa-tional e?ort,with respect to the?lter bank implementa-tion,it has the drawback that introduces data dependency among subsequent lifting steps.As shown in?gure1the i-th lifting step needs results directly from the(i?1)-th one.Therefore,if the encoding rate is a critical issue,it is not feasible to adopt look-ahead strategies,where more lifting steps are computable concurrently.An easy way to tackle this disadvantage is to maximize internal step par-allelism,obtaining a fast evaluation of a single lifting step. This strategy can yield to huge waste of area and energy when many lifting steps are required.

In order to optimize the dynamic range around zero a DC-shift is provided.In fact the DC component could lead to an excessive growth of low-pass sub-band range.More-over the wavelet has the drawback that low-pass?lters can keep samples in a?xed range provided that a unitary gain is guaranteed.The joint e?ect of DC component suppres-sion and unitary gain assures that sample range constraints are ful?lled during the whole wavelet transform.

B.Quantizer

JPEG2000resorts to a scalar uniform quantizer as in-termediate stage between transform and entropy encodind phases.Surprisingly[8]this simple quantizer is near-optimal in many cases.Actually it is optimal if the in-put X has a Laplacian or an exponential probability den-sity function.Otherwise the performance are only slightly reduced with respect to the optimal quantizer.From an encoding perspective this block is mainly devoted to re-duce the quantity of information to be encoded.When an irreversible coding is performed it is necessary to convert transform results from R to N.On the other hand when a reversible transform is performed the quantizer does not introduce any modi?cations to the samples.Moreover this block adapts the di?erent sub-bands range to guarantee the coder to work in optimal conditions[1].

C.Entropy coder

The last stage of the compression chain is the entropy encoder.Entropy encoding process is mainly devoted to reduce the total amount of information needed to represent the image.

The entropy encoding algorithm used in JPEG2000is named EBCOT,which stands for Embedded Block Cod-ing with Optimal Truncation.Proposed in late1998by David Taubman[4],it is able to produce highly scalable compressed bit-streams.In particular two di?erent types of scalability are required by JPEG2000:the resolution scalability and the SNR(Signal to Noise Ratio)scalability. Resolution scalability can be easily achieved through the sub-band decomposition o?ered by wavelet transform.On the other hand,SNR scalability is a new important char-acteristic added by EBCOT algorithm.A compressed bit-stream is said to be SNR scalable if it can be decoded pro-gressively,such that every new reconstructed information lead to a reduction of the overall distortion.It is worth noticing that SNR progressive bit-streams are well suited for heterogeneous application’s environments,where sev-eral decoding systems with di?erent features need to share the same encoded data.This?gure represents a great de-part from currently available image coding standard,such as JPEG.

From an algorithmic point of view EBCOT is a block-based bitplane encoder.It subdivides each wavelet sub-band into a disjoint set of rectangular blocks,called code-blocks.Then the compression algorithm is independently applied to every code-block.This makes the entropy en-coding part of EBCOT very suitable for hardware parallel implementation,since it is possible to encode several code-block concurrently.Samples of every code-block are ar-ranged in some so called bitplane.Formally,if a code-block B i is made of samples x i(x,y),which can be represented as binary sign-magnitude quantities with P bit,then the bit-plane is V p

i

={x p

i

(x,y)∈B i}where x p

i

(x,y)is the p-th bit of binary representation of x i(x,y),starting from the most signi?cant one.The encoding of a code-block starts always from most signi?cant bitplanes and then moves downward to the least signi?cant ones.

The compressed information of every code-block is then arranged in several quality layers,to create an SNR scalable compressed bit-stream.Conceptually each quality layer monotonically increases the knowledge of samples magni-tudes,i.e.increases the SNR of reconstructed image.

D.Applications

It is worth noticing that SNR scalability provided by JPEG2000has not been emphasized enough yet.In fact new multimedia client-server perspectives can be explored also taking into account current wide di?usion of network based applications.

Usually,due to large amount of resources available in wireless base stations,high quality SNR progressive im-ages can be easily processed with slight implementation drawbacks.On the other hand,as far as mobile termi-nal side is concerned,low bit-rate streams are desirable, in order to relax memory and computational requirements. Poor interoperability performance can be achieved employ-ing old DCT based JPEG standard,since the decoder must be aware of all encoding options used to produce the compressed bit-stream.Moreover,when di?erent resolu-tion/quality representations are needed,the encoding pro-cess ought to be repeated for every required version. JPEG2000presents a great depart from traditional en-coding schemes and new classes of mobile devices can

3

2

2

(1)s (z)

(1)t (z)

(m)s (z)

(m)t

(z)

d z

x

x x d p =

=a d (0)

(0)

a (1)1/K

(1)

K

a

d

a

d

(m?1)(m?1)

(m)

(m)

LP

BP

Fig.1.Forward lifting

scheme

HW ? FPGA coprocessor

JPEG 2000 decoder External hardware Fig.3.System architecture

computational resources a dedicated implementation is rea-sonable at least for some key blocks.Resorting to pro?le analysis results,it is possible to identify most critical blocks in terms of required computational e?ort.

The proposed coprocessor based architecture makes use of a mixed DSP/FPGA system.In ?gure 3a functional view of the proposed decoder architecture is shown.Ex-ploiting system recon?gurability the same structure can be easily reused to obtain the coder,provided that de-coder blocks are substituted with encoder ones and minor changes to the DSP software are needed.

IV.The processors

An open standard,subjected to possible further re?ne-ments and improvements,as JPEG2000,need to operate in an open environment,able to guarantee the required degree of recon?gurability.Resorting to DSP and FPGA coprocessors a good ?exibility margin is granted,and the possibility of future enhancements and updating is assured .In fact,minor changes that impact directly on hardware coprocessors can be easily absorbed with recon?gurability provided by FPGA devices.On the other hand,extensions or signi?cant enhancements are straightforwardly mapped on DSP ?rmware .

4

Currently the two coprocessor architectures have been completely de?ned.A VHDL behavioral model has been developed and validated for both;besides the design?ow oughts to be completed up to the logic level.

A.The wavelet processor

Since the s i,t i blocks represented in?gure1are?nite impulse response?lters(FIR),the internal parallelism in-crease(resorting to several multipliers)is not always pos-sible:this is particularly true in many critical environment such as wireless ones.In fact,the overall number of mul-tipliers depends directly on the number of taps of every lifting step.

On the other hand the reduction of the number of bits de-voted to coe?cients representation enables the possibility to simplify the lifting step core moving from multiplier-based architectures to shifter-based ones.The key fea-ture in this strategy is the trade-o?between the number of bits employed and the sensitivity of LS to?nite preci-sion representation.From another perspective,in very high throughput applications,such as real-time video ones,this approach can be successfully exploited in order to reach low latency and high speed or low power solutions.It is worth noticing that the reduction of coe?cients preci-sion results in a more important decreasing of the overall computational complexity for longer?lters rather than for shorter ones.Looking at JPEG2000encoding system,as described in[1],two principal?lter types are presented: the9/7is employed to perform DWT in the lossy com-pression scheme,and the5/3,well suited to compute Inte-ger Wavelet Transform(IWT)in lossless image transform. The particular lifting scheme factorization adopted for5/3 wavelet has the interesting property that only two frac-tional bits are needed in order to completely represent all lifting step coe?cients.In this case,hardware implemen-tation can simply forget all?nite representation e?ects at the expense of just two fractional bits.On the other hand, the9/7wavelet can be evaluated by means of four lifting steps,each of which is substantially a two-tap FIR?lter. The main disadvantage of the9/7wavelet is the need of many?ltering operations with irrational coe?cients:hard-ware solutions ought to deal with typical?nite precision problems.

All the above considerations lead to the necessity of in-vestigating more deeply the?nite precision representation e?ects on JPEG2000encoding environment.

A.1Performed analysis and experimental results Essentially our main goal is to discover the monotonicity of JPEG2000performance in terms of PSNR versus m(the number of bits devoted to represent fractional part of DWT coe?cients).In order to get meaningful measures,a careful selection of test images have to be performed.

All experimental results presented in this paper have been obtained enabling JPEG2000lossy option.It is known that the9/7?lter achieves very good performance in?oating point software implementations of image codecs. This?gure can be easily explained taking into account that

P

S

N

R

[

d

B

]

bpp

Fig.4.PSNR Vs bpp

almost all modern general purpose CPUs own an high per-formance?oating point unit.

As the9/7coe?cients are not exactly represented as negative powers of2,performance reachable in?xed point hardware implementations might not be as good as soft-ware ones.It is very interesting to observe that the curve which represents PSNR versus the total bit-rate is a mono-tonic non-decreasing function,whereas the PSNR as a func-tion of m presents a minimum for m=3.In?gure4the behavior of a family of PSNR functions is depicted.The family has been obtained varying the number of fractional bits devoted to represent DWT coe?cients.In particu-lar,only a signi?cant set of values,selected to emphasize most relevant di?erences,is shown.The?rst curve repre-sents experimental results evaluated resorting to maximum hardware representation capability;results obtained with 8≤m≤14di?er from the‘golden sample’for just few fractions of dB,hence,they have been omitted for sake of clarity.

Surprisingly,very satisfactory results have been discov-ered employing just one or two fractional bits.For the sake of completeness,it must be noted that curves referred to one and two bits are completely overlapped,due to par-ticular factorization of the9/7?lter.This result perfectly suits preliminary considerations,exposed in II-A,enabling great hardware simpli?cation.The main reason of this re-markable performance variation lays in the shape of the mother wavelet associated to the9/7?lter.In fact the9/7 mother wavelet exhibits di?erent degrees of regularity and smoothness changing the number of fractional bits devoted to coe?cients representation[3].

A.2Estimated hardware impact

In previous sections general hardware environment prob-lems have been proposed,posing particular care to com-plexity/performance trade-o?.In order to sustain real-time video rate,highly parallel hardware solutions may be explored.This approach could lead to rapid complexity growth,due to the need of a large number of multiply and accumulate operations(MAC).In fact,traditional MAC

5

implementations are substantially multiplier based;in or-der to reach high rate applications,fully pipelined parallel multipliers are often a natural choice[10].Nevertheless,a large amount of gates is needed in order to map such ex-tensive units,especially when operands are wider than a single byte.

The one fractional bit proposed solution can lead to relevant advance in the implementation?eld,as allows a noteworthy area save.Correct interoperation between encoder and decoder will be granted resorting to possible JPEG2000Part II extensions,which could enable explicit signaling of user de?ned wavelet coe?cients quantization in the bitstream.The use of a parallel multiplier leads to a waste of resources since a modi?ed shifter could accomplish the same functionalities with lower cost.

Starting from these simple considerations a possible ar-chitecture for this modi?ed shifter have been described in VHDL language.Results obtained from logic synthesis on a Xilinx Virtex FPGA have shown an area occupation of just17LUTs for a16×2multiplier unit.As far as speed is concerned it has been possible to reach a clock frequency of145MHz resorting to two stages of pipeline.

On the other hand for a16×16unit an area of284 LUTs is required.Moreover a signi?cant performance loss have been noted since maximum clock frequency has de-creased down to77MHz.Even if this waste of area can be easily absorbed by modern deep sub-micron technologies,a strongly parallel wavelet architecture can require too many resources.

B.The EBCOT processor

A behavioral model of EBCOT coprocessor core has been successfully developed and validated resorting to VHDL language.The main idea lays in using a“sliding win-dow”approach,where a shift register mask glides over the code-block status bu?er(?g.5).Contexts genera-tion,accomplished by Window Processor block,can ex-ploit this technique completely forgetting bounds detection problems.The obtained structure enables the possibility to achieve high throughput due to reduction of memory bandwidth requirements.

At present a synthetizable structural view is under devel-opment.During this second stage of architecture develop-ment particular care have been posed to core’s reusability in order to obtain a System On Chip ready unit.It is worth noticing that arithmetic coding engine,which is one of the most relevant unit,consist of1271LUTs,comprehensive of both data and control units.The maximum achievable clock frequency is of69MHz.

As last stage of the design?ow a complete FPGA im-plementation have been planned:in particular Xilinx Vir-tex devices provide noteworthy arithmetic and memory re-sources.

V.Conclusions

Starting from JPEG2000documentation an analysis of the standard has been made focusing both on functionali-ties and their implementation impact.The latter issue has

Fig.5.EBCOT coprocessor architecture

been faced beginning from a study of total execution time needed by di?erent stages.Then?xed point representation e?ects have been studied for Discrete Wavelet Transform. The obtained results have guided the system architecture development shown in the paper.

Currently a complete JPEG2000decoder,particularly suited for mobile and wireless applications,is under devel-opment,resorting to a Texas Instruments DSP and a Xilinx Virtex FPGA device.It is worth noticing that,even if the DSP device used is not explicitly designed for image and video processing,the actual overall system performance are quite satisfactory.In fact,it is possible to decode up to9 medium sized(256×256)images per second.

References

[1]Martin Boliek(ed.),“JPEG2000Final Committee Draft,”

ISO/IEC FCD15444-1,Mar.2000.

[2] C.Christopoulos,T.Ebrahimi,and A.Skodras,“The upcoming

JPEG2000standard,”in Invited Tutorial to the11th Portuguese Conference on Pattern Recognition(RECPAD2000),May2000.

[3]M.Grangetto,E.Magli,M.Martina,and G.Olmo,“Optimiza-

tion and implementation of the integer wavelet transform for image coding,”Accepted at IEEE trans.on Image Processing.

[4]David Taubman,“High performance scalable image compres-

sion with EBCOT,”in Proceedings of the1999International Conference on Image Processing(ICIP-99),Los Alamitos,CA, Oct.24–281999,pp.344–348,IEEE.

[5]“URL:http://jj2000.ep?.ch/jj download/index.html,”.

[6]“URL:https://www.wendangku.net/doc/9e16128766.html,/products/products.htm,”.

[7]I.Daubechies and W.Sweldens,“Factoring wavelet transforms

into lifting steps,”Tech.Rep.,Bell Laboratories,Lucent Tech-nologies,1996.

[8]O.Egger,P.Fleury,T.Ebrahimi,and M.Kunt,“High-

performance compression of visual information–a tutorial re-view.I.Still pictures,”Proceedings of the IEEE,vol.87,no.6, pp.976–1013,June1999.

[9]M.D.Adams and F.Kossentini,“JasPer:a software-based

JPEG-2000codec implementation,”in IEEE International Con-ference on Image Processing,September2000,vol.2.

[10] A.Grzeszczak,M.K.Mandal,S.Panchanathan,and T.Yeap,

“VLSI implementation of discrete wavelet transform,”IEEE Trans.on very large scale integration systems,vol.4,no.4,pp.

421–433,Dec.1996.

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第1位—美国大峡谷-TheGrandCanyon 美国大峡谷是一个举世闻名的自然奇观，位于西部亚利桑那州西北部的凯巴布高原上，总面积2724．7平方公里。由于科罗拉多河穿流其中，故又名科罗拉多大峡谷，它是联合国教科文组织选为受保护的天然遗产之一。

第2位—澳大利亚的大堡礁—GreatBarrierReef 世界上有一个最大最长的珊瑚礁群，它就是有名的大堡礁—GreatBarrierReefo它纵贯蜿蜒于澳洲的东海岸，全长2011公里，最宽处161公里。南端最远离海岸241公里，北端离海岸仅16公里。在落潮时，部分的珊瑚礁露出水面形成珊瑚岛。 第3位—美国佛罗里达州—Flori—dl

佛罗里达风景最亮丽的棕榈海滩是全球著名的旅游天堂之一，适宜的气候、美丽的海滩、精美的饮食、艺术展览和文艺演出，即使是最挑剔的游客，在棕榈海滩也能满意而归。每年的四月，棕榈海滩的艺术活动是最丰富多彩的，包括各种海滩工艺品展览，其中于4月4 日启动的棕榈海滩爵士节以展示美国最杰出的爵士音乐而赢得了艺术爱好者的青睐。 第4位—新西兰的南岛-Soutls—land

新西兰位于南太平洋，西隔塔斯曼海与澳大利亚相望，西距澳大利亚1600公里，东邻汤加、斐济国土面积为二十七万平方公里，海岸线长6900千米，海岸线上有许多美丽的海滩。 第5位—好望角一CapeTown

好望角为太平洋与印度洋冷暖流水的分界，气象万变，景象奇妙，耸立于大海，更有高逾二干尺的达卡马峰，危崖峭壁，卷浪飞溅，令人眼界大开。 第6位—金庙-GoldenTemple

金庙位于印度边境城市阿姆利则。作为锡克教的圣地，阿姆利则意为“花蜜池塘”。金庙由锡克教第5代祖师阿尔琼1589年主持建造，1601年完工，迄今已有400年历史。因该庙门及大小19个圆形寺顶均贴满金箔，在阳光照耀下，分外璀璨夺目，一直以来被锡克人尊称为“上帝之殿”。 第7位—拉斯维加斯-LasVegas

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