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AT49BV160DT-70TU中文资料

Features Array?Single Voltage Read/Write Operation: 2.65V to 3.6V

?Access Time – 70 ns

?Sector Erase Architecture

–Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

–Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

?Fast Word Program Time – 10 μs

?Fast Sector Erase Time – 100 ms

?Suspend/Resume Feature for Erase and Program

–Supports Reading and Programming from Any Sector by Suspending Erase

of a Different Sector

–Supports Reading Any Word by Suspending Programming of Any Other Word ?Low-power Operation

–10 mA Active

–15 μA Standby

?VPP Pin for Write Protection and Accelerated Program Operation

?RESET Input for Device Initialization

?Flexible Sector Protection

?TSOP Package

?Top or Bottom Boot Block Configuration Available

?128-bit Protection Register

?Minimum 100,000 Erase Cycles

?Common Flash Interface (CFI)

?Green (Pb/Halide-free) Packaging

1.Description

The AT49BV160D(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each. The memory is divided into 39 sectors for erase operations. The device is offered in a 48-lead TSOP package. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming.

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see “Flexible Sector Protection” on page 6).

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory.

The VPP pin provides data protection. When the V PP input is below 0.4V, the program and erase functions are inhibited. When V PP is at 1.65V or above, normal program and erase operations can be performed. With V PP at 10.0V, the program (Dual-word

Program Command) operation is accelerated.

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2.Pin Configurations

2.1TSOP Top View (Type 1)

Pin Name Function A0 - A19Addresses CE Chip Enable OE Output Enable WE Write Enable RESET Reset

VPP Write Protection I/O0 - I/O15Data Inputs/Outputs NC No Connect

VCCQ Output Power Supply WP

Write Protect

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3.Block Diagram

4.Device Operation

4.1

Command Sequences

When the device is first powered on, it will be in the read mode. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the “Command Definition Table” on page 15 (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address and data are The address locations used in the command sequences are not affected by entering the com-mand sequences.

4.2Read

When the AT49BV160D(T) is in the read mode, with CE and OE low and WE high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

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4.3Reset

high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read mode, depending upon the state of the control inputs.

4.4Erase

Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The individual sectors can be erased by using the Sector Erase command.

4.4.1Sector Erase

The device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector address and the D0H Data Input com-mand are latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the second cycle provided the given sector has not been protected. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is t SEC . An attempt to erase a sector that has been protected will result in the operation terminat-ing immediately.

4.5Word Programming

Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis. Programming is accomplished via the Internal Device command register and is a two-bus cycle operation. The device will automatically generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase opera-tions can convert “0”s to “1”s. Programming is completed after the specified t BP cycle time. If the program status bit is a “1”, the device was not able to verify that the program operation was per-formed successfully. The status register indicates the programming status. While the program sequence executes, status bit I/O7 is “0”. While programming, the only valid commands are Read Status Register, Program Suspend and Program Resume.

4.6VPP Pin

The circuitry of the AT49BV160D(T) is designed so that the device cannot be programmed or erased if the V PP voltage is less that 0.4V. When V PP is at 1.65V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating.

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4.7

Read Status Register

The status register indicates the status of device operations and the success/failure of that oper-ation. The Read Status Register command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the memory, issue a Read command.

The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H when a Read Status Register command is issued.

(whichever occurs last), which prevents possible bus errors that might occur if status register or the status register will not indicate completion of a Program or Erase operation.

When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 4-1).

Note:

1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.

Table 4-1.

Status Register Bit Definition

WSMS ESS ES PS VPPS PSS SLS R 7

Notes

SR7 WRITE STA TE MACHINE STA TUS (WSMS)1 = Ready 0 = Busy

Check Write State Machine bit first to determine Word Program or Sector Erase completion, before checking program or erase status bits.

SR6 = ERASE SUSPEND STA TUS (ESS)1 = Erase Suspended

0 = Erase In Progress/Completed When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to “1” – ESS bit remains set to “1” until an Erase Resume command is issued.

SR5 = ERASE STA TUS (ES)1 = Error in Sector Erase 0 = Successful Sector Erase When this bit is set to “1”, WSM has applied the max number of erase pulses to the sector and is still unable to verify successful sector erasure.

SR4 = PROGRAM ST A TUS (PS)1 = Error in Programming 0 = Successful Programming When this bit is set to “1”, WSM has attempted but failed to program a word

SR3 = VPP STA TUS (VPPS)

1 = VPP Low Detect, Operation Abort 0 = VPP OK

The V PP status bit does not provide continuous indication of VPP level. The WSM interrogates V PP level only after the Program or Erase command sequences have been entered and informs the system if V PP has not been switched on. The V PP is also checked before the operation is verified by the WSM.

SR2 = PROGRAM SUSPEND STA TUS (PSS)1 = Program Suspended

0 = Program in Progress/Completed

When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to “1”. PSS bit remains set to “1” until a Program Resume command is issued.

SR1 = SECTOR LOCK STA TUS (SLS)

1 = Prog/Erase attempted on a locked sector; Operation aborted.0 = No operation to locked sectors

If a Program or Erase operation is attempted to one of the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode.SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R)This bit is reserved for future use and should be masked out when polling the status register.

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4.7.1

Clear Status Register

The WSM can set status register bits 1 through 7 and can clear bits 2, 6 and 7; but, the WSM cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4 and 5 indicate various error con-ditions, these bits can be cleared only through the Clear Status Register command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple sectors in sequence) before reading the status register to determine if an error occurred during those operations. The status register should be cleared before beginning another operation. The Read command must be issued before data can be read from the memory array. The status register can also be cleared by resetting the device.

4.8Flexible Sector Protection

The AT49BV160D(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-lock protection mode enabled.

4.8.1

Softlock and Unlock

The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector.4.8.2

Hardlock and Write Protect

The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock Soft-ware command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden.

?unlocked and the contents of the sector is read-only.

?When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command.

To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.

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Figure 4-1.Sector Locking State Diagram

Note:

1.The notation [X, Y and the two bits of the sector-lock status D[1:0].

Table 4-2.

Hardlock and Softlock Protection Configurations in Conjunction with WP

V PP WP Hard-lock Soft-lock Erase/Prog Allowed?Comments V CC /5V 000Y es No sector is locked

V CC /5V 001No Sector is Softlocked. The Unlock command can unlock the sector.

V CC /5V 011No Hardlock protection mode is enabled. The sector cannot be unlocked.V CC /5V 100Y es No sector is locked.

V CC /5V 101No Sector is Softlocked. The Unlock command can unlock the sector.

V CC /5V 110Y es Hardlock protection mode is overridden and the sector is not locked.

V CC /5V 111No Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command.V IL

Erase and Program Operations cannot be performed.

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4.8.3

Sector Protection Detection

A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode, a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, soft-locked, or hardlocked.

4.9Erase Suspend/Erase Resume

The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the memory. After the Erase Suspend com-mand is given, the device requires a maximum time of 15 μs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend com-mand. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume com-mand is a one-bus cycle command. The only valid commands while erase is suspended are Read Status Register, Product ID Entry, CFI Query, Program, Program Resume, Erase Resume, Sector Softlock/Hardlock, Sector Unlock.

4.10Program Suspend/Program Resume

The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 μs to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same and the command sequence for the erase resume and program resume are the same. The only other valid commands while program is suspended are Read Status Register, Product ID Entry, CFI Query and Program Resume.

4.11Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be accessed a software operation. For details, see “Operating Modes” on page 19.

Table 4-3.

Sector Protection Status

I/O1I/O0Sector Protection Status 00Sector Not Locked 01Softlock Enabled 10Hardlock Enabled

Both Hardlock and Softlock Enabled

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4.12

128-bit Protection Register

The AT49BV160D(T) contains a 128-bit register that can be used for security purposes in sys-tem design. The protection register is divided into two 64-bit sectors. The two sectors are designated as sector A and sector B. The data in sector A is non-changeable and is pro-grammed at the factory with a unique number. The data in sector B is programmed by the user and can be locked out such that data in the sector cannot be reprogrammed. To program sector B in the protection register, the two-bus cycle Program Protection Register command must be used as shown in the “Command Definition Table” on page 15. To lock out sector B, the two-bus cycle Lock Protection Register command must be used as shown in the “Command Definition Table” . Data bit D1 must be zero during the second bus cycle. All other data bits during the sec-ond bus cycle are don’t cares. To determine whether sector B is locked out, use the status of sector B protection command. If data bit D1 is zero, sector B is locked. If data bit D1 is one, sec-tor B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 16for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the pro-tection register. After determining whether sector B is protected or not, or reading the protection register, the Read command must be given to return to the read mode.

4.13Common Flash Interface (CFI)

CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to any address. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in “Common Flash Interface Definition Table” on page 24. To return to the read mode, issue the Read command.

4.14Hardware Data Protection

The Hardware Data Protection feature protects against inadvertent programs to the AT49BV160D(T) in the following ways: (a) V CC sense: if V CC is below 1.8V (typical), the program program cycles. (c) Program inhibit: V PP is less than V ILPP .

4.15Input Levels

CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V CCQ + 0.6V.

4.16Output Levels

For the AT49BV160D(T), output high levels (V OH ) are equal to V CCQ - 0.1V (not V CC ). For 2.65V -3.6V output levels, V CCQ must be tied to V CC .

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5.Word Program Flowchart

6.Word Program Procedure

Bus Operation Command Comments Write

Program Setup Data = 40

Addr = Any Address Write

Data

Data = Data to program Addr = Location to program Read

None

Status register data: Toggle CE or

OE to update status register Idle

None

Check SR7

1 = WSM Ready 0 = WSM Busy

Repeat for subsequent Word Program operations.

Full status register check can be done after each program, or after a sequence of program operations.

Write FF after the last operation to set to the Read state.

7.Full Status Check Flowchart

8.Full Status Check Procedure

Bus Operation

Command Comments Idle

None Check SR3: 1 = V PP Error

Idle

None

Check SR4:

1 = Data Program Error Idle None

Check SR1:

1 = Sector locked; operation aborted

SR3 MUST be cleared before the Write State Machine allows further program attempts.

If an error is detected, clear the status register before continuing operations – only the Clear Status Register command clears the status register error bits.

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9.Program Suspend/Resume

Flowchart

10.Program Suspend/Resume

Procedure

Bus Operation Command Comments Write

Program Suspend Data = B0

Addr = Any Address Write

Read Status

Data = 70

Addr = Any address

Read None

Status register data: Toggle CE or

OE to update status register Addr = Any address Idle None

Check SR7

1 = WSM Ready 0 = WSM Busy

Idle

None

Check SR2

1 = Program suspended 0 = Program completed Write

Read Array Data = FF

Addr = Any address

Read

None Read data from any word in the memory

Write

Program Resume

Data = D0

Addr = Any address

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11.Sector Erase Flowchart

12.Sector Erase Procedure

Bus Operation

Command Comments Write

Sector Erase Setup Data = 20

Addr = Any Address

Write

Erase Confirm Data = D0

Addr = Sector to be erased (SA)Read

None

Status register data: Toggle CE or

OE to update status register data Idle None

Check SR7

1 = WSM Ready 0 = WSM Busy

Repeat for subsequent sector erasures.

Full status register check can be done after each sector erase, or after a sequence of sector erasures.

Write FF after the last operation to enter read mode.

13.Full Erase Status Check Flowchart

14.Full Erase Status Check Procedure

Bus Operation

Command Comments Idle

None

Check SR3:

1 = V PP Range Error

Idle None

Check SR4, SR5:

Both 1 = Command Sequence Error

Idle None

Check SR5:

1 = Sector Erase Error Idle None

Check SR1:

1 = Attempted erase of locked sector; erase aborted.

SR1, SR3 must be cleared before the Write State Machine allows further erase attempts.

Only the Clear Status Register command clears SR1, SR3, SR4, SR5.

If an error is detected, clear the status register before attempting an erase retry or other error recovery.

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15.Erase Suspend/Resume Flowchart

16.Erase Suspend/Resume Procedure

Bus Operation

Command Comments Write Erase Suspend Data = B0

Addr = Any address Write

Read Status

Data = 70

Addr = Any address

Read

None

Status register data: Toggle CE or

OE to update status register Addr = Any address Idle

None

Check SR7

1 = WSM Ready 0 = WSM Busy Idle

None Check SR6

1 = Erase suspended 0 = Erase completed Write Read or Program Data = FF or 40Addr = Any address

Read or Write None Read or program data from/to sector other than the one being erased

Write

Program Resume

Data = D0

Addr = Any address

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17.Protection Register Programming

Flowchart

18.Protection Register Programming

Procedure

Bus Operation

Command Comments Write Program PR Setup Data = C0

Addr = Any Address Write

Protection Program Data = Data to Program Addr = Location to Program Read

None

Status register data: Toggle CE or

OE to update status register data Idle None

Check SR7

1 = WSM Ready 0 = WSM Busy

Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error.

Repeat for subsequent programming operations.

Full status register check can be done after each program, or after a sequence of program operations.

Write FF after the last operation to return to the Read mode.

19.

Full Status Check Flowchart

20.Full Status Check Procedure

Bus Operation

Command Comments

Idle None Check SR1, SR3, SR4: 0,1,1 = V PP Range Error Idle

None

Check SR1, SR3, SR4: 0,0,1 = Programming Error Idle None

Check SR1, SR3, SR4:

1, 0,1 = Sector locked; operation aborted

SR3 must be cleared before the Write State Machine allows further program attempts.

Only the Clear Status Register command clears SR1, SR3, SR4.

If an error is detected, clear the status register before attempting a program retry or other error recovery.

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Notes:

1.The DA TA FORMA T shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS

FORMA T shown for each bus cycle is as follows: A7 - A0 (Hex). Address A19 through A8 are don’t care.

2.SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 and 18

for details).

3.This fast programming option enables the user to program two words in parallel only when V PP = 9.5V . The addresses,

Addr0 and Addr1, of the two words, D IN0 and D IN1, must only differ in address A0. This command should be used during manufacturing purposes only.

4.During the second bus cycle, the manufacturer code is read from address 00000H, the device code is read from address

00001H, and the data in the protection register is read from addresses 00081H - 00088H.5.The status register bits are output on I/O7 - I/O0.

6.Any addresses within the user programmable protection register region. Address locations are shown on “Protection Regis-ter Addressing Table” on page 16.

7.If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed.

https://www.wendangku.net/doc/9716734511.html,mand Definition Table

Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Addr Data Addr

Data

Addr

Data

Read

1XX FF Sector Erase/Confirm 2XX 20SA (2)D0Word Program 2XX 40/10Addr D IN Dual-word Program (3)3XX E0Addr0

D IN0

Addr1

D IN1

Erase/Program Suspend 1XX B0Erase/Program Resume 1XX D0Product ID Entry (4)1XX 90Sector Softlock 2XX 60SA (2)01Sector Hardlock 2XX 60SA (2)2F Sector Unlock 2XX 60SA (2)D0Read Status Register 2XX 70XX

D OUT (5)

Clear Status Register 1XX 50Program Protection Register 2XX C0Addr (6)D IN Lock Protection Register – Sector B 2XX C080FFFD Status of Sector B Protection 2XX 9080

D OUT (7)

CFI Query 1

22.Absolute Maximum Ratings*

T emperature under Bias ................................-55°C to +125°C *NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage T emperature.....................................-65°C to +150°C All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V All Output Voltages

with Respect to Ground...........................-0.6V to V CCQ + 0.6V Voltage on V PP

with Respect to Ground...................................-0.6V to +10.0V

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Note:

All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.

23.Protection Register Addressing Table

Word Use Sector A7A6A5A4A3A2A1A00Factory A 100000011Factory A 100000102Factory A 100000113Factory A 100001004User B 100001015User B 100001106User B 100001117User

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24.AT49BV160D – Sector Address Table

Sector Size (Bytes/Words)

Address Range (A19 - A0)

SA08K/4K 00000 - 00FFF SA18K/4K 01000 - 01FFF SA28K/4K 02000 - 02FFF SA38K/4K 03000 - 03FFF SA48K/4K 04000 - 04FFF SA58K/4K 05000 - 05FFF SA68K/4K 06000 - 06FFF SA78K/4K 07000 - 07FFF SA864K/32K 08000 - 0FFFF SA964K/32K 10000 - 17FFF SA1064K/32K 18000 - 1FFFF SA1164K/32K 20000 - 27FFF SA1264K/32K 28000 - 2FFFF SA1364K/32K 30000 - 37FFF SA1464K/32K 38000 - 3FFFF SA1564K/32K 40000 - 47FFF SA1664K/32K 48000 - 4FFFF SA1764K/32K 50000 - 57FFF SA1864K/32K 58000 - 5FFFF SA1964K/32K 60000 - 67FFF SA2064K/32K 68000 - 6FFFF SA2164K/32K 70000 - 77FFF SA2264K/32K 78000 - 7FFFF SA2364K/32K 80000 - 87FFF SA2464K/32K 88000 - 8FFFF SA2564K/32K 90000 - 97FFF SA2664K/32K 98000 - 9FFFF SA2764K/32K A0000 - A7FFF SA2864K/32K A8000 - AFFFF SA2964K/32K B0000 - B7FFF SA3064K/32K B8000 - BFFFF SA3164K/32K C0000 - C7FFF SA3264K/32K C8000 - CFFFF SA3364K/32K D0000 - D7FFF SA3464K/32K D8000 - DFFFF SA3564K/32K E0000 - E7FFF SA3664K/32K E8000 - EFFFF SA3764K/32K F0000 - F7FFF SA38

64K/32K

F8000 - FFFFF

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25.AT49BV160DT – Sector Address Table

Sector Size (Bytes/Words)

x16

Address Range (A19 - A0)

SA064K/32K 00000 - 07FFF SA164K/32K 08000 - 0FFFF SA264K/32K 10000 - 17FFF SA364K/32K 18000 - 1FFFF SA464K/32K 20000 - 27FFF SA564K/32K 28000 - 2FFFF SA664K/32K 30000 - 37FFF SA764K/32K 38000 - 3FFFF SA864K/32K 40000 - 47FFF SA964K/32K 48000 - 4FFFF SA1064K/32K 50000 - 57FFF SA1164K/32K 58000 - 5FFFF SA1264K/32K 60000 - 67FFF SA1364K/32K 68000 - 6FFFF SA1464K/32K 70000 - 77FFF SA1564K/32K 78000 - 7FFFF SA1664K/32K 80000 - 87FFF SA1764K/32K 88000 - 8FFFF SA1864K/32K 90000 - 97FFF SA1964K/32K 98000 - 9FFFF SA2064K/32K A0000 - A7FFF SA2164K/32K A8000 - AFFFF SA2264K/32K B0000 - B7FFF SA2364K/32K B8000 - BFFFF SA2464K/32K C0000 - C7FFF SA2564K/32K C8000 - CFFFF SA2664K/32K D0000 - D7FFF SA2764K/32K D8000 - DFFFF SA2864K/32K E0000 - E7FFF SA2964K/32K E8000 - EFFFF SA3064K/32K F0000 - F7FFF SA318K/4K F8000 - F8FFF SA328K/4K F9000 - F9FFF SA338K/4K FA000 - FAFFF SA348K/4K FB000 - FBFFF SA358K/4K FC000 - FCFFF SA368K/4K FD000 - FDFFF SA378K/4K FE000 - FEFFF SA38

8K/4K

FF000 - FFFFF

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Notes:

1.The VPP pin can be tied to V CC for faster program operations, VPP pin can be set 9.5V ± 0.5V .

2.X can be V IL or V IH .

3.Refer to “Program Cycle Waveforms” on page 23.

4.V IHPP (min) = 1.65V .

5.V ILPP (max) = 0.4V .

Manufacturer Code: 001FH, Device Code: 90C3H – A T49BV160D; 90C2H – A T49BV160DT.

Note:

1.In the erase mode, I CC is 25 mA.

26.DC and AC Operating Range

AT49BV160D(T)-70

Operating T emperature (Case)Ind.

-40°C - 85°C V CC Power Supply

2.65V to

3.6V

27.Operating Modes

Mode CE OE WE RESET V PP (1)Ai I/O Read

V IL V IL V IH V IH X (2)Ai D OUT Program/Erase (3)

V IL V IH V IL V IH V IHPP (4)

Ai D IN Standby/Program Inhibit

V IH X (2)X V IH X X

High-Z

Program Inhibit

X V IH V IH X X V IL X V IH X X

X X V IH V ILPP (5)

Output Disable X V IH X V IH X High-Z Reset

V IL X

High-Z

Product Identification Software V IH

A0 = V IL , A1 - A19 = V IL Manufacturer Code (6)

A0 = V IH , A1 - A19 = V IL

Device Code (6)

28.DC Characteristics

Symbol Parameter Condition Min

Typ

Max Units I LI Input Load Current V IN = 0V to V CC 2μA I LO Output Leakage Current V I/O = 0V to V CC

2μA I SB V CC Standby Current CMOS CE = V CC - 0.3V to V CC 1525μA I CC (1)V CC Active Read Current f = 5 MHz; I OUT = 0 mA

15mA I CC1V CC Programming Current 25mA I PP1V PP Input Load Current 10μA V IL Input Low Voltage 0.6

V V IH Input High Voltage V CCQ - 0.6

V V OL Output Low Voltage I OL = 2.1 mA 0.45

V V OH Output High Voltage

I OH = -100 μA

V CCQ - 0.1V

3591C–FLASH–6/06

AT49BV160D(T)

29.Input Test Waveforms and Measurement Level

t R , t F < 5 ns

30.Output Test Load

Note:

This parameter is characterized and is not 100% tested.

31.Pin Capacitance

f = 1 MHz, T = 25°C (1)

Symbol

Typ Max Units Conditions C IN 46pF V IN = 0V C OUT 8

V OUT = 0V