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MX29LV320ABTI-70G中文资料

MX29LV320AT/B

32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE

3V ONLY FLASH MEMORY FEATURES

GENERAL FEATURES

?4,194,304 x 8 / 2,097,152 x 16 switchable

?Sector Structure

- 8K-Byte x 8 and 64K-Byte x 63

?Extra 64K-Byte sector for security

- Features factory locked and identifiable, and cus-tomer lockable

?Twenty-Four Sector Groups

- Provides sector group protect function to prevent pro-gram or erase operation in the protected sector group - Provides chip unprotect function to allow code chang-ing

- Provides temporary sector group unprotect function for code changing in previously protected sector groups ?Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program opera-tions

?Latch-up protected to 250mA from -1V to Vcc + 1V ?Low Vcc write inhibit is equal to or less than 1.4V ?Compatible with JEDEC standard

- Pinout and software compatible to single power sup-ply Flash

?2nd generation of 3V/32M Flash product

- Fully compatible with MX29LV320T/B device PERFORMANCE

?High Performance

- Fast access time: 70/90ns

- Fast program time: 7us/word typical utilizing acceler-ate function

- Fast erase time: 0.9s/sector, 35s/chip (typical)?Low Power Consumption

- Low active read current: 10mA (typical) at 5MHz

- Low standby current: 200nA (typical)

?Minimum 100,000 erase/program cycle

?10 years data retention

SOFTWARE FEATURES

?Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data from or program data to another sector which is not being erased

?Status Reply

- Data polling & Toggle bits provide detection of pro-gram and erase operation completion

?Support Common Flash Interface (CFI) HARDWARE FEATURES

?Ready/Busy (RY/BY) Output

- Provides a hardware method of detecting program and erase operation completion

?Hardware Reset (RESET) Input

- Provides a hardware method to reset the internal state machine to read mode

?WP/ACC input pin

- Provides accelerated program capability

P ACKAGE

?48-Pin TSOP

?48-Ball CSP

GENERAL DESCRIPTION

The MX29L V320A T/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29L V320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29L V320A T/B offers access time as fast as 70ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29L V320A T/B has separate chip enable (CE) and output enable (OE) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29L V320AT/B uses a command register to manage this functionality.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.

MX29LV320AT/B

AUTOMATIC PROGRAMMING

The MX29LV320A T/B is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV320A T/B is less than 36 seconds.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 un-lock write cycle and A0H) and a program command (pro-gram data and address). The device automatically times the programming pulse width, provides the program veri-fication, and counts the number of sequences. A status bit similar to DAT A polling and a status bit toggling be-tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 35 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electri-cal erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE

The MX29LV320AT/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand-ard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu-tive read cycles provides feedback to the user as to the status of the programming operation.

Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, relia-bility, and cost effectiveness. The MX29L V320AT/B elec-trically erases all bits simultaneously using Fowler-Nord-heim tunneling. The bytes/words are programmed by using the EPROM programming mechanism of hot elec-tron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set.

The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.

MX29LV320AT/B

Table 1.a: MX29LV320AT SECTOR GROUP ARCHITECTURE

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12(Kbytes/Kwords)Address Range Address Range

1SA0000000xxx64/32000000h-00FFFFh000000h-07FFFh

1SA1000001xxx64/32010000h-01FFFFh008000h-0FFFFh

1SA2000010xxx64/32020000h-02FFFFh010000h-17FFFh

1SA3000011xxx64/32030000h-03FFFFh018000h-01FFFFh

2SA4000100xxx64/32040000h-04FFFFh020000h-027FFFh

2SA5000101xxx64/32050000h-05FFFFh028000h-02FFFFh

2SA6000110xxx64/32060000h-06FFFFh030000h-037FFFh

2SA7000111xxx64/32070000h-07FFFFh038000h-03FFFFh

3SA8001000xxx64/32080000h-08FFFFh040000h-047FFFh

3SA9001001xxx64/32090000h-09FFFFh048000h-04FFFFh

3SA10001010xxx64/320A0000h-0AFFFFh050000h-057FFFh

3SA11001011xxx64/320B0000h-0BFFFFh058000h-05FFFFh

4SA12001100xxx64/320C0000h-0CFFFFh060000h-067FFFh

4SA13001101xxx64/320D0000h-0DFFFFh068000h-06FFFFh

4SA14001110xxx64/320E0000h-0EFFFFh070000h-077FFFh

4SA15001111xxx64/320F0000h-0FFFFFh078000h-07FFFFh

5SA16010000xxx64/32100000h-10FFFFh080000h-087FFFh

5SA17010001xxx64/32110000h-11FFFFh088000h-08FFFFh

5SA18010010xxx64/32120000h-12FFFFh090000h-097FFFh

5SA19010011xxx64/32130000h-13FFFFh098000h-09FFFFh

6SA20010100xxx64/32140000h-14FFFFh0A0000h-0A7FFFh

6SA21010101xxx64/32150000h-15FFFFh0A8000h-0AFFFFh

6SA22010110xxx64/32160000h-16FFFFh0B0000h-0B7FFFh

6SA23010111xxx64/32170000h-17FFFFh0B8000h-0BFFFFh

7SA24011000xxx64/32180000h-18FFFFh0C0000h-0C7FFFh

7SA25011001xxx64/32190000h-19FFFFh0C8000h-0CFFFFh

7SA26011010xxx64/321A0000h-1AFFFFh0D0000h-0D7FFFh

7SA27011011xxx64/321B0000h-1BFFFFh0D8000h-0DFFFFh

8SA28011100xxx64/321C0000h-1CFFFFh0E0000h-0E7FFFh

8SA29011101xxx64/321D0000h-1DFFFFh0E8000h-0EFFFFh

8SA30011110xxx64/321E0000h-1EFFFFh0F0000h-0F7FFFh

8SA31011111xxx64/321F0000h-1FFFFFh0F8000h-0FFFFFh

9SA32100000xxx64/32200000h-20FFFFh100000h-107FFFh

9SA33100001xxx64/32210000h-21FFFFh108000h-10FFFFh

9SA34100010xxx64/32220000h-22FFFFh110000h-117FFFh

9SA35100011xxx64/32230000h-23FFFFh118000h-11FFFFh

10SA36100100xxx64/32240000h-24FFFFh120000h-127FFFh

10SA37100101xxx64/32250000h-25FFFFh128000h-12FFFFh

10SA38100110xxx64/32260000h-26FFFFh130000h-137FFFh

10SA39100111xxx64/32270000h-27FFFFh138000h-13FFFFh

MX29LV320AT/B

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12(Kbytes/Kwords)Address Range Address Range

11SA40101000xxx64/32280000h-28FFFFh140000h-147FFFh

11SA41101001xxx64/32290000h-29FFFFh148000h-14FFFFh

11SA42101010xxx64/322A0000h-2AFFFFh150000h-157FFFh

11SA43101011xxx64/322B0000h-2BFFFFh158000h-15FFFFh

12SA44101100xxx64/322C0000h-2CFFFFh160000h-147FFFh

12SA45101101xxx64/322D0000h-2DFFFFh168000h-14FFFFh

12SA46101110xxx64/322E0000h-2EFFFFh170000h-177FFFh

12SA47101111xxx64/322F0000h-2FFFFFh178000h-17FFFFh

13SA48110000xxx64/32300000h-30FFFFh180000h-187FFFh

13SA49110001xxx64/32310000h-31FFFFh188000h-18FFFFh

13SA50110010xxx64/32320000h-32FFFFh190000h-197FFFh

13SA51110011xxx64/32330000h-33FFFFh198000h-19FFFFh

14SA52110100xxx64/32340000h-34FFFFh1A0000h-1A7FFFh

14SA53110101xxx64/32350000h-35FFFFh1A8000h-1AFFFFh

14SA54110110xxx64/32360000h-36FFFFh1B0000h-1B7FFFh

14SA55110111xxx64/32370000h-37FFFFh1B8000h-1BFFFFh

15SA56111000xxx64/32380000h-38FFFFh1C0000h-1C7FFFh

15SA57111001xxx64/32390000h-39FFFFh1C8000h-1CFFFFh

15SA58111010xxx64/323A0000h-3AFFFFh1D0000h-1D7FFFh

15SA59111011xxx64/323B0000h-3BFFFFh1D8000h-1DFFFFh

16SA60111100xxx64/323C0000h-3CFFFFh1E0000h-1E7FFFh

16SA61111101xxx64/323D0000h-3DFFFFh1E8000h-1EFFFFh

16SA62111110xxx64/323E0000h-3EFFFFh1F0000h-1F7FFFh

17SA631111110008/43F0000h-3F1FFFh1F8000h-1F8FFFh

18SA641111110018/43F2000h-3F3FFFh1F9000h-1F9FFFh

19SA651111110108/43F4000h-3F5FFFh1FA000h-1FAFFFh

20SA661111110118/43F6000h-3F7FFFh1FB000h-1FBFFFh

21SA671111111008/43F8000h-3F9FFFh1FC000h-1FCFFFh

22SA681111111018/43FA000h-3FBFFFh1FD000h-1FDFFFh

23SA691111111108/43FC000h-3FDFFFh1FE000h-1FEFFFh

24SA701111111118/43FE000h-3FFFFFh1FF000h-1FFFFFh Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)

Top Boot Security Sector Addresses

Sector Address Sector Size(x8)(x16)

A20~A12(Kbytes/Kwords)Address Range Address Range

111111xxx64/323F0000h-3FFFFFh1F8000h-1FFFFFh

MX29LV320AT/B

Table 1.b: MX29LV320AB SECTOR GROUP ARCHITECTURE

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12(Kbytes/Kwords)Address Range Address Range

1SA00000000008/4000000h-001FFFh000000h-000FFFh

2SA10000000018/4002000h-003FFFh001000h-001FFFh

3SA20000000108/4004000h-005FFFh002000h-002FFFh

4SA30000000118/4006000h-007FFFh003000h-003FFFh

5SA40000001008/4008000h-009FFFh004000h-004FFFh

6SA50000001018/400A000h-00BFFFh005000h-005FFFh

7SA60000001108/400C000h-00DFFFh006000h-006FFFh

8SA70000001118/400E000h-00FFFFh007000h-007FFFh

9SA8000001xxx64/32010000h-01FFFFh008000h-00FFFFh

9SA9000010xxx64/32020000h-02FFFFh010000h-017FFFh

9SA10000011xxx64/32030000h-03FFFFh018000h-01FFFFh

10SA11000100xxx64/32040000h-04FFFFh020000h-027FFFh

10SA12000101xxx64/32050000h-05FFFFh028000h-02FFFFh

10SA13000110xxx64/32060000h-06FFFFh030000h-037FFFh

10SA14000111xxx64/32070000h-07FFFFh038000h-03FFFFh

11SA15001000xxx64/32080000h-08FFFFh040000h-047FFFh

11SA16001001xxx64/32090000h-09FFFFh048000h-04FFFFh

11SA17001010xxx64/320A0000h-0AFFFFh050000h-057FFFh

11SA18001011xxx64/320B0000h-0BFFFFh058000h-05FFFFh

12SA19001100xxx64/320C0000h-0CFFFFh060000h-067FFFh

12SA20001101xxx64/320D0000h-0DFFFFh068000h-06FFFFh

12SA21001110xxx64/320E0000h-0EFFFFh070000h-077FFFh

12SA22001111xxx64/320F0000h-0FFFFFh078000h-07FFFFh

13SA23010000xxx64/32100000h-10FFFFh080000h-087FFFh

13SA24010001xxx64/32110000h-11FFFFh088000h-08FFFFh

13SA25010010xxx64/32120000h-12FFFFh090000h-097FFFh

13SA26010011xxx64/32130000h-13FFFFh098000h-09FFFFh

14SA27010100xxx64/32140000h-14FFFFh0A0000h-0A7FFFh

14SA28010101xxx64/32150000h-15FFFFh0A8000h-0AFFFFh

14SA29010110xxx64/32160000h-16FFFFh0B0000h-0B7FFFh

14SA30010111xxx64/32170000h-17FFFFh0B8000h-0BFFFFh

15SA31011000xxx64/32180000h-18FFFFh0C0000h-0C7FFFh

15SA32011001xxx64/32190000h-19FFFFh0C8000h-0CFFFFh

15SA33011010xxx64/321A0000h-1AFFFFh0D0000h-0D7FFFh

15SA34011011xxx64/321B0000h-1BFFFFh0D8000h-0DFFFFh

16SA35011100xxx64/321C0000h-1CFFFFh0E0000h-0E7FFFh

16SA36011101xxx64/321D0000h-1DFFFFh0E8000h-0EFFFFh

16SA37011110xxx64/321E0000h-1EFFFFh0F0000h-0F7FFFh

16SA38011111xxx64/321F0000h-1FFFFFh0F8000h-0FFFFFh

MX29LV320AT/B

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12(Kbytes/Kwords)Address Range Address Range

17SA39100000xxx64/32200000h-20FFFFh100000h-107FFFh

17SA40100001xxx64/32210000h-21FFFFh108000h-10FFFFh

17SA41100010xxx64/32220000h-22FFFFh110000h-117FFFh

17SA42100011xxx64/32230000h-23FFFFh118000h-11FFFFh

18SA43100100xxx64/32240000h-24FFFFh120000h-127FFFh

18SA44100101xxx64/32250000h-25FFFFh128000h-12FFFFh

18SA45100110xxx64/32260000h-26FFFFh130000h-137FFFh

18SA46100111xxx64/32270000h-27FFFFh138000h-13FFFFh

19SA47101000xxx64/32280000h-28FFFFh140000h-147FFFh

19SA48101001xxx64/32290000h-29FFFFh148000h-14FFFFh

19SA49101010xxx64/322A0000h-2AFFFFh150000h-157FFFh

19SA50101011xxx64/322B0000h-2BFFFFh158000h-15FFFFh

20SA51101100xxx64/322C0000h-2CFFFFh160000h-167FFFh

20SA52101101xxx64/322D0000h-2DFFFFh168000h-16FFFFh

20SA53101110xxx64/322E0000h-2EFFFFh170000h-177FFFh

20SA54101111xxx64/322F0000h-2FFFFFh178000h-17FFFFh

21SA55110000xxx64/32300000h-30FFFFh180000h-187FFFh

21SA56110001xxx64/32310000h-31FFFFh188000h-18FFFFh

21SA57110010xxx64/32320000h-32FFFFh190000h-197FFFh

21SA58110011xxx64/32330000h-33FFFFh198000h-19FFFFh

22SA59110100xxx64/32340000h-34FFFFh1A0000h-1A7FFFh

22SA60110101xxx64/32350000h-35FFFFh1A8000h-1AFFFFh

22SA61110110xxx64/32360000h-36FFFFh1B0000h-1B7FFFh

22SA62110111xxx64/32370000h-37FFFFh1B8000h-1BFFFFh

23SA63111000xxx64/32380000h-38FFFFh1C0000h-1C7FFFh

23SA64111001xxx64/32390000h-39FFFFh1C8000h-1CFFFFh

23SA65111010xxx64/323A0000h-3AFFFFh1D0000h-1D7FFFh

23SA66111011xxx64/323B0000h-3BFFFFh1D8000h-1DFFFFh

24SA67111100xxx64/323C0000h-3CFFFFh1E0000h-1E7FFFh

24SA68111101xxx64/323D0000h-3DFFFFh1E8000h-1EFFFFh

24SA69111110xxx64/323E0000h-3EFFFFh1F0000h-1F7FFFh

24SA70111111xxx64/323F0000h-3FFFFFh1F8000h-1FFFFFh Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)

Bottom Boot Security Sector Addresses

Sector Address Sector Size (x8) (x16)

A20~A12(Kbytes/Kwords)Address Range Address Range

111111xxx64/32000000h-00FFFFh00000h-07FFFh

MX29LV320AT/B

Operation CE OE WE RESET WP/ACC Addresses Q0~Q7

Q8 ~ Q15(Note 2)Byte=VIH Byte=VIL Read L L H H L/H A IN D OUT D OUT Q8-A14=High-Z Write (Note 1)L H L H Note 3A IN D IN D IN Q15=A-1

Accelerate L

V HH

A IN

D IN D IN

Program Standby VCC ±X X

VCC ±H

High-Z

0.3V 0.3V Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H X

High-Z

High-Z High-Z Sector Group L

L V ID

L/H

Sector Addresses,D IN , D OUT

Protect (Note 2)A6=L, A1=H, A0=L

Chip Unprotect L

V ID

Note 3

Sector Addresses,D IN , D OUT X

(Note 2)

A6=H, A1=H, A0=L

Temporary Sector X

V ID

Note 3

A IN

D IN

High-Z

Group Unprotect

Legend:

L=Logic LOW=V IL , H=Logic High=V IH , V ID =12.0±0.5V, V HH =11.5-12.5V, X=Don't Care, A IN =Address IN, D IN =Data IN,D OUT =Data OUT

Notes:

1. When the WP/ACC pin is at V HH , the device enters the accelerated program mode. See "Accelerated Program Operations" for more information.

2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotection" section.

3.If WP/ACC=V IL , the two outermost boot sectors remain protected. If WP/ACC=V IH , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP/ACC=V HH , all sectors will be unprotected.

4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm.

5.Address are A20:A0 in word mode (BYTE=V IH ), A20:A-1 in byte mode (BYTE=V IL ).

Table 2. BUS OPERATION--1

MX29LV320AT/B

BUS OPERATION--2

A20A11A9A8A6A5

Operation CE OE WE to to to to A1A0Q0-Q7Q8-Q15

A12A10A7A2

X L X L L C2H X Read Silicon ID L L H X X V

Manufacturer Code

X L X L H A7H22h(word) Read Silicon ID L L H X X V

MX29L V320A T X (byte)

X L X L H A8H22h(word) Read Silicon ID L L H X X V

MX29L V320AB X (byte) Sector Protect L L H SA X V

X L X H L01h(1),X

Verification or 00h

X L X H H99h(2),X Security Sector L L H X X V

Indicater or 19h

Bit (Q7)

Notes:

1.Code=00h means unprotected, or code=01h protected.

2.Code=99 means factory locked, or code=19h not factory locked.

MX29LV320AT/B

REQUIREMENTS FOR READING ARRAY DATA

T o read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES

T o program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH.

An erase operation can erase one sector, multiple sectors , or the entire device. T able 1 indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. Writing specific address and data commands or sequences into the command register initiates device operations. Table 3 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.ACCELERATED PROGRAM OPERATION

The device offers accelerated program operations through

the WP/ACC function. If the system asserts V

on ACC

pin, the device will provide the fast programming time to

user. This function is primarily intended to allow faster

manufacturing throughput during production. Removing

from the WP/ACC pin returns the device to normal

operation. Note that the WP/ACC pin must not be at V

HH for operations other than accelerated programming, or

device damage may result.

STANDBY MODE

MX29L V320A T/B can be set into Standby mode with two

different approaches. One is using both CE and RESET

pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ±0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE and RESET are held at VIH, but not within the range of VCC ±0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc ac-tive current (ICC2) is required even CE = "H" until the operation is completed. The device can be read with stan-dard access time (tCE) from either of these standby modes.

When using only RESET, a CMOS standby mode is

achieved with RESET input held at Vss ± 0.3V, Under

this condition the current is consumed less than 1uA

(typ.). Once the RESET pin is taken high, the device is

back to active without recovery delay.

In the standby mode the outputs are in the high imped-

ance state, independent of the OE input.

MX29LV320AT/B is capable to provide the Automatic

Standby Mode to restrain power consumption during read-

out of data. This mode can be used effectively with an

application requested low power consumption such as

handy terminals.

To active this mode, MX29LV320AT/B automatically

switch themselves to low power mode when

MX29L V320A T/B addresses remain stable during access

time of tACC+30ns. It is not necessary to control CE,

WE, and OE on the mode. Under the mode, the current consumed is typically 0.2uA (CMOS level).

MX29LV320AT/B

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.

RESET OPERATION

The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity

Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater.

The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory.

If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram. SECTOR GROUP PROTECT OPERATION

The MX29LV320A T/B features hardware sector group protection. This feature will disable both program and erase operations for these sector group protected. Sec-tor protection can be implemented via two methods.The primary method requires VID on the RESET only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Figure 13 for timing diagram and Figure 14 illustrates the algorithm for the sector group protection operation.

The alternate method intended only for programming equipment, must force VID on address pin A9 and con-trol pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL(see Table 2). Programming of the protection circuitry begins on the falling edge of the WE pulse and is termi-nated on the rising edge. Contact MXIC for details.

T o verify programming of the protection circuitry, the pro-gramming equipment must force V

on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1= VIL are reserved to read manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT OPERATION

The MX29LV320A T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

The primary method requires VID on the RESET only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Figure 13 for timing diagram and Figure 14 illustrates the algorithm for the sector group protection operation.

MX29LV320AT/B

It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command.Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

TEMPORARY SECTOR GROUP UNPROTECT OPERATION

This feature allows temporary unprotection of previously protected sector to change data in-system. The Tempo-rary Sector Unprotect mode is activated by setting the RESET pin to V ID (11.5V-12.5V). During this mode, for-merly protected sectors can be programmed or erased as un-protected sector. Once V ID is remove from the RESET pin, all the previously protected sectors are pro-tected again.

WRITE PROTECT (WP)

The write protect function provides a hardware method to protect boot sectors without using V ID .

If the system asserts VIL on the WP/ACC pin, the de-vice disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector/Sector Group Pro-tection and Chip Unprotection". The two outermost 8Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device.

If the system asserts VIH on the WP/ACC pin, the de-vice reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sec-tors depends on whether they were last protected or un-protected using the method described in "Sector/Sector Group Protection and Chip Unprotection".

Note that the WP/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

AUTOMATIC SELECT OPERATION

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design prac-tice.

MX29L V320AT/B provides hardware method to access the Automatic Select operation. This method requires V ID on A9 pin, VIL on CE, OE, A6, and A1 pins. When apply-ing VIL on A0 pin, the device will output MXIC's manu-facture code of C2H. When applying VIH on A0 pin, the device will output MX29LV320A T/B device code of 22A7h and 22A8h.

VERIFY SECTOR GROUP PROTECT STATUS OPERATION

MX29L V320AT/B provides hardware method for sector group protect status verify. This method requires V ID on A9 pin, VIH on WE and A1 pins, VIL on CE, OE, A6, and A0 pins, and sector address on A12 to A20 pins. When the identified sector is protected, the device will output 01H. When the identified sector is not protect, the device will output 00H.

SECURITY SECTOR FLASH MEMORY REGION

The Security Sector (Security Sector) feature provides a Flash memory region that enables permanent part iden-tification through an Electronic Serial Number (ESN). The Security Sector is 64 Kbytes (32 Kwords) in length, and uses a Security Sector Indicator Bit (Q7) to indicate whether or not the Security Sector is locked when shipped from the factory. This bit is per-manently set at the fac-tory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.

MXIC offers the device with the Security Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the fac-tory, and has the Security on Silicon Sector (Security Sector) Indicator Bit permanently set to a "1". The cus-tomer-lockable version is shipped with the unprotected,allowing customers to utilize the that sector in any man-

MX29LV320AT/B

ner they choose. The customer-lockable version has the Security on Silicon Sector (Security Sector) Indicator Bit permanently set to a "0". Thus, the Security Sector Indi-cator Bit prevents customer-lockable devices from be-ing used to replace devices that are factory locked.

The system accesses the Security Sector through a command sequence (see "Enter Security Sector/Exit Security Sector Command Sequence"). After the sys-tem has written the Enter Security Sector command se-quence, it may read the Security Sector by using the ad-dresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Security Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.

Factory Locked: Security Sector Programmed and Protected at the Factory

In a factory locked device, the Security Sector is pro-tected when the device is shipped from the factory. The Security Sector cannot be modified in any way. The de-vice is available preprogrammed with one of the follow-ing:

A random, secure ESN only.

Customer code through the Express Flash service. Both a random, secure ESN and customer code through the Express Flash service.

In devices that have an ESN, a Bottom Boot device will have the 16-byte (8-word) ESN in the lowest address-able memory area starting at 00000h and ending at 0000Fh (00007h). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte (4 Kword) boot sector starting at 3F0000h (1F8000h) and ending at 3F000Fh (1F8007h). Customer Lockable: Security Sector NOT Pro-grammed or Protected at the Factory

If the security feature is not required, the Security Sec-tor can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes (32 Kwords). The Security Sector can be read, programmed, and erased as often as required. The Se-curity Sector area can be protected using one of the following procedures:Write the three-cycle Enter Security Region command sequence, and then follow the in-system sector group protect algorithm as shown in Figure 14, except that RE-SET may be at either VIH or V

. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the Security Sector.

Write the three-cycle Enter Security Region command sequence, and then use the alternate method of sector protection described in the "Sector/Sector Block Protec-tion and Unprotection section.

Once the Security Sector is locked and verified, the sys-tem must write the Exit Security Sector Region com-mand sequence to return to reading and writing the re-mainder of the array.

The Security Sector protection must be used with cau-tion since, once protected, there is no procedure avail-able for unprotecting the Security Sector area and none of the bits in the Security Sector memory space can be modified in any way.

DATA PROTECTION

The MX29LV320A T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically re-sets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful comple-tion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down tran-sition or system noise.

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not ac-cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLKO.

MX29LV320AT/B

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on OE, CE or WE

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =

VIH or WE = VIH. T o initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

POWER-UP SEQUENCE

The MX29L V320A T/B powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

POWER-UP WRITE INHIBIT

If WE=CE=VIL and OE=VIH during power up, the device

does not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the

read mode on power-up.

POWER SUPPL Y DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND.

SOFTWARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. T able 3 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

All addresses are latched on the falling edge of WE or

CE, whichever happens later. All data are latched on ris-

ing edge of WE or CE, whichever happens first.

MX29LV320AT/B

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read(Note 5)1RA RD

Reset(Note 4)1XXX F0

Automatic Select(Note 5)

Manufacturer ID Word4555AA2AA5555590X00C2H

Byte4AAA AA55555AAA90X00C2H

Device ID Word4555AA2AA5555590X01ID

Byte4AAA AA55555AAA90X02

Security Sector Factory Word4555AA2AA5555590X0399/19

Protect Verify (Note 6)Byte4AAA AA55555AAA90X06

Sector Protect Verify Word4555AA2AA5555590(SA)X0200/01

(Note 7)Byte4AAA AA55555AAA90(SA)X04

Enter Security Sector Word3555AA2AA5555588

Region Byte3AAA AA55555AAA88

Exit Security Sector Word4555AA2AA5555590XXX00

Byte4AAA AA55555AAA90XXX00

Program Word4555AA2AA55555A0PA PD

Byte4AAA AA55555AAA A0PA PD

Chip Erase Word6555AA2AA5555580555AA2AA5555510 Byte6AAA AA55555AAA80AAA AA55555AAA10 Sector Erase Word6555AA2AA5555580555AA2AA55SA30 Byte6AAA AA55555AAA80AAA AA55555SA30 CFI Query (Note 8)Word15598

Byte1AA98

Erase Suspend(Note 9)1SA B0

Erase Resume(Note 10)1SA30

TABLE 3. MX29LV320AT/B COMMAND DEFINITIONS

Legend:

X=Don't care

RA=Address of the memory location to be read.

RD=Data read from location RA during read operation.

P A=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.PD=Data to be programmed at location P A. Data is latched on the rising edge of WE or CE pulse.

SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector.

ID=22A7h(T op), 22A8h(Bottom)

Notes:

1.See Table 1 for descriptions of bus operations.

2.All values are in hexadecimal.

3.Except when reading array or Automatic Select data, all bus cycles are write operation.

4.The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes

high.

5.The fourth cycle of the Automatic Select command sequence is a read cycle.

6.The data is 99h for factory locked and 19h for not factory locked.

7.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third cycle of the

command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to verify sectors 32~70 for Top Boot device.

https://www.wendangku.net/doc/9617068337.html,mand is valid when device is ready to read array data or when device is in Automatic Select mode.

9.The system may read and program functions in non-erasing sectors, or enter the Automatic Select mode, when in the erase

Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

10.The Erase Resume command is valid only during the Erase Suspend mode.

MX29LV320AT/B

READING ARRAY DATA

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys-tem can read array data using the standard read tim-ings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-en-able the device for reading array data if Q5 goes high during an active program or erase operation, or while in the Automatic Select mode. See the "Reset Command" section, next.

RESET COMMAND

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command.

The reset command may be written between the se-quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the se-quence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se-quence cycles in an Automatic Select command sequence. Once in the Automatic Select mode, the reset command must be written to return to reading array data (also applies to Automatic Select during Erase Suspend). If Q5 goes high during a program or erase operation, writing the reset command returns the device to read-ing array data (also applies during Erase Suspend).AUTOMATIC SELECT COMMAND SEQUENCE The Automatic Select command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is pro-tected. T able 2 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for EPROM programmers and requires V ID on address bit A9.

The Automatic Select command sequence is initiated by writ-ing two unlock cycles, followed by the Automatic Select command. The device then enters the Automatic Select mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or xx02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to T able 1 for valid sector addresses.

The system must write the reset command to exit the Automatic Select mode and return to reading array data. ENTER SECURITY SECTOR & EXIT SECURITY SECTOR COMMAND SEQUENCE

The Security Sector provides a secured area which con-tains a random, sixteen-byte electronic serial number.(ESN)

The system can access the Security Sector area by is-suing the three-cycle "Enter Security Sector command sequence. The device continues to access the security section area until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security Sector command sequence returns the device to normal operation.

BYTE/WORD PROGRAM COMMAND SEQUENCE The device programs one byte/word of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and

MX29LV320AT/B

verifies the programmed cell margin. Table 3 shows the address and data requirements for the byte/word program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY . See "Write Operation Status" for information on these status bits.

Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte/Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may cause the device to set Q5 to "1" ,” or cause the Data Polling algorithm to indicate the operation was successful.

Pins

A0A1Q7Q6Q5Q4Q3Q2Q1Q0Code (Hex)Manufacture code

VIL

11000010C2H Device code for MX29LV320AT VIH VIL 1010011122A7H Device code for MX29LV320AB

VIH VIL

22A8H

TABLE 4. SILICON ID CODE

AUTOMATIC CHIP/SECTOR ERASE COMMAND The device does not require the system to preprogram prior to erase. The Automatic Erase algorithm automati-cally preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 3 shows the address and data requirements for the chip erase command sequence.Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hard-ware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should

However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".

SETUP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H, or the sector erase command 30H.

The MX29LV320A T/B contains a Silicon-ID-Read opera-tion to supplement traditional PROM programming meth-odology. The operation is initiated by writing the read silicon ID command sequence into the command regis-ter. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H.A read cycle with A1=VIL, A0=VIH returns the device code of A7H/A8H for MX29LV320A T/B.

be reinitiated once the device has returned to reading array data, to ensure data integrity.

The system can determine the status of the erase op-eration by using Q7, Q6, Q2, or RY/BY . See "Write Op-eration Status" for information on these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

Figure 5 illustrates the algorithm for the erase opera-tion.See the Erase/Program Operations tables in "AC Char-acteristics" for parameters, and to Figure 4 for timing diagrams.

MX29LV320AT/B

SECTOR ERASE COMMANDS

The device does not require the system to entirely pre-program prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later , while the command(data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 50us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com-mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, When the Erase Suspend com-mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to re-spond to the Erase Resume, program data to, or read data from any sector not selected for erasure. The sys-tem can use Q7, or Q6 and Q2 together, to determine if a sector is actively erasing or is erase-suspended. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro-gram operation is complete, the system can once again read array data within non-suspended blocks.

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.

MX29LV320AT/B

Table 5. Write Operation Status

Notes:

1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2.Performing successive read operations from any address will cause Q6 to toggle.

3.Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1"at the Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

WRITE OPERATION STATUS

The device provides several bits to determine the sta-tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY .T able 5 and the following subsections describe the func-tions of these bits. Q7, RY/BY , and Q6 each offer a

method for determining whether a program or erase op-eration is complete or in progress. These three bits are discussed first.

Status

Q7Q6Q5Q3Q2RY/BY Note1Note2Byte/Word Program in Auto Program Algorithm Q7Toggle 0N/A No 0Toggle Auto Erase Algorithm

0Toggle 01

Toggle

0Erase Suspend Read

No 0N/A Toggle 1(Erase Suspended Sector)

Toggle In Progress

Erase Suspended Mode

Erase Suspend Read Data Data Data Data Data 1(Non-Erase Suspended Sector)Erase Suspend Program

Q7Toggle 0N/A N/A 0Byte/Word Program in Auto Program Algorithm

Q7Toggle 1N/A No 0Toggle Exceeded

Time Limits Auto Erase Algorithm

0Toggle 11Toggle 0Erase Suspend Program

Toggle

N/A