HEF4011BP

DATA SHEET

Product speci?cation

File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF4011B gates

Quadruple 2-input NAND gate

For a complete data sheet, please also download:

?The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC ?The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

Quadruple 2-input NAND gate

gates

DESCRIPTION

The HEF4011B provides the positive quadruple 2-input

NAND function. The outputs are fully buffered for highest

noise immunity and pattern insensitivity of output

impedance.

Fig.1 Functional diagram.HEF4011BP(N):14-lead DIL; plastic

(SOT27-1)

HEF4011BD(F):14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4011BT(D):14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.2 Pinning diagram.

FAMILY DATA, I DD LIMITS category GATES See Family Specifications

Fig.3 Logic diagram (one gate).

Quadruple 2-input NAND gate

gates

AC CHARACTERISTICS

V SS=0 V; T amb=25°C; C L=50 pF; input transition times≤20 ns

V DD V SYMBOL TYP MAX

TYPICAL EXTRAPOLATION

FORMULA

Propagation delays555110ns28 ns+(0,55 ns/pF) C L I n→O n10t PHL; t PLH2545ns14 ns+(0,23 ns/pF) C L

152035ns12 ns+(0,16 ns/pF) C L Output transition times560120ns10 ns+(1,0 ns/pF) C L HIGH to LOW10t THL3060ns9 ns+(0,42 ns/pF) C L

152040ns 6 ns+(0,28 ns/pF) C L

560120ns10 ns+(1,0 ns/pF) C L LOW to HIGH10t TLH3060ns9 ns+(0,42 ns/pF) C L

152040ns 6 ns+(0,28 ns/pF) C L

V DD

V

TYPICAL FORMULA FOR P (μW)

Dynamic power51300 f i+∑(f o C L)×V DD2where

dissipation per106000 f i+∑(f o C L)×V DD2f i=input freq. (MHz) package (P)1520 100 f i+∑(f o C L)×V DD2f o=output freq. (MHz)

C L=load capacitance (pF)

∑(f o C L)=sum of outputs

V DD=supply voltage (V)