74VHC273SJ中文资料
April 1994
Revised April 1999
74VHC273 Octal D-Type Flip-Flop ? 1999 Fairchild Semiconductor Corporation DS011670.prf https://www.wendangku.net/doc/a61118171.html, 74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal D-
type flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: f MAX= 165 MHz (typ) at V CC= 5V
s Low power dissipation: I CC= 4 μA (max) at T A= 25°C
s High noise immunity: V NIH= V NIL= 28% V CC (min)
s Power down protection is provided on all inputs
s Low noise: V OLP= 0.9V (max)
s Pin and function compatible with 74HC273
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC273M M20B20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ M20D20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N N20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D0–D7Data Inputs
MR Master Reset
CP Clock Pulse Input
Q0–Q7Data Outputs
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74V H C 273
Function Table
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Operating Mode
Inputs Outputs MR
CP D n Q n Reset (Clear)L X
X L Load ’1’H H H Load ’0’
H
L
L
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74VHC273
Absolute Maximum Ratings (Note 1)
Recommended Operating Conditions (Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifica-tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari-ables. Fairchild does not recommend operation outside databook specifica-tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter guaranteed by design.
Supply Voltage (V CC )?0.5V to +7.0V DC Input Voltage (V IN )?0.5V to +7.0V DC Output Voltage (V OUT )?0.5V to V CC + 0.5V
Input Diode Current (I IK )?20 mA Output Diode Current (I OK )±20 mA DC Output Current (I OUT )±25 mA DC V CC /GND Current (I CC )±75 mA
Storage Temperature (T STG )?65°C to +150°C
Lead Temperature (T L )(Soldering, 10 seconds)
260°C
Supply Voltage (V CC ) 2.0V
to +5.5V Input Voltage (V IN )0V to
+5.5V Output Voltage (V OUT )0V to V CC
Operating Temperature (T OPR )?40°C to +85°C
Input Rise and Fall Time (t r , t f )V CC = 3.3V ± 0.3V 0 ns/V ～ 100 ns/V V CC = 5.0V ± 0.5V
0 ns/V ～ 20 ns/V Symbol Parameter
V CC (V)T A = 25°C
T A = ?40°C to +85°C Units Conditions
Min Typ
Max
Min Max
V IH HIGH Level Input 2.0 1.50 1.50V Voltage
3.0 ? 5.50.7 V CC
0.7 V CC
V IL LOW Level Input 2.00.500.50V
Voltage
3.0 ? 5.50.3 V CC
0.3 V CC V OH
HIGH Level Output 2.0 1.9 2.0 1.9V
V IN = V IH I OH = ?50 μA
Voltage
3.0 2.9 3.0 2.9or V IL
4.5 4.4 4.5 4.43.0 2.58 2.48V
I OH = ?4 mA 4.5
3.94
3.80
I OH = ?8 mA V OL
LOW Level Output 2.00.00.10.1
V V IN = V
IH I
OL
= 50 μA
Voltage
3.00.00.10.1or V IL
4.50.0
0.10.13.00.360.44V I OL = 4 mA 4.5
0.360.44I OL = 8 mA
I IN Input Leakage 0 ? 5.5
±0.1
±1.0
μA V IN = 5.5V or GND Current
I CC
Quiescent Supply 5.5
4.0
40.0
μA
V IN = V CC or GND
Current
Symbol Parameter
V CC
(V)T A = 25°C Units Conditions Typ Limits V OLP Quiet Output Maximum Dynamic V OL 5.00.60.9V C L = 50 pF (Note 3) V OLV Quiet Output Minimum Dynamic V OL
5.0?0.6
?0.9V C L = 50 pF (Note 3) V IHD Minimum HIGH Level Dynamic Input Voltage 5.0 3.5V C L = 50 pF (Note 3) V ILD Maximum LOW Level Dynamic Input Voltage
5.0
1.5
V
C L = 50 pF
(Note 3)
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74V H C 273
AC Electrical Characteristics
Note 4: Parameter guaranteed by design t OSLH = |t PLH max ? t PLH min|; t OSHL = |t PHL max ? t PHL min|.
Note 5: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: I CC (opr.) = C PD * V CC * f IN + I CC /8 (per F/F). The total C PD when n pieces of the Flip Flop operates can be calculated by the equation: C PD (total) = 22 + 9n.
AC Operating Requirements
Note 6: V CC is 3.3 ± 0.3V or 5.0 ± 0.5V
Symbol Parameter
V CC (V)T A = 25°C
T A = ?40°C to +85°C Units Conditions
Min Typ Max
Min Max
f MAX
Maximum Clock 3.3 ± 0.3
7512065MHz C L = 15 pF Frequency
507545C L = 50 pF 5.0 ± 0.5
120165100MHz C L = 15 pF 80
11070C L = 50 pF t PLH Propagation Delay 3.3 ± 0.3
8.713.6 1.016.0ns C L = 15 pF t PHL
Time (CK - Q)
11.217.1 1.019.5C L = 50 pF 5.0 ± 0.5
5.89.0 1.010.5ns C L = 15 pF 7.311.0 1.012.5C L = 50 pF t PHL
Propagation Delay 3.3 ± 0.3
8.913.6 1.016.0ns C L = 15 pF Time (MR - Q)
11.417.1 1.019.5C L = 50 pF 5.0 ± 0.5
5.28.5 1.010.0ns C L = 15 pF
6.7
10.5 1.0
12.0C L = 50 pF
t OSLH Output to 3.3 ± 0.3 1.5 1.5ns (Note 4)C L = 50 pF t OSHL Output Skew 5.0 ± 0.5
1.0
1.0C L = 50 pF
C IN Input Capacitance 41010pF V CC = Open C PD
Power Dissipation 31
pF
(Note 5)
Capacitance
Symbol Parameter
V CC (V)(Note 6)T A = 25°C T A = ?40°C to +85°C
Units
Typ
Guaranteed Minimum t W (L)Minimum Pulse Width (CK)
3.3 5.5 6.5ns t W (H) 5.0 5.0 5.0t W (L)Minimum Pulse Width (MR) 3.3 5.0 6.0ns 5.0 5.0 5.0t S Minimum Setup Time 3.3 5.5 6.5ns 5.0
4.5 4.5t H Minimum Hold Time
3.3 1.0 1.0ns 5.0 1.0 1.0t REC
Minimum Removal Time (MR)
3.3 2.5 2.5ns
5.0
2.0
2.0
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74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74V H C 273
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC273 Octal D-Type Flip-Flop
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1.Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.
2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or https://www.wendangku.net/doc/a61118171.html, Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A