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28278FAZ中文资料

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FN6145.2

ISL28278, ISL28478

Dual and Quad Micropower Single Supply Rail-to-Rail Input and Output (RRIO) Op-Amp

The ISL28278 and ISL28478 are dual and quad channel micropower operational amplifiers optimized for single supply operation over the 2.4V to 5V range. They can be operated from one lithium cell or two Ni-Cd batteries. For equivalent performance in a single channel op-amp reference EL8178.

These devices feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages 10% above the positive supply rail and to 100mV below the negative supply. The output operation is rail to rail.

The ISL28278 and ISL28478 draw minimal supply current while meeting excellent DC-accuracy, AC-performance, noise and output drive specifications. The ISL28278

contains a power down enable pin that reduces the power supply current to typically 4μA in the disabled state.

Pinouts

ISL28278 (16 LD QSOP)

TOP VIEW

ISL28478 (16 LD QSOP)

TOP VIEW

Features

?Low power 120μA typical supply current (ISL28278)?225μV max offset voltage ?30pA max input bias current

?300kHz typical gain-bandwidth product ?105dB typical PSRR ?100dB typical CMRR

?Single supply operation down to 2.4V

?Input is capable of swinging above V+ and below V- (ground sensing)?Rail-to-rail input and output (RRIO)?Enable Pin (ISL28278 only)

?Pb-free plus anneal available (RoHS compliant)

Applications

?Battery- or solar-powered systems ?4mA to 25mA current loops

?Handheld consumer products ?Medical devices ?Thermocouple amplifiers ?Photodiode pre-amps ?pH probe amplifiers

Ordering Information

123

41615141356

71211108

9NC NC OUT_A IN-_A NC V+OUT_B IN-_B IN+_A IN+_B EN_A V-EN_B NC NC NC

-+

-+

12

3

416151413567

1211108

9OUT_A IN-_A IN+_A V+OUT_D IN-_D IN+_D V-IN+_B IN+_C IN-_B OUT_B IN-_C OUT_C NC NC

-+

-+

-+-+PART NUMBER

(Note)PART MARKING PACKAGE (Pb-Free)PKG. DWG.#ISL28278FAZ*28278FAZ 16 Ld QSOP MDP0040ISL28478FAZ*

28478FAZ

16 Ld QSOP

MDP0040

*“-T7” suffix is for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE:Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet

July 11, 2007

元器件交易网https://www.wendangku.net/doc/ab5111214.html,

Operating Junction

Absolute Maximum Ratings (T A = +25°C)

Thermal Information

Supply Voltage, V - to V + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Tolerance

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V

Thermal Resistance

θJA (°C/W)

16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 112Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . .+125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below https://www.wendangku.net/doc/ab5111214.html,/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

IMPORTANT NOTE:All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A

Electrical Specifications

V + = 5V, V - = 0V, V CM = 2.5V, R L = Open, T A = +25°C unless otherwise specified.

Boldface limits apply over the operating temperature range, -40°C to +125°C, temperature data established by characterization

PARAMETER DESCRIPTION

CONDITIONS

MIN (Note 1)

TYP

MAX (Note 1)

UNIT

DC SPECIFICATIONS V OS Input Offset Voltage

-225-450

±0.20

225450

μV Input Offset Voltage vs Temperature 1.0

μV/°C

I OS Input Offset Current

-40°C to +85°C

-30-80±5

3080pA I B Input Bias Current

-40°C to +85°C

-30-80±10

3080pA CMIR Common-Mode Voltage Range Guaranteed by CMRR 05

V CMRR Common-Mode Rejection Ratio V CM = 0V to 5V 8075100dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5V

8580

105dB A VOL

Large Signal Voltage Gain

V O = 0.5V to 4.5V, R L = 100k Ω 200

190300V/mV V O = 0.5V to 4.5V, R L = 1k Ω

60V/mV V OUT

Maximum Output Voltage Swing

Output low, R L = 100k Ω3630mV Output low, R L = 1k Ω130

175225

mV Output high, R L = 100k Ω 4.9904.97 4.996V Output high, R L = 1k Ω

4.8004.750

4.880V I S,ON

Quiescent Supply Current, Enabled ISL28278, All channels enabled.120156175μA ISL28478, All channels enabled.

240315350μA I S,OFF

Quiescent Supply Current, Disabled

All channels disabled.ISL28278

4

79μA

ΔV OS ΔT ---------------

I O +Short Circuit Sourcing Capability R L = 10Ω292431mA I O -Short Circuit Sinking Capability R L = 10Ω242026

mA V SUPPLY Supply Operating Range V - to V + 2.4 5.0V V ENH EN Pin High Level ISL282782

V V ENL EN Pin Low Level ISL282780.8V I ENH EN Pin Input High Current VEN = V+ISL282780.811.5μA I ENL

EN Pin Input Low Current

VEN = V-ISL28278

0.1

μA

AC SPECIFICATIONS GBW Gain Bandwidth Product

A V = 100, R F = 100k Ω, R G = 1k Ω,R L = 10k Ω to V CM 300kHz e n

Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 4.5μV P-P Input Noise Voltage Density

f O = 1kHz 45nV /√Hz i n

Input Noise Current Density

f O = 1kHz

0.04pA/√Hz CMRR @ 60Hz Input Common Mode Rejection Ratio V CM = 1V P-P , R L = 10k Ω to V CM

-70dB PSRR+ @120Hz Power Supply Rejection Ratio, +V V +,V - = ±1.2V and ±2.5V,

V SOURCE = 1V P-P , R L = 10k Ω to V CM -80dB PSRR- @120Hz

Power Supply Rejection Ratio, -V

V +,V - = ±1.2V and ±2.5V

V SOURCE = 1V P-P , R L = 10k Ω to V CM

-60

dB

TRANSIENT RESPONSE SR Slew Rate

±0.12±0.09

±0.14

±0.16±0.21

V/μs t EN

Enable to Output Turn-on Delay Time, 10% EN to 10% Vout

VEN = 5V to 0V, A V = -1,

R G = R F = R L = 1k to V CM , ISL282782μs Enable to Output Turn-off Delay Time, 10% EN to 10% Vout

VEN = 0V to 5V, A V = -1,

R G = R F = R L = 1k to V CM , ISL28278

0.1

μs

NOTE:

1.Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.

Electrical Specifications

V + = 5V, V - = 0V, V CM = 2.5V, R L = Open, T A = +25°C unless otherwise specified.

Boldface limits apply over the operating temperature range, -40°C to +125°C, temperature data established by characterization (Continued)

PARAMETER DESCRIPTION

CONDITIONS

MIN (Note 1)TYP MAX (Note 1)

UNIT

Typical Performance Curves V + = 5V, V - = 0V, V CM = 2.5V, R L = Open, unless otherwise specified.

FIGURE 1.FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 2.FREQUENCY RESPONSE vs SUPPLY VOLTAGE

FIGURE 3.A VOL vs FREQUENCY @ 100k Ω LOAD FIGURE 4.A VOL vs FREQUENCY @ 1k Ω LOAD

FIGURE 5.PSRR vs FREQUENCY FIGURE 6.CMRR vs FREQUENCY

V OUT = 50mV P-P A V = 1C L = 3pF

R F = 0, R G = INF

8G A I N (d B )

-5-4-30+1-2-1-7-610k

100k

1M

FREQUENCY (Hz)

1k

V +,V -= ±2.5V RL = 10k 5M

V +,V -= ±1.2V RL = 10k

V +,V -= ±2.5V RL = 1k

V +,V -= ±1.2V RL = 1k

A V = 100R L = 10k ΩC L = 3pF R F = 100k ΩR G = 1k Ω

0G A I N (d B )

15202540453035510100

10k

100k 1M

FREQUENCY (Hz)

1k

V +,V -= ±1.0V

V +,V -= ±1.2V

V +,V -= ±2.5V

-80

G A I N (d B )

4012080

-400

11k 100k 10M

FREQUENCY (Hz)

10-120P H A S E (°)

8040

0-40-8010k 1M

100GAIN

PHASE

-20G A I N (d B )

020*******

6010

10k 1M

FREQUENCY (Hz)

100-150P H A S E (°)

200150100500

-50-100

100k

1k PHASE

GAIN

-100

-90

-80-70-60-50-40-30-20-1001010

1001k 10k 100k FREQUENCY (Hz)P S R R (d B )

PSRR +

PSRR -V SOURCE = 1V P-P R L = 10k ΩV +,V - = ±2.5VDC

A V = +1

1M -100

-90-80-70-60-50-40-30-20-1010

FREQUENCY (Hz)

C M R R (d B )

0V SOURCE = 1V P-P R L = 10k Ω

V +,V - = ±2.5VDC 10

1001k 10k 100k 1M

FIGURE 7.VOLTAGE NOISE vs FREQUENCY FIGURE 8.CURRENT NOISE vs FREQUENCY

FIGURE 9.0.1Hz TO 10Hz INPUT VOLTAGE NOISE FIGURE 10.SMALL SIGNAL TRANSIENT RESPONSE

FIGURE https://www.wendangku.net/doc/ab5111214.html,RGE SIGNAL TRANSIENT RESPONSE

FIGURE 12.ISL28278 ENABLE TO OUTPUT DELAY TIME

101001k 1

10

100

1k

10k

FREQUENCY (Hz)

V O L T A G E N O I S E (n V /√H z )

10

100

1k

110

100

1k 10k

FREQUENCY (Hz)

C U R R E N T N O I S E (f A /√H z )

1

2

3

4

5

6

7

8

9

10

TIME (1s/DIV)

V O L T A G E N O I S E (0.5μV /D I V )

-2.5

-2.0-1.5-1.0-0.500.51.01.5

2.02.5 2.42

2.462.48

2.502.522.54

2.56

2

4

6

8

10

12

14

16

18

20

2.44V OUT = 0.1V P-P R L = 1k Ω V + = 5VDC

A V = +1TIME (μs)

V O L T S (V )

V OUT

V IN

V IN

V OUT

50

100

150

200

250V OUT = 4V P-P R L = 1k ΩV + = 5VDC A V = -2

012354TIME (μs)

V O L T S (V )

1V /D I V

0.1V /D I V

10μs/DIV

V OUT

EN INPUT

A V = -1

V IN = 200mV P-P V+ = 5V

FIGURE 13.INPUT OFFSET VOLTAGE vs COMMON MODE

INPUT VOLTAGE FIGURE 14.INPUT BIAS CURRENT vs COMMON-MODE

INPUT VOLTAGE

FIGURE 15.ISL28478 SUPPLY CURRENT vs TEMPERATURE,

V +,V - = ±2.5V, R L = INF FIGURE 16.ISL28278 DISABLED SUPPLY CURRENT vs

TEMPERATURE, V +,V - = ±2.5V R L = INF

FIGURE 17.V OS vs TEMPERATURE, V IN = 0V, V +,V - = ±2.5V FIGURE 18.V OS vs TEMPERATURE, V IN = 0V, V +,V - = ±1.2V

-1000

-800-600-400-20002004006008001000-1

1

234

5

6

V CM (V)

V O S (μV )

V + = 5V R L = OPEN

A V = +1000R F = 100k, R G = 100-100

-80-60-40-20020406080100-1

1

234

5

6

V CM (V)

I B I A S (p A )

V + = 5V R L = OPEN

A V = +1000

R F = 100k, R G = 100-40

-20

20406080100

120

TEMPERATURE (°C)

190200210220230240250260270280C U R R E N T (μA )

MAX

MEDIAN

MIN

N = 1000

3.23.4

3.63.8

4.04.24.44.6

4.8

-40-20020406080100120

TEMPERATURE (°C)

C U R R E N T (μA )

n = 12

MAX

MIN

MEDIAN

-400

-300-200-1000100200300400500V O S (μV )

MAX

MEDIAN

MIN

N = 1000

-40

-200

20406080100120

TEMPERATURE (°C)

-400

-300

-200-1000100200300400

500V O S (μV )

MAX

MEDIAN

MIN

N = 1000

-40

-200

20406080100120

TEMPERATURE (°C)

FIGURE 19.I BIAS + vs TEMPERATURE, V +,V - = ±2.5V FIGURE 20.I BIAS - vs TEMPERATURE, V +,V - = ±2.5V

FIGURE 21.I BIAS + vs TEMPERATURE, V +,V - = ±1.2V

FIGURE 22.I BIAS - vs TEMPERATURE, V +,V - = ±1.2V

FIGURE 23.I OS vs TEMPERATURE, V +,V - = ±2.5V

FIGURE 24.A VOL vs TEMPERATURE, V +,V - = ±2.5V, R L = 100k

-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)-2500

-2000

-1500

-1000-5000500

n = 1000

I B I A S + (p A )

MEDIAN

MAX

MIN

-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)

-1400

-1200-1000-800-600-400-200

0200I B I A S - (p A )

n = 1000

MAX

MEDIAN MIN -40-20020406080

100

120

TEMPERATURE (°C)

-2500

-2000

-1500-1000-500

0500n = 1000

I B I A S + (p A )

MIN

MEDIAN

MAX

-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)

-1200

-1000

-800-600-400-200

0200

n = 1000

I B I A S - (p A )

MIN

MEDIAN

MAX

-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)

-1400

-1200-1000-800-600-400-200

0200I O S (p A )

n = 1000

MIN MEDIAN

MAX

-40

-20

20406080100

120

TEMPERATURE (°C)

150200

250300350400450500550

A V O L (V /m V )

MAX

MEDIAN MIN

N = 1000

FIGURE 25.A VOL vs TEMPERATURE, V +,V - = ±2.5V, R L = 1k

FIGURE 26.CMRR vs TEMPERATURE, V CM = +2.5V TO -2.5V

V +,V - = ±2.5V

FIGURE 27.PSRR vs TEMPERATURE, V +,V - = ±1.2V TO ±2.5V

FIGURE 28.V OUT HIGH vs TEMPERATURE, V +,V - = ±2.5V,

R L = 1k

FIGURE 29.V OUT HIGH vs TEMPERATURE, V +,V - = ±2.5V,

R L = 100k

FIGURE 30.V OUT LOW vs TEMPERATURE, V +,V - = ±2.5V,

R L = 1k

304050607080

90

MAX

MEDIAN

MIN

N = 1000

-40

-200

20406080100120TEMPERATURE (°C)

A V O L (V /m V )

758595105115125135

C M R R (d B )

MAX

MEDIAN

MIN

N = 1000

-40

-200

20406080100120

TEMPERATURE (°C)

8090100110120

130140

P S R R (d B )

MAX

MEDIAN

MIN N = 1000

-40

-200

20406080100120

TEMPERATURE (°C)

4.85

4.864.87

4.884.894.90

4.91

V O U T (V )

MAX

MEDIAN

MIN

N = 1000

-40

-200

20406080100120

TEMPERATURE (°C)

4.9964

4.99664.99684.99704.99724.99744.99764.99784.99804.99824.9984V O U T (V )

n = 12

MEDIAN

-40

-20

20406080100

120

TEMPERATURE (°C)

MAX

MIN

90100

110120

130140150160

V O U T (m V )

MAX

MIN

N = 1000

-40

-200

20406080100120

TEMPERATURE (°C)

MEDIAN

FIGURE 31. V OUT LOW vs TEMPERATURE, V +,V - = ±2.5V,

R L = 100k

FIGURE 32.+ OUTPUT SHORT CIRCUIT CURRENT vs

TEMPERATURE, V IN = -2.55V, R L = 10, V +,V - = ±2.5V

FIGURE 33. - OUTPUT SHORT CIRCUIT CURRENT vs

TEMPERATURE, V IN = +2.55V, R L = 10, V +,V - = ±2.5V

FIGURE 34. + SLEW RATE vs TEMPERATURE, V OUT = ±1.5V,

A V = +2

FIGURE 35.- SLEW RATE vs TEMPERATURE, V OUT = ±1.5V, A V = +2

3.43.53.63.73.83.9

4.04.14.24.3-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)

V O U T (m V )

n = 12

MIN

MAX

MEDIAN

-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)

2527293133

35373941 + O U T P U T S H O R T C I R C U I T C U R R E N T (m A )

MAX

MIN N = 1000

MEDIAN

-33-31-29-27

-25-23

-21

- O U T P U T S H O R T C I R C U I T C U R R E N T (m A )

MAX

MIN

N = 1000

-40

-20

20

40

60

80

100

120

TEMPERATURE (°C)MEDIAN

0.09

0.10

0.110.120.130.140.150.160.170.180.19+ S L E W R A T E (V /μs )

MAX

MIN

N = 1000

-40

-20020406080100120

TEMPERATURE (°C)

MEDIAN

- S L E W R A T E (V /μs )

0.100.110.120.130.140.150.160.170.180.190.20MAX

MIN

N = 1000

-40

-20020406080100120

TEMPERATURE (°C)

MEDIAN

Applications Information

Introduction

The ISL28278 and ISL28478 are dual and quad CMOS rail-to-rail input, output (RRIO) micropower operational amplifiers. These devices are designed to operate from a single supply (2.4V to 5.0V) or dual supplies (±1.2V to ±2.5V) while drawing only 120μA (ISL28278) of supply current. This combination of low power and precision performance makes these devices suitable for solar and battery power applications.

Rail-to-Rail Input

Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an

undesired change in magnitude and polarity of input offset current.

The ISL28278 achieves input rail-to-rail without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically 100mV below the negative rail and 10% higher than the V + rail (0.5V higher than V + when V + equals 5V).

Input Protection

All input terminals have internal ESD protection diodes to the positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. There is an additional pair of back-to-back diodes across the input

terminals. For applications where the input differential voltage is expected to exceed 0.5V, external series resistors must be used to ensure the input currents never exceed 5mA.

Pin Descriptions

ISL28278(16 LD QSOP)

ISL28478(16 LD QSOP)

PIN NAME EQUIVALENT CIRCUIT DESCRIPTION

31OUT_A Circuit 3Amplifier A output 42IN-_A Circuit 1Amplifier A inverting input 53IN+_A Circuit 1Amplifier A non-inverting input 154V+Circuit 4Positive power supply 125IN+_B Circuit 1Amplifier B non-inverting input 136IN-_B Circuit 1Amplifier B inverting input 147OUT_B Circuit 3

Amplifier B output 1, 2, 8, 9, 10, 16

8, 9NC No internal connection 10OUT_C Circuit 3Amplifier C output 11IN-_C Circuit 1Amplifier C inverting input 12

IN+_C Circuit 1Amplifier B non-inverting input 7

13V-Circuit 4Negative power supply 14IN+_D Circuit 1Amplifier D non-inverting input 15IN-_D Circuit 1Amplifier D inverting input 16

OUT_D Circuit 3Amplifier D output

6EN_A Circuit 2Amplifier A enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state.

11

EN_B

Circuit 2Amplifier B enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state.

IN-V +

V -

LOGIC PIN

V +

V -V +V -

OUT CIRCUIT 3

CIRCUIT 1

CIRCUIT 2

IN+V +

V -CAPACITIVELY COUPLED ESD CLAMP

CIRCUIT 4

Rail-to-Rail Output

A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. Both parts, with a 100k Ω load, will typically swing to within 4mV of the positive supply rail and within 3mV of the negative supply rail.

Enable/Disable Feature

The ISL28278 offers two EN pins (EN_A and EN_B) which disable the op amp when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 4μA. By disabling the part, multiple parts can be connected together as a MUX. The outputs are tied together in parallel and a channel can be selected by the EN pins. The loading effects of the feedback resistors of the disabled amplifier must be considered when multiple

amplifier outputs are connected together. The EN pin also has an internal pull-down. If left open, the EN pin will pull to the negative rail and the device will be enabled by default.

Using Only One Channel

The ISL28278 and ISL28478 are dual and quad channel op amps. If the application only requires one channel when using the ISL28278 or less than 4 channels when using the ISL28478, the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the

negative input and ground the positive input (as shown in Figure 36).

Proper Layout Maximizes Performance

To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28278 and ISL28478, care should be taken in the circuit board layout. The PC board surface must remain clean and free of

moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 37 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should

form a continuous loop around both inputs. For further

reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators.

Example Application

Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The ISL28X78 (Figure 38) is used to convert the differential

thermocouple voltage into single-ended signal with 10X gain. The ISL28X78's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the amplifier to run from a single 5V supply.

Current Limiting

The ISL28278 and ISL28478 have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device.

Power Dissipation

It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the

maximum junction temperature (T JMAX ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1:

FIGURE 36.PREVENTING OSCILLATIONS IN UNUSED

CHANNELS

-

+

1/2 ISL282781/4 ISL28478

FIGURE 37.GUARD RING EXAMPLE FOR UNITY GAIN

AMPLIFIER

-+

5V

+

V+V-

ISL28X78K TYPE

THERMOCOUPLE

10k ΩR 310k Ω

R 2

R 4100k Ω

R 1100k Ω

410μV/°C

FIGURE 38.THERMOCOUPLE AMPLIFIER

T JMAX T MAX θJA xPD MAXTOTAL ()

+=(EQ. 1)

where:

?P DMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PD MAX )?PD MAX for each amplifier is calculated in Equation 2:

where:

?T MAX = Maximum ambient temperature ?θJA = Thermal resistance of the package

?PD MAX = Maximum power dissipation of 1 amplifier ?V S = Supply voltage (Magnitude of V + and V -)?I MAX = Maximum supply current of 1 amplifier ?V OUTMAX = Maximum output voltage swing of the application ?R L = Load resistance

PD MAX 2*V S I SMAX V S ( - V OUTMAX )V OUTMAX

R

L

----------------------------×+×=(EQ. 2)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at https://www.wendangku.net/doc/ab5111214.html,/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see https://www.wendangku.net/doc/ab5111214.html,

Quarter Size Outline Plastic Packages Family (QSOP)

0.010

C A B

SEATING PLANE DETAIL X

E E1

1(N/2)

(N/2)+1

N

PIN #1I.D. MARK

b

0.004C c

A

SEE DETAIL "X"

A2

4°±4°

GAUGE PLANE 0.010

L

A1

D

B H

C

e

A

0.007

C A B

L1

MDP0040

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY

SYMBOL INCHES

TOLERANCE NOTES

QSOP16QSOP24QSOP28A 0.0680.0680.068Max.-A10.0060.0060.006±0.002-A20.0560.0560.056±0.004-b

0.0100.0100.010±0.002-c 0.0080.0080.008±0.001-D 0.1930.3410.390±0.0041, 3E

0.2360.2360.236±0.008-E10.1540.1540.154±0.0042, 3e 0.0250.0250.025Basic -L 0.0250.0250.025±0.009-L10.0410.0410.041Basic -N

16

24

28

Reference

-Rev. F 2/07

NOTES:

1.Plastic or metal protrusions of 0.006” maximum per side are not included.

2.Plastic interlead protrusions of 0.010” maximum per side are not included.

3.Dimensions “D” and “E1” are measured at Datum Plane “H”.

4.Dimensioning and tolerancing per ASME Y14.5M-1994.

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