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WSE128K16-300G2TMA中文资料

WSE128K16-XXX

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PRELIMINARY*

128Kx16 SRAM/EEPROM MODULE

FEATURES

Access Times of 35ns (SRAM) and 150ns (EEPROM) Access Times of 45ns (SRAM) and 120ns (EEPROM) Access Times of 70ns (SRAM) and 300ns (EEPROM) Packaging

? 66 pin, PGA Type, 1.075" square HIP , Hermetic Ceramic HIP (H1) (Package 400)? 68 lead, Hermetic CQFP (G2T), 22mm (0.880") square (Package 509). Designed to ? t JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2) 128Kx16 SRAM 128Kx16 EEPROM

Organized as 128Kx16 of SRAM and 128Kx16 of

EEPROM Memory with separate Data Buses Both blocks of memory are User Con? gurable as

256Kx8 Low Power CMOS

Commercial, Industrial and Military Temperature

Ranges TTL Compatible Inputs and Outputs

Built-in Decoupling Caps and Multiple Ground Pins

for Low Noise Operation Weight - 13 grams typical

EEPROM MEMORY FEATURES

Write Endurance 10,000 Cycles Data Retention at 25°C, 10 Years Low Power CMOS Operation Automatic Page Write Operation Page Write Cycle Time 10ms Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs

* T his product is under development, is not quali? ed or characterized and is subject to change without notice.

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WSE128K16-XXX

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WSE128K16-XXX

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RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5V Input High Voltage V IH 2.0V CC + 0.3V Input Low Voltage V IL -0.3+0.8V Operating Temp. (Mil.)

T A

-55

+125

°C

EEPROM TRUTH TABLE

CS#OE#WE#Mode Data I/O H X X Standby High Z L L H Read Data Out L H L Write Data In X H X Out Disable High Z/Data Out

X X H Write Inhibit

SRAM TRUTH TABLE

SCS#OE#SWE#Mode

Data I/O Power H X X Standby High Z Standby L L H Read Data Out Active L H H

Read

High Z

Active

L X L Write Data In Active

DC CHARACTERISTICS

V CC = 5.0V, GND = 0V, -55°C ≤ T A ≤ +125°C

Parameter

Symbol Conditions

Min

Max Unit Input Leakage Current I LI V CC = 5.5, V IN = GND to V CC

10μA Output Leakage Current

I LO SCS# = V IH , OE# = V IH , V OUT = GND to V CC

10μA SRAM Operating Supply Current x 16 Mode I CC x16SCS# = V IL , OE# = ECS# = V IH , f = 5MHz, V CC = 5.5360mA Standby Current

ISB ECS# = SCS# = V IH , OE# = V IH , f = 5MHz, V CC = 5.531.2mA SRAM Output Low Voltage

(35 to 45ns)

V OL I OL = 8.0mA, V CC = 4.50.4V (70ns)V OL I OL = 2.1mA, V CC = 4.50.4

V SRAM Output High Voltage

(35 to 45ns)

V OH I OH = -4.0mA, V CC = 4.5 2.4V (70ns)

V OH I OH = -1mA, V CC = 4.5

2.4

V EEPROM Operating Supply Current x 16 Mode I CC1ECS# = V IL , OE# = SCS# = V IH 155mA EEPROM Output Low Voltage V OL I OL = 2.1 mA, V CC = 4.5V 0.45

V EEPROM Output High Voltage

V OH1

I OH = 400 μA, V CC = 4.5V

2.4

NOTES:1. The I CC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).

The frequency component typically is less than 2 mA/MHz, with OE at V IH .2. DC test conditions: V IL = 0.3V, V IH = V CC - 0.3V

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol Min Max Unit Operating Temperature T A -55+125°C Storage Temperature

T STG -65+150°C Signal Voltage Relative to GND V G -0.5V CC +0.5V Junction Temperature T J 150°C Supply Voltage

V CC

-0.5

7.0

CAPACITANCE

T A = +25°C

Parameter

Symbol Conditions Max Unit OE# capacitance C OE V IN = 0 V, f = 1.0 MHz 50pF WE#1-4 capacitance HIP (PGA)C WE V IN = 0 V, f = 1.0 MHz 20pF CQFP G2T

20CS#1-4 capacitance C CS V IN = 0 V, f = 1.0 MHz 20pF Data I/O capacitance C I/O V I/O = 0 V, f = 1.0 MHz 20pF Address input capacitance

C AD

V IN = 0 V, f = 1.0 MHz

This parameter is guaranteed by design but not tested.

WSE128K16-XXX

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SRAM AC CHARACTERISTICS

V CC = 5.0V, GND = 0V, -55°C ≤ T A ≤ +125°C

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WSE128K16-XXX

PRELIMINARY FIGURE 4 – SRAM READ CYCLES

FIGURE 5 – SRAM WRITE CYCLE SWE# CONTROLLED

FIGURE 6 – SRAM WRITE CYCEL SCS# CONTROLLED

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EEPROM WRITE

A write cycle is initiated when OE# is high and a low pulse is on EWE# or ECS# with ECS# or EWE# low. The address is latched on the falling edge of ECS# or EWE# whichever occurs last. The data is latched by the rising edge of ECS# or EWE#, whichever occurs ? rst. A byte write operation will automatically continue to completion.

WRITE CYCLE TIMING

Figures 7 and 8 show the write cycle timing relationships.

A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the ECS# line low. Write enable consists of setting the EWE# line low. The write cycle begins when the last of either ECS# or EWE# goes low.

The EWE# line transition from high to low also initiates an internal 150 μsec delay timer to permit page mode operation. Each subsequent EWE# transition from high to low that occurs before the completion of the 150 μsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot.

EEPROM AC WRITE CHARACTERISTICS V CC = 5.0V, GND = 0V, -55°C ≤ T A ≤ +125°C

Write Cycle Parameter Symbol Min Max Unit Write Cycle Time, TYP = 6ms t WC10ms Address Set-up Time t AS0ns Write Pulse Width (EWE# or ECS#)t WP150ns Chip Select Set-up Time t CS0ns Address Hold Time t AH100ns Data Hold Time t DH10ns Chip Select Hold Time t CSH0ns Data Set-up Time t DS100ns Output Enable Set-up Time t OES10ns Output Enable Hold Time t OEH10ns Write Pulse Width High t WPH50ns

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WSE128K16-XXX

PRELIMINARY FIGURE 7 – EEPROM WRITE WAVEFORMS EWE# CONTROLLED

WSE128K16-XXX

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FIGURE 9 – EEPROM READ WAVEFORMS

EEPROM READ

The WSE128K16-XXX EEPROM stores data at the memory location determined by the address pins. When ECS# and OE# are low and EWE# is high, this data is present on the outputs. When ECS# and OE# are high, the outputs are in a high impedance state. This two line control prevents bus contention.

EEPROM AC READ CHARACTERISTICS

V CC = 5.0V, GND = 0V, -55°C ≤ T A ≤ +125°C

Read Cycle Parameter

Symbol -120-150

-300

Unit Min Max Min Max Min Max Read Cycle Time t RC 120

150

300

ns Address Access Time t ACC 120150300ns Chip Select Access Time

t ACS 120

150300ns Output Hold from Add. Change, OE# or ECS#t OH 000ns Output Enable to Output Valid

t OE 0

50055085ns Chip Select or OE# to High Z Output

t DF

WSE128K16-XXX

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EEPROM DATA POLLING

The WSE128K16-XXX offers a data polling feature for the EEPROM which allows a faster method of writing to the device. Figure 11 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle.

FIGURE 10 – EEPROM DATA POLLING WAVEFORMS

EEPROM DATA POLLING CHARACTERISTICS

V CC = 5.0V, GND = 0V, -55°C ≤ T A ≤ +125°C

Parameter Symbol Min Max

Unit Data Hold Time t DH 10ns OE# Hold Time t OEH 10ns OE# To Output Valid t OE 55

ns Write Recovery Time

t WR

WSE128K16-XXX

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EEPROM PAGE WRITE OPERATION

The WSE128K16-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the ? rst data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150μs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period.

The usual procedure is to increment the least signi? cant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle.

FIGURE 11 – EEPROM PAGE MODE WRITE WAVEFORMS EEPROM PAGE WRITE CHARACTERISTICS

V CC = 5.0V, GND = 0V, -55°C ≤ T A ≤ +125°C

Page Mode Write Characteristics Parameter

Symbol Min Max Unit Write Cycle Time, TYP = 6ms t WC 10

ms Address Set-up Time t AS 0ns Address Hold Time (1)t AH 100ns Data Set-up Time t DS 100ns Data Hold Time t DH 10ns Write Pulse Width t WP 150

ns Byte Load Cycle Time t BLC 150

μs Write Pulse Width High

t WPH

NOTE:

1. Page address must remain valid for duration of write cycle.

After the 150μs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed.

WSE128K16-XXX

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LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA A0

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS (4)

LOAD LAST BYTE

LAST ADDRESS

FIGURE 12 – EEPROM SOFTWARE DATA PROTECTION ENABLE ALGORITHM (1)

WRITES ENABLED (2)

NOTES:

1. Data Format: ED7 - ED0 (Hex); Address Format: A16 - A0 (Hex).

2. Write Protect state will be activated at end of write even if no other data is loaded.

3. Write Protect state will be deactivated at end of write period even if no other data is loaded.

4. 1 to 128 bytes of data may be loaded.

ENTER DATA PROTECT STATE

WSE128K16-XXX

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EEPROM HARDWARE DATA PROTECTION

These features protect against inadvertent writes to the WSE128K16-XXX. These are included to improve reliability during normal operation:

a) V CC power on delay

As V CC climbs past 3.8V typical the device will wait 5 msec typical before allowing write cycles.

b) V CC sense

While below 3.8V typical write cycles are inhibited.c) Write inhibiting

Holding OE# low and either ECS# or EWE# high inhibits write cycles.d) Noise ? lter

Pulses of <8ns (typ) on EWE# or ECS# will not initiate a write cycle.

EEPROM SOFTWARE DATA PROTECTION

A software write protection feature may be enabled or disabled by the user. When shipped by WEDC, the WSE128K16-XXX has the feature disabled. Write access to the device is unrestricted.

To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of twc. The write protection feature can be disabled by a six byte write sequence of speci? c data to speci? c locations. Power transitions will not reset the software write protection.

Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modi? cation using a PROM programmer.

FIGURE 13 – EEPROM SOFTWARE DATA PROTECTION DISABLE ALGORITHM (1)

EXIT DATA (3)PROTECT STATE

NOTES:

1. Data Format: ED7 - ED0 (Hex);

Address Format: A16 - A0 (Hex).

2. Write Protect state will be activated at end of write even if no other data

is loaded.

3. Write Protect state will be deactivated at end of write period even if no

other data is loaded.

4. 1 to 128 bytes of data may be loaded.

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 20

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS (4)

LOAD LAST BYTE

LAST ADDRESS

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WSE128K16-XXX

PRELIMINARY PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

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WSE128K16-XXX

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PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)

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WSE128K16-XXX

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ORDERING INFORMATION

W S E 128K16 - XXX X X X

LEAD FINISH:

Blank = Gold plated leads

A = Solder dip leads

DEVICE GRADE:

M = Military Screened -55°C to +125°C

I = I ndustrial -40°C to +85°C

C = Commercial 0°C to +70°C

PACKAGE TYPE:

H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400)

G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)

ACCESS TIME (ns)

35 = 35ns SRAM and 150ns EEPROM

42 = 45ns SRAM and 120ns EEPROM

73 = 70ns SRAM and 300ns EEPROM

ORGANIZATION, 128K x 16

EEPROM

SRAM

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