IRFP250NPbF
HEXFET ? Power MOSFET
2/11/04
Parameter
Max.
Units
I D @ T C = 25°C Continuous Drain Current, V GS @ 10V 30I D @ T C = 100°C Continuous Drain Current, V GS @ 10V 21A I DM
Pulsed Drain Current
120P D @T C = 25°C Power Dissipation 214W Linear Derating Factor 1.4W/°C V GS Gate-to-Source Voltage
± 20V E AS Single Pulse Avalanche Energy 315mJ I AR Avalanche Current
30A E AR Repetitive Avalanche Energy 21mJ dv/dt Peak Diode Recovery dv/dt 8.6V/ns T J Operating Junction and
-55 to +175T STG
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )°C
Mounting torque, 6-32 or M3 srew
10 lbf?in (1.1N?m)
Absolute Maximum Ratings
Parameter
Typ.
Max.
Units
R θJC Junction-to-Case
–––0.7R θCS Case-to-Sink, Flat, Greased Surface 0.24–––°C/W
R θJA
Junction-to-Ambient
–––
40
Thermal Resistance
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Description
l Advanced Process Technology l Dynamic dv/dt Rating
l 175°C Operating Temperature l Fast Switching
l Fully Avalanche Rated l Ease of Paralleling
l Simple Drive Requirements PD - 95007
l
Lead-Free
IRFP250NPbF
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Source-Drain Ratings and Characteristics
Starting T J = 25°C, L = 1.9mH
R G = 25?, I AS = 18A. (See Figure 12)
Repetitive rating; pulse width limited by max. junction temperature. (See Fig. 11)
Notes:
I SD ≤ 18A , di/d t ≤ 374A/μs, V DD ≤ V (BR)DSS ,
T J ≤ 175°C
Pulse width ≤ 300μs; duty cycle ≤ 2%.
Electrical Characteristics @ T = 25°C (unless otherwise specified)
IRFP250NPbF
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Vs. Temperature
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Fig 5. Typical Capacitance Vs.Drain-to-Source Voltage
Fig 6.Gate-to-Source Voltage
Forward Voltage
Typical Gate Charge Vs.
1
10
100
1000
V DS , Drain-to-Source Voltage (V)
01000
2000
3000
4000
5000
C , C a p a c i t a n c e (p F )
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Fig 9. Maximum Drain Current Vs.
Fig 10a. Switching Time Test Circuit
V V d(on)
r
d(off)
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
DD
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V
DS
Current Sampling Resistors
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform Fig 12b. Unclamped Inductive Waveforms
I AS
Vs. Drain Current
V DD
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Fig 14. For N-Channel HEXFETS
* V GS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
V DD
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TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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Note: For the most current drawings please refer to the IR website at:
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