物理新视角看MOS管功率损耗New Physical Insights on Power MOSFET Switching Losses
New Physical Insights on Power MOSFET
Switching Losses
Yali Xiong,Member,IEEE,Shan Sun,Student Member,IEEE,Hongwei Jia,Student Member,IEEE, Patrick Shea,Student Member,IEEE,and Z.John Shen,Senior Member,IEEE
Abstract—Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and ef?ciency of power electronics circuits.The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach,and subsequently examine the commonly used power loss calculation method in light of the new physical insights.The widely accepted output capacitance loss term is found to be redun-dant and erroneous based on the new modeling and measurement results.In addition,the existing method of approximating switch-ing times with the power MOSFET gate charge parameters grossly overestimates the switching power loss.This paper recommends a new MOSFET gate charge parameter speci?cation and an effec-tive switching time estimation method to compensate for the power loss calculation error introduced by the two-slope voltage transi-tion waveform of the power MOSFET.
Index Terms—Power converters,power MOSFET,switching power loss.
I.I NTRODUCTION
T HE SWITCHING loss of power MOSFETs becomes a dominant factor in the total power loss of power electronics converters when the switching frequency is increased to improve dynamic performance and reduce size.A simple yet reasonably accurate method of estimating power MOSFET switching losses using device datasheet information is highly desirable for pre-dicting maximum junction temperatures and overall power con-verter ef?ciencies.However,the complex switching behavior and switching losses of a power MOSFET are dif?cult to model analytically due to the nonlinear characteristics of MOSFET parasitic capacitances.
Fig.1shows a typical diode-clamped inductive load switch-ing circuit.This simple switch-diode-inductor pole is widely used in nearly all power electronics topologies including buck, boost,buck-boost converters,and inverters.The three interelec-
Manuscript received May5,2008;revised September11,2008;accepted September12,2008.Current version published February6,2009.This work was presented in part at the IEEE Industry Application Society Meeting(IAS), Tampa,FL,2006.This work was supported in part by the U.S.National Science Foundation under Award ECS-0454835and by a grant from Intel Corporation. Recommended for publication by Associate Editor Y.C.Liang.
Y.Xiong was with the School of Electrical Engineering and Computer Sci-ence,University of Central Florida,Orlando,FL32816USA.She is now with International Recti?er Corporation,Temecula,CA92590USA(e-mail: dancingbruin@https://www.wendangku.net/doc/af14218965.html,).
S.Sun,H.Jia,P.Shea,and Z.J.Shen are with the School of Electrical Engineering and Computer Science,University of Central Florida,Orlando, FL328162362USA(e-mail:ssun@https://www.wendangku.net/doc/af14218965.html,;cnjhw99@https://www.wendangku.net/doc/af14218965.html,; pshea@https://www.wendangku.net/doc/af14218965.html,;johnshen@https://www.wendangku.net/doc/af14218965.html,).
Color versions of one or more of the?gures in this paper are available online at https://www.wendangku.net/doc/af14218965.html,.
Digital Object Identi?er
10.1109/TPEL.2008.2006567
Fig.1.Typical switching circuit of a power MOSFET with an inductive
load.
Fig.2.Typical switching waveforms of a power MOSFET with an inductive
load.
trode parasitic capacitances C GS,C GD,and C DS of the power
MOSFET are also labeled in Fig.1.Fig.2shows the simpli?ed
switching waveforms of the power MOSFET in this switching
circuit.In Fig.2,v D and i D are the drain-to-source voltage and
current,respectively.
A commonly used formula for estimating the power MOSFET
drain-to-source switching loss P SW is given by
P SW=
1
I D V D(t OFF+t ON)f+
1
C OSS V2
D f(1)
where I D,V D,and f are the load current,bus voltage,and switch-
ing frequency while t ON and t OFF are the power MOSFET turn-ON
and turn-OFF times,respectively.Assuming a linear transition of
i DS and v DS,the?rst term of(1)simply calculates the switching
power loss as the area below i DS and v DS during the transition
periods in Fig.2.The second term of(1)is often referred to
as the output capacitance loss term.The rationale for including
this additional loss term was that the energy stored in the output
capacitance of the power MOSFET during MOSFET turn-OFF
is internally dissipated through the MOS channel in the form of
Joule heating during MOSFET turn-ON,but is not accounted for
by the?rst term of(1).C OSS is the output capacitance of the
power MOSFET and given by
C OSS=C GD+C DS.(2) 0885-8993/$25.00?2009IEEE
The switching times t ON and t OFF are often estimated by
t ON=t OFF=Q SW
I GS
(3)
where I G is the gate drive current and Q SW is the gate switch charge provided in all power MOSFET datasheets.
The method of estimating power MOSFET switching loss based on(1)–(3)is widely accepted in numerous textbooks [1],technical articles[2],application notes[3],and device datasheets[4].However,there are two fundamental questions re-garding the correctness and accuracy of the calculation method. The?rst question is regarding the justi?cation of including the additional output capacitance loss term.The second question is related to the accuracy of the linear approximation of v DS since realistic voltage waveforms of a power MOSFET are highly nonlinear due to its nonlinear capacitive characteristics.
This paper investigates the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach,and subsequently examines the ex-isting switching loss estimation method based on the new phys-ical insights.The misconception and inaccuracy in the existing estimation method are identi?ed and clari?ed.A more accu-rate method of estimating switching loss based on the datasheet information is then introduced,which is validated by a mixed-mode device/circuit simulation approach and measurement data.
II.M ETHODOLOGY
It is generally believed that analytical models of semiconduc-tor devices should always be validated experimentally.In the case of power MOSFET loss analysis,experimental validation can be performed with either electrical or calorimetric power loss measurement techniques.These experimental techniques, however,have several limitations in practice.The direct elec-trical measurement approach is subject to measurement errors introduced by instrument in the sampling and acquisition of voltage and current signals,resulting in inaccurate power loss measurement data[5],[6].The calorimetric technique essen-tially measures the power loss of the circuit dissipated as heat within a measurement chamber[7].This approach does provide more accurate average power loss measurement,but mostly for the whole test circuitry for steady-state circuit operations rather than that of individual components in the circuit.Further-more,undesirable second-order effects in a practical measure-ment setup,such as the freewheeling diode reverse recovery and wiring impedance,can considerably in?uence the measurement result,making it dif?cult to study the individual contributing fac-tors.Most importantly,none of the experimental investigation approaches provide the physical insights of MOSFET switching operation.
Modeling analysis approaches provide an alternative way of investigating power MOSFET performance.Previous works on power MOSFET performance analysis used simple analytical
device models and device parameters,such as R DS(
ON),Q G,and
a set of simple analytical equations for power loss calculation
[2],[8],[9].While these approaches provide a quick?rst-order estimation of converter ef?ciency,its accuracy is inevitably
lim-Fig.3.Numerical power MOSFET model in mixed-mode DESSIS simulation. Note that separate n+source and p-body contacts are used to provide information on the channel and displacement currents.
ited by the approximation and simpli?cation made in the ana-lytical models.Recently,Cavallaro et al.proposed a circuit sim-ulator to estimate buck converter power losses using MOSFET behavior models that were derived from2-D numerical device and process simulation[10].It should be pointed out that the accuracy of converter power losses can be further improved by using a mixed-mode device/circuit simulation approach with numerical MOSFET models being directly incorporated into cir-cuit simulation[11].Furthermore,detailed information on the power loss contributions over a wide range of operating condi-tions can be easily obtained from the mixed-mode simulation. In this paper,we use a physically based mixed device/circuit modeling approach to investigate the power losses of the MOSFETs under different operating conditions.“Virtual”power MOSFETs were?rst built using a2-D numerical de-vice simulation TCAD tool—Device Simulation for Smart Inte-grated Systems(DESSIS)from Synopsis[12]—and then placed into a circuit shown in Fig.3for mixed-mode device/circuit simulation.DESSIS numerically solves the Possion’s equation, and the continuity equations of electron and hole currents self-consistently,using a variety of physical models.It can be used to predict the electrical characteristics of arbitrary2-D or3-D semi-conductor structures under user-speci?ed operating conditions. It also offers SPICE-like circuit simulation capability combined with device numerical modeling capability,and provides a quick and inexpensive way of evaluating and optimizing circuit and device concepts.Unlike analytical or other SPICE models of power MOSFETs,the numerical device model,relying little on approximations or simpli?cations,faithfully represents the be-havior of a realistic power MOSFET,and therefore,proves to be a very powerful tool for our investigation on MOSFET power loss analysis.Furthermore,efforts are made to compare the nu-merical modeling data to electrical measurement data whenever possible to ensure the validity of the models.
III.M ODELING OF A P OWER MOSFET
To conduct a comprehensive study on the switching behav-ior of power MOSFETs,we?rst build a500-V and16-A virtual power MOSFET.In order to accurately reproduce the
XIONG et al.:NEW PHYSICAL INSIGHTS ON POWER MOSFET SWITCHING LOSSES 527
TABLE I
E LECTRICAL P ARAMETERS O
F P OWER
MOSFETs
Fig.4.Capacitance characteristics of the virtual power MOSFET.
behavior of the power MOSFET in actual circuit operation,we have carefully chosen the physical models and model pa-rameters used in DESSIS simulation,such as carrier mobility and carrier lifetime.The MOSFET model is validated by com-paring the measurement parameters of two commercial power MOSFETs (IRFP450from International Recti?er [13]and FQP9N50C from Fairchild Semiconductor [14]).Table I shows the electrical parameter comparison between the virtual power MOSFETs and the two commercial counterparts.Reasonable agreement is observed.Note that little efforts were made to ?ne-tune the geometrical and process parameters of the virtual MOSFET to perfectly match with the commercial MOSFETs.Instead,the intention was to build a realistic yet suf?ciently generic power MOSFET model for the purpose of studying its switching characteristics.
The capacitance characteristics,which strongly in?uence the switching performance of a power MOSFET,are shown in Fig.4to further validate the physical power MOSFET model.The MOSFET’s interelectrode capacitances C GS ,C GD ,and C DS shown in Fig.1are related to C iss ,C rss ,and C OSS by the following equations:
C iss =C GS +C G
D C rss =C GD
C OSS =C DS +C G
D .
(4)
Furthermore,the gate charge characteristic of the virtual power MOSFET,often preferred by circuit designers to esti-
mate device switching times,is shown in Fig.4.The v DS is also plotted in this same ?gure for reference.
IV .R ESULTS AND D ISCUSSION
The switching behavior of the virtual power MOSFET under diode-clamped-inductive load condition is investigated using the mixed-mode simulation setup shown in Fig.3.A set of supply voltages (V D )of 400,200,and 100V ,and load currents (I D )of 16,8,and 4A is selected for the numerical study.A pulsewidth modulation switching frequency of 100kHz is used in the sim-ulation.An ideal freewheeling diode with negligible reverse recovery charge is used in the simulation in order to separate the investigation on switching losses of the power MOSFET from that on diode reverse-recovery-related losses.Note that diode reverse-recovery-related losses can be signi?cant in prac-tical circuits,and should always be considered in the total power loss calculation.Yet for the purpose of our investigation,we can arti?cially decouple the two power loss mechanisms with our mixed-mode modeling method.
Fig.5shows the simulated switching waveforms of the gate voltage,drain current,drain voltage,and internal MOS chan-nel current of the virtual MOSFET with 400-V V D and 8-A I D .These waveforms closely resemble the measured switch-ing waveforms of power MOSFETs widely reported in litera-tures [15].Detailed power loss analysis for various testing con-ditions can be performed based on the simulation results that provide the physical insights of the power MOSFET.A.Output Capacitance C OSS Loss Term
As shown in Fig.3,we have purposely made two separate source metal contacts for the n +source and p-body regions of the virtual MOSFET,respectively.This allows us to monitor the electron channel current from the n +source and the hole displacement current from the p-body individually,which would be impossible to do in actual measurement.Fig.6illustrates the internal MOS channel current i CH and the externally measurable drain-to-source current i DS ,respectively,along with the gate voltage.
It is observed that i CH is identical to i DS (8A in this case)at steady state,as shown in Fig.6.The gate current and p-body dis-placement current are also shown in Fig.6.During the MOSFET turn-ON and turn-OFF transition periods,i CH signi?cantly dif-fers from i DS .The MOS channel conducts a current signi?cantly
528IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.24,NO.2,FEBRUARY
2009
Fig.5.Simulated (a)turn-ON and (b)turn-OFF switching waveforms of the “virtual”power
MOSFET.
Fig.6.Simulated switching waveforms of the virtual power MOSFET.(a)Increased MOS channel current during turn-ON due to C O S S discharging.(b)Reduced MOS channel current during turn-OFF due to C O S S charging.
higher than the load current during turn-ON because of the ad-ditional current coming from the discharging of the output ca-pacitance,as shown in Fig.6(a).It ?rst seems to be appropriate to include the C OSS loss term in (1)since the energy stored in the output capacitance of the power MOSFET during turn-OFF is internally dissipated through the MOS channel in the form of Joule heating during turn-ON ,but is not accounted for by the ?rst term of (1).However,Fig.6(b)clearly shows that the actual i CH is signi?cantly lower than the i DS during turn-OFF because a large percentage of the load current is diverted from the MOS channel to charge the output capacitor.It should be pointed out that the reduction in channel current and Joule heating during turn-OFF is equally unaccounted for by the ?rst term of (1).The MOSFET equivalent circuit with internal capacitances in Fig.1can be used to explain the internal physics of MOSFET switching.When the MOSFET turns OFF ,the total drain cur-rent i DS is split into two current components.The ?rst current component ?ows through channel as i CH .This current gen-erates Joule heat and contributes to the switching power loss.The second current component charges the output capacitance C OSS ,but does not generate any Joule heat.Obviously,the en-ergy stored in the output capacitor should not be accounted as a part of the turn-OFF switching loss.In another words,the ?rst term of (1)overestimates the turn-OFF switching loss.When the MOSFET turns on,the charge stored in C OSS is discharged through the MOS channel.As a result,the actual i CH is com-posed of two current components:i DS and the C OSS discharging current.Both currents generate Joule heat during the turn-ON pe-riod but the discharging current contribution is not accounted for by the ?rst term of (1).In another words,the ?rst term of (1)underestimates the turn-ON switching loss.
This physical insight raises two questions.The ?rst question is if there is a net difference between the overestimated turn-OFF loss and underestimated turn-ON loss by the ?rst term of (1).The second question is if the second term,i.e.,the C OSS loss term,of (1)can be justi?ed to account for this difference.
Table II summarizes the power loss contributions from the C OSS turn-ON discharging and turn-OFF charging processes for a range of operating voltages and currents,based on our mixed-mode device/circuit simulation of the virtual power MOSFET.The power loss contributions are calculated based on the time integral of the product of the simulated drain-to-source volt-age and the net channel current due to C OSS charging or dis-charging (i.e.,the MOS channel current less the i DS ).The net charging/discharging power loss contribution and the calculated C OSS loss using the second term of (1)are also listed in the table
XIONG et al.:NEW PHYSICAL INSIGHTS ON POWER MOSFET SWITCHING LOSSES 529
TABLE II
S IMULATED O UTPUT C APACITOR P OWER L OSS C ONTRIBUTIONS D URING THE
MOSFET T URN -ON AND T URN -
OFF
Fig.7.Experimental setup to verify our hypothesis on power MOSFET C O S S switching loss using an external capacitor between the drain and source of the MOSFET.
for comparison.It is observed that the power loss contributions from the C OSS turn-ON discharging and turn-OFF charging al-most completely cancel each other under all switching voltage and current conditions.The minor difference between them,mainly due to the gate-related power loss,is much smaller than the calculated C OSS loss P4based on the second term of (1).It is hence concluded that the C OSS loss term in (1)cannot be justi?ed.Note that C OSS still has a signi?cant impact on the switching time,and hence,the total switching loss of the power MOSFET in the ?rst term in (1).The switching power loss calculation can be simply given by
P SW =
1
2
I D V D (t OFF +t ON )f.(5)
An experimental setup is built to verify this conclusion as shown in Fig.7.An IRFP450commercial power MOSFET is used in the testing circuit.In order to truly measure the power loss of power MOSFET,no snubber circuit is used in this setup.Unlike in the mixed-mode modeling study,the MOS channel current i CH in this setup cannot be directly measured.Instead,only the drain current i DS of the power MOSFET can be directly measured.We have to add an external capacitor CAP to emulate the effect of C OSS .A 0.22-μF and 1-μF capacitor are used as the CAP,respectively,which are much larger than the internal C OSS of IRFP450of 0.33nF to amplify the effect of C OSS .The bus voltage is set to 100V and the switching frequency at 10kHz.
The output capacitance C OSS loss according to (1/2)C OSS V 2D
f would be additional 11and 50W for the two capacitance
values,
Fig.8.Gate charge characteristics of the power
MOSFET.
Fig.9.Simulated gate voltage and gate current waveforms of the virtual power MOSFET.
respectively.However,the measured total power losses of the IRFP450MOSFET in this setup are 10.3and 13.7W for the two external capacitors,respectively.The difference is much
smaller than the prediction of the (1/2)C OSS V 2
D
f term.This further validates the conclusion from our modelin
g study that the C OSS loss term in (1)is not justi?ed.
B.Linear Approximation of Drain-to-Source Voltage Waveform Equations (1)and (3)both assume linear approximation of both the drain current and voltage waveforms to estimate the switching time t ON and t OFF and the switching power loss.How-ever,MOSFET inner capacitances are highly nonlinear func-tions of interelectrode voltages,as shown in Fig.4.The reverse transfer capacitance C GD of the power MOSFET decreases dra-matically with increasing v DS .As a result,v DS typically demon-strates a two-slope switching waveform,as shown in Fig.8.During the turn-ON period of a power MOSFET,v DS ?rst de-creases quickly to a transition voltage V X ,and then decreases very slowly to the drain-to-source on voltage V D S (O N )[9].V X ,usually much lower than the bus voltage V D ,represents the v DS at which the n-epi layer under the gate oxide changes from depletion to accumulation.
Several gate charge parameters are de?ned in Fig.8.Q 1is the gate charge required to raise the gate voltage to the threshold
530IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.24,NO.2,FEBRUARY2009 voltage of the power MOSFET while Q2de?nes the gate charge
increment needed to further increase the gate voltage to the
Miller plateau voltage V P.In this paper,we de?ne Q3as the
gate charge increment needed for the drain voltage v DS to drop
to the transition voltage V X,and Q4as the gate charge increment
needed for gate voltage further?nishing the Miller plateau.Note
that Q3and Q4are not explicitly speci?ed in the datasheets of
commercial power MOSFETs.Instead,a switching gate charge
parameter Q SW is de?ned as
Q SW=Q2+Q3+Q4(6)
where Q SW is used in(3)to calculate the switching time,which
is subsequently used for switching power loss calculation in(5).
Switching power loss calculation based on the linear approx-
imation of v DS over the period de?ned by Q SW will result in a
gross overestimation since the switching loss contribution dur-
ing the second slope period de?ned by Q4is almost negligible.
From a practical point of view,it is acceptable to neglect the
switching loss contribution after v DS goes below V X.We pro-
pose to de?ne a new effective switching gate charge Q?SW to
estimate switching time as
Q?SW=Q2+Q3.(7)
The effective switching gate charge Q?SW will compensate for
the power loss overestimation due to the linear approximation
of v DS.V X is a very important device parameter for accurate
estimation of the effective switching time.Unfortunately,most
power MOSFET manufacturers do not provide this information
on the datasheets[9].Q SW and Q?SW are54and24nC,respec-
tively,in the virtual power MOSFET that is being investigated.
Furthermore,practical power MOSFET gate driver are volt-
age sources rather than ideal current sources,making it more
dif?cult to estimate I?GS for calculating the switching times t ON
and t OFF using(3).As shown in Fig.9,the gate current?rst
starts with a large spike,then stays nearly constant during the
Miller plateau,and?nally drops to zero with a certain RC time
constant.Brown suggested an approach on calculating the times
related to the three distinct switching phases and then calculat-
ing the t ON and t OFF[16].However,such a calculation method
may be too complicated for practical use.We propose to use
the gate current at the Miller plateau to approximate the average
gate current in(3),which is de?ned as
I?GS=V gs?V P
R g
(8)
where R g is the total gate resistance,including the external gate resistance and internal gate resistance of both the power MOSFET and the gate driver IC while V P is the gate plateau voltage of the MOSFET.
The switching times t ON and t OFF of the power MOSFET can now be estimated by applying(3),(7),and(8).Table III compares the actual switching power loss P1of the virtual MOSFET with the estimated switching loss values of(5)with t ON and t OFF obtained from various approaches.The parameters t ON and t OFF are estimated using the Q SW and Q?SW gate charge parameters in P2and P3,respectively.We also list the power loss estimation P4using the switching times calculated by the
TABLE III
C OMPARISON OF P OWER MOSFET S WITCHING L OSS E STIMATION W ITH Q S W
AND Q?S W P
ARAMETERS
more complicated Brown method[16].P4demonstrated a large error when compared to the actual power loss since a linear v DS transition was assumed in the Brown approach.To isolate the in?uence of the inaccurate linear v DS transition assumption,we substitute Q GD in[16]with Q3in Fig.8to calculate yet another switching loss estimation P5.
Table III clearly shows that switching power loss calculation methods with the linear v DS assumption introduce a large error in P2and P4while the calculation based on the new gate charge parameter Q?SW offers far more accurate estimate in P3 and P5.Our simple method of estimating effective gate current and switching times yields slightly better results than the more complicated Brown method[12].It can be concluded that our proposed method of calculating power MOSFET switching loss, as summarized by(5),(7),and(8),provides a practical and relatively accurate estimate.
V.C ONCLUSION
This paper uses a physically based device modeling approach to analyze power MOSFET switching losses.The switching power loss estimation method widely accepted by the power electronics community is carefully examined based on the new physical insights.The misconception and calculation inaccu-racy in the existing method are identi?ed based on detailed MOS channel current analysis in the physical device model.It is concluded that the widely accepted output capacitance loss term in the existing calculation method is redundant and erro-neous,and the current method of approximating switching times with the power MOSFET gate charge parameters grossly over-estimates the switching power loss.This paper recommends that a new transition voltage parameter V X and a corresponding new switching gate charge parameter Q?SW be speci?ed in all power MOSFET datasheets to facilitate a more accurate estimation on switching times and power losses of power MOSFETs.It should be pointed out that this study did not take into consideration the parasitic inductance effect of the power MOSFET pack-age,which has considerable impact to power MOSFET losses [17]–[19].Our future work will address the effect of the parasitic inductances and their interaction with the parasitic MOSFET capacitances.
XIONG et al.:NEW PHYSICAL INSIGHTS ON POWER MOSFET SWITCHING LOSSES531
R EFERENCES
[1]R.Erickson and D.Maksimovic,Fundamentals of Power Electronics.
New York:Springer-Verlag,2001,pp.92–100.
[2]R.Sodhi,S.Brown,Sr.,and D.Kinzer,“Integrated design environ-
ment for DC/DC converter FET optimization,”in Proc.11th Int.Symp.
Power Semicond.Devices ICs(ISPSD1999),May26–28,pp.241–
244.
[3]M.Melito and G.Belverde,“STripFETTM III and optimal choice of
MOSFETs in high current VRMs,”STMicroelectronics,Geneva,
Switzerland,Appl.Note AN1730,Jul.2003.
[4]International recti?er power MOSFET datasheets(for example,IRF6603
and IRF6604)[Online].Available:https://www.wendangku.net/doc/af14218965.html,
[5] C.Xiao,G.Chen,and W.G.Odendall,“Overview of power loss measure-
ment techniques in power electronics systems,”in Proc.37th IAS Annu.
Meeting,Oct.2002,pp.1352–1359.
[6]G.Cauffet and J.-P.Keradec,“Digital oscilloscope measurements in high-
frequency switching power electronics,”IEEE Trans.Instrum.Meas.,
vol.41,no.6,pp.856–860,Dec.1992.
[7] E.Ritchie,J.K.Pedersen,F.Blaabjerg,and P.Hansen,“Calorimetric
measuring systems,”IEEE Ind.Appl.Mag.,vol.10,no.3,pp.70–78,
May/Jun.2004.
[8] C.S.Mitter,“Device consideration for high current,low voltage syn-
chronous buck regulator(SBR),”in Proc.IEEE Wescon1997,Santa Clara,
CA,pp.281–288.
[9]P.Markowski.(2002).Estimating MOSFET switching losses means
higher performance buck converter,Report on planet analog Web site
[Online].Available:https://www.wendangku.net/doc/af14218965.html,/showArticle?articleID
=12802296
[10] C.Cavallaro,S.Musumeci,R.Pagano,A.Raciti,and K.Shenai,“Anal-
ysis modeling and simulation of low-voltage MOSFETs in synchronous-
recti?er buck-converter applications,”in Proc.29th Annu.Conf.IEEE
Ind.Electron.Soc.2003(IECON),vol.2,Nov.2–6,pp.1697–
1702.
[11]Z.J.Shen,Y.Xiong,X.Cheng,Y.Fu,and P.Kumar,“Power MOSFET
switching loss analysis:A new insight,”in Proc.IEEE IAS Meeting,
Tampa,FL,Oct.2006,pp.1438–1442.
[12]Synopsis Web site[Online].Available:https://www.wendangku.net/doc/af14218965.html,
[13]IRFP450Datasheet[Online].Available:https://www.wendangku.net/doc/af14218965.html,
[14]SFQ9N50C Datasheet[Online].Available:https://www.wendangku.net/doc/af14218965.html,
[15]Q.Zhao and G.Stojcic,“Design considerations for a new generation mid-
voltage power MOSFET technology,”in Proc.Appl.Power Electron.
Conf.Expo.,2005,pp.336–342.
[16]J.Brown,“Modeling the switching performance of a MOSFET in the
high side of a non-isolated buck converter,”IEEE Trans.Power Electron.,
vol.21,no.1,pp.3–10,Jan.2006.
[17]Y.Ren,M.Xu,J.Zhou,and F.C.Lee,“Analytical loss model of power
MOSFET,”IEEE Trans.Power Electron.,vol.21,no.2,pp.310–319,
Mar.2006.
[18]Z.Zhang,W.Eberle,Z.Yang,Y.F.Liu,and P.C.Sen,“Optimal design
of a current source gate driver,”IEEE Trans.Power Electron.,vol.23,
no.2,pp.653–666,Mar.2008.
[19]W.Eberle,Z.Zhang,Y.F.Liu,and P.C.Sen,“A simple switching loss
model for high switching frequency DC–DC converters,”in Proc.IEEE
Appl.Power Electron.Conf.(APEC),Austin,TX,Feb.2008,pp.
36–42.
Yali Xiong(S’07–M’08)received the B.S.and M.S. degrees from Huazhong University of Science and Technology,Wuhan,China,in1998and2001,re-spectively,and the Ph.D.degree from the University of Central Florida,Orlando,FL,in2008,all in elec-trical engineering.
She is currently with International Recti?er Corpo-ration,Temecula,CA.Her current research interests include power electronics and power semiconductor
devices.
Shan Sun(S’06)received the B.S.degree in electri-
cal engineering from Shanghai Jiaotong University,
Shanghai,China,in2005,and the M.S.degree in
electrical engineering in2007from the University of
Central Florida,Orlando,where he is currently work-
ing toward the Ph.D.degree at the School of Electrical
Engineering and Computer Science.
His current research interests include power semi-
conductor devices,power electronics,and strained
SiGe semiconductor
devices.
Hongwei Jia(S’06)received the B.S.degree from
Xi’an Jiaotong University,Shaanxi,China,in1996,
and the M.S.degree from the University of Electronic
Science and Technology,Zhengzhou,China,in2003.
He is currently working toward the Ph.D.degree at
the School of Electrical Engineering and Computer
Science,University of Central Florida,Orlando.
He was with STMicroelectronics between2003
and2004.His current research interests include
power management IC design,power semiconduc-
tor devices,and power
electronics.
Patrick Shea(S’04)received the B.S.and M.S.de-
grees in electrical engineering in2006and2007,re-
spectively,from the University of Central Florida,
Orlando,where he is currently working toward the
Ph.D.degree at the School of Electrical Engineering
and Computer Science.
His current research interests include power semi-
conductor devices,power electronics,and radiation-
hard semiconductor
devices.
Z.John Shen(S’90–M’94–SM’02)received the
B.S.degree from Tsinghua University,Beijing,
China,in1987,and the M.S.and Ph.D.degrees from
Rensselaer Polytechnic Institute,Troy,NY,in1991
and1994,respectively,all in electrical engineering.
Between1994and1999,he held a number of tech-
nical positions including a Senior Principal Staff Sci-
entist with Motorola Semiconductor Products Sector,
Phoenix,AZ.Between1999and2004,he was with
the University of Michigan-Dearborn,Dearborn.In
2004,he joined the University of Central Florida,
Orlando,where he is currently the Director of the Power Semiconductor Re-
search Laboratory,the Associate Director of Florida Power Electronics Cen-
ter,and an Associate Professor of electrical engineering.His current research
interests include power semiconductor devices and ICs,power electronics,au-
tomotive electronics,nanotechnology,and renewable energy systems.He has
authored or coauthored over80journal and referred conference publications.
He holds nine issued and numerous pending U.S.patents.He is the inventor of
the world’s?rst sub-milliohms power MOSFET.
Dr.Shen was a recipient of the2003U.S.National Science Foundation
CAREER Award,the2006Transaction Prize Paper Award of IEEE T RANSAC-TION ON P OWER E LECTRONICS from the IEEE Power Electronics Society,the 2003IEEE Best Automotive Electronics Paper Award from the IEEE Society of
Vehicular Technology,and the1996Motorola Science and Technology Award.
He is currently the Chair of the Technical Committee on Power Semiconduc-
tors of the IEEE Power Electronics Society.He is an Associate Editor of the
IEEE T RANSACTIONS IN P OWER E LECTRONICS.He has also been the Technical
Program Chair of the38th IEEE Power Electronics Specialists Conference in
2007and the1st IEEE Vehicle Power and Propulsion Conference in2005.He
has served on the organizing committees of numerous IEEE conferences and
workshops.