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LMR14030
ZHCSDJ7A–FEBRUARY2015–REVISED APRIL2015 LMR14030SIMPLE SWITCHER?40V3.5A、2.2MHz降压转换器，具有
40μA I Q
1特性3说明
?输入电压范围：4V至40V LMR14030器件是一款具有集成型高侧MOSFET的
40V、3.5A降压稳压器。该器件具有4V至40V的宽? 3.5A持续输出电流
输入电压范围，适用于从工业到汽车各类应用中非稳压?40μA超低工作静态电流
电源的电源调节。该稳压器在休眠模式下的静态电流?90mΩ高侧金属氧化物半导体场效应晶体
(MOSFET)为40μA，非常适合电池供电类系统。并且在关断模式?最短导通时间：75ns下具有1μA的超低电流，可进一步延长电池使用寿?电流模式控制命。该稳压器的可调开关频率范围较宽，这使得效率?可调节开关频率范围：200kHz至2.5MHz或外部元件尺寸能够得到优化。内部环路补偿意味着?与外部时钟频率同步用户不用承担设计环路补偿组件的枯燥工作。并且还?内部补偿方便使用能够以最大限度减少器件的外部元件数。精密使能输?支持高占空比运行入简化了稳压器控制和系统电源排序。此外，该器件?精密使能引脚还内置多种保护特性：逐周期电流限制保护、应对功耗
过大的热感测和热关断保护、以及输出过压保护。?关断电流：1μA
?外部软启动
器件信息(1)
?热保护、过压保护和短路保护
器件型号封装封装尺寸（标称值）?8引脚HSOIC PowerPAD?封装
LMR14030SDDA HSOIC-8 4.89mm x3.90mm
(1)要了解所有可用封装，请见数据表末尾的可订购产品附录。
2应用范围
?汽车电池稳压
?工业用电源
?电信和数据通信系统
?电池供电系统
4简化电路原理图
效率与输出电流间的关系
LMR14030
ZHCSDJ7A–FEBRUARY2015–REVISED https://www.wendangku.net/doc/a614465426.html,
目录
8.1Overview (8)
1特性 (1)
8.2Functional Block Diagram (8)
2应用范围 (1)
8.3Feature Description (9)
3说明 (1)
9Application and Implementation (15)
4简化电路原理图 (1)
9.1Application Information (15)
5修订历史记录 (2)
9.2Typical Application (15)
6Pin Configuration and Functions (3)
10Power Supply Recommendations (21)
7Specifications (4)
11Layout (21)
7.1Absolute Maximum Ratings (4)
11.1Layout Guidelines (21)
7.2ESD Ratings (4)
11.2Layout Example (22)
7.3Recommended Operating Conditions (4)
12器件和文档支持 (23)
7.4Thermal Information (4)
12.1商标 (23)
7.5Electrical Characteristics (5)
12.2静电放电警告 (23)
7.6Switching Characteristics (5)
12.3术语表 (23)
7.7Typical Characteristics (6)
13机械封装和可订购信息 (23)
8Detailed Description (8)
5修订历史记录
Changes from Original(February2015)to Revision A Page ?已更改“产品预览”至“量产数据”。 (1)
FB
SS
BOOT VIN
EN
HSOIC PACKAGE
(TOP VIEW)
LMR14030
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6Pin Configuration and Functions
HSOIC
8-Pin
Top View
Pin Functions
PIN
TYPE (1)DESCRIPTION NAME
NO.BOOT
1O Bootstrap capacitor connection for high-side MOSFET driver.Connect a high quality 0.1μF capacitor from BOOT to SW.VIN
2I Connect to power supply and bypass capacitors C IN .Path from VIN pin to high frequency bypass C IN and GND must be as short as possible.EN 3I Enable pin,with internal pull-up current source.Pull below 1.2V to disable.Float or connect
to VIN to enable.Adjust the input under voltage lockout with two resistors.See the Enable
and Adjusting Under voltage lockout section.
RT/SYNC 4I Resistor Timing or External Clock input.An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency.If the pin is pulled
above the PLL upper threshold,a mode change occurs and the pin becomes a
synchronization input.The internal amplifier is disabled and the pin is a high impedance clock
input to the internal PLL.If clocking edges stop,the internal amplifier is re-enabled and the
operating mode returns to frequency programming by resistor.
FB 5I Feedback input pin,connect to the feedback divider to set V OUT .Do not short this pin to
ground during operation.
SS 6O Soft-start control pin.Connect to a capacitor to set soft-start time.
GND 7G System ground pin.
SW 8O Switching output of the regulator.Internally connected to high-side power MOSFET.Connect
to power inductor.
Thermal Pad
9G Major heat dissipation path of the die.Must be connected to ground plane on PCB.(1)I =Input,O =Output,G =Ground
LMR14030
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7Specifications
7.1Absolute Maximum Ratings
over operating free-air temperature range(unless otherwise noted)(1)
MIN MAX UNIT
VIN,EN to GND-0.344
BOOT to GND-0.349
Input Voltages SS to GND-0.35V
FB to GND-0.37
RT/SYNC to GND-0.3 3.6
BOOT to SW 6.5
Output Voltages V
SW to GND-344
T J Junction temperature-40150°C
T stg Storage temperature-65150°C (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings
only,which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2ESD Ratings
PARAMETER DEFINITION VALUE UNIT
Human body model(HBM)(1)2
Electrostatic
V(ESD)kV discharge Charged device model(CDM)(2)0.5
(1)JEDEC document JEP155states that500-V HBM allows safe manufacturing with a standard ESD control process.
(2)JEDEC document JEP157states that250-V CDM allows safe manufacturing with a standard ESD control process.
7.3Recommended Operating Conditions
over operating free-air temperature range(unless otherwise noted)
MIN MAX UNIT VIN440
VOUT0.828
Buck Regulator BOOT45V
SW-140
FB05
EN040
Control RT/SYNC0 3.3V
SS03
Switching frequency range at RT mode2002500
Frequency kHz
Switching frequency range at SYNC mode2502300
Temperature Operating junction temperature,T J-40125°C
7.4Thermal Information
DDA
THERMAL METRIC(1)UNIT
8PINS
RθJA Junction-to-ambient thermal resistance42.5
ψJT Junction-to-top characterization parameter9.9
ψJB Junction-to-board characterization parameter25.4
°C/W
RθJC(top)Junction-to-case(top)thermal resistance56.1
RθJC(bot)Junction-to-case(bottom)thermal resistance 3.8
RθJB Junction-to-board thermal resistance25.5
(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.
LMR14030 https://www.wendangku.net/doc/a614465426.html, ZHCSDJ7A–FEBRUARY2015–REVISED APRIL2015
7.5Electrical Characteristics
Limits apply over the recommended operating junction temperature(T J)range of-40°C to+125°C,unless otherwise stated. Minimum and Maximum limits are specified through test,design or statistical correlation.Typical values represent the most likely parametric norm at T J=25°C,and are provided for reference purposes only.Unless otherwise specified,the following conditions apply:V IN=4.0V to40V
PARAMETER TEST CONDITION MIN TYP MAX UNIT POWER SUPPLY(VIN PIN)
V IN Operation input voltage440V UVLO Under voltage lockout thresholds Rising threshold 3.5 3.7 3.9V
Hysteresis285mV I SHDN Shutdown supply current V EN=0V,T A=25°C,4.0V≤V IN≤40V 1.0 3.0μA I Q Operating quiescent current(non-V FB=1.0V,T A=25°C40μA
switching)
ENABLE(EN PIN)
V EN_TH EN Threshold Voltage 1.05 1.20 1.38V
I EN_PIN EN PIN current Enable threshold+50mV-4.6
μA
Enable threshold-50mV-1.0
I EN_HYS EN hysteresis current-3.6μA EXTERNAL SOFT-START
I SS SS pin current T A=25°C3μA VOLTAGE REFERENCE(FB PIN)
V FB Feedback voltage T J=25°C0.7440.7500.756V
T J=-40°C to125°C0.7350.7500.765V HIGH-SIDE MOSFET
R DS_ON On-resistance V IN=12V,BOOT to SW=5.8V90180m?High-side MOSFET CURRENT LIMIT
I LIMT Current limit V IN=12V,T A=25°C,Open Loop 4.4 5.5 6.6A THERMAL PERFORMANCE
T SHDN Thermal shutdown threshold170
°C T HYS Hysteresis12
7.6Switching Characteristics
over operating free-air temperature range(unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT f SW Switching frequency R T=49.9k?,1%accuracy400500600kHz
V SYNC_HI SYNC clock high level threshold 1.7
V
V SYNC_LO SYNC clock low level threshold0.5
T SYNC_MIN Minimum SYNC input pulse width Measured at500kHz,V SYNC_HI>3V,30ns
V SYNC_LO<0.3V
T LOCK_IN PLL lock in time Measured at500kHz100μs
T ON_MIN Minimum controllable on time V IN=12V,BOOT to SW=5.8V,I Load=75ns
1A
D MAX Maximum duty cycle f SW=200kHz97%
LMR14030
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7.7Typical Characteristics
Unless otherwise specified the following conditions apply:V IN=12V,f SW=500kHz,L=5.6μH,C OUT=47μF x2,T A=
25°C.
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Typical Characteristics(continued)
Unless otherwise specified the following conditions apply:V IN=12V,f SW=500kHz,L=5.6μH,C OUT=47μF x2,T A=
FB VIN
GND EN BOOT
SS RT/SYNC
SW
LMR14030
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8Detailed Description
8.1Overview
The LMR14030SIMPLE SWITCHER ?regulator is an easy to use step-down DC-DC converter that operates
from 4.0V to 40V supply voltage.It integrates a 90m Ω(typical)high-side MOSFET,and is capable of delivering
up to 3.5A DC load current with exceptional efficiency and thermal performance in a very small solution size.
The operating current is typically 40μA under no load condition (not switching).When the device is disabled,the
supply current is typically 1μA.An extended family is available in 2A and 5A load options in pin to pin
compatible packages.
The LMR14030implements constant frequency peak current mode control with Sleep-mode at light load to
achieve high efficiency.The device is internally compensated,which reduces design time,and requires fewer
external components.The switching frequency is programmable from 200kHz to 2.5MHz by an external resistor
R T .The LMR14030is also capable of synchronization to an external clock within the 250kHz to 2.3MHz
frequency range,which allows the device to be optimized to fit small board space at higher frequency,or high
efficient power conversion at lower frequency.
Other optional features are included for more comprehensive system requirements,including precision enable,
adjustable soft-start time,and approximate 97%duty cycle by BOOT capacitor recharge circuit.These features
provide a flexible and easy to use platform for a wide range of applications.Protection features include over
temperature shutdown,V OUT over voltage protection (OVP),V IN under-voltage lockout (UVLO),cycle-by-cycle
current limit,and short-circuit protection with frequency fold-back.
8.2Functional Block Diagram
V
-V 0
S W V o l t a g e i I 0
I n d u c t o r C u r r e n t I LMR14030
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8.3Feature Description
8.3.1Fixed Frequency Peak Current Mode Control
The following operation description of the LMR14030will refer to the Function Block Diagram and to the
waveforms in Figure 13.LMR14030output voltage is regulated by turning on the high-side N-MOSFET with
controlled ON time.During high-side switch ON time,the SW pin voltage swings up to approximately V IN ,and the
inductor current i L increase with linear slope (V IN –V OUT )/L.When high-side switch is off,inductor current
discharges through freewheel diode with a slope of –V OUT /L.The control parameter of Buck converter is defined
as Duty Cycle D =t ON /T SW ,where t ON is the high-side switch ON time and T SW is the switching period.The
regulator control loop maintains a constant output voltage by adjusting the duty cycle D.In an ideal Buck
converter,where losses are ignored,D is proportional to the output voltage and inversely proportional to the input
voltage:D =V OUT /V IN .
Figure 13.SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LMR14030employs fixed frequency peak current mode control.A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset.The peak
inductor current is sensed from the high-side switch and compared to the peak current to control the ON time of
the high-side switch.The voltage feedback loop is internally compensated,which allows for fewer external
components,makes it easy to design,and provides stable operation with almost any combination of output
capacitors.The regulator operates with fixed switching frequency at normal load condition.At very light load,the
LMR14030will operate in Sleep-mode to maintain high efficiency and the switching frequency will decrease with
reduced load current.
8.3.2Slope Compensation
The LMR14030adds a compensating ramp to the MOSFET switch current sense signal.This slope
compensation prevents sub-harmonic oscillations at duty cycle greater than 50%.The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
8.3.3Sleep-mode
The LMR14030operates in Sleep-mode at light load currents to improve efficiency by reducing switching and
gate drive losses.If the output voltage is within regulation and the peak switch current at the end of any
switching cycle is below the current threshold of 300mA,the device enters Sleep-mode.The Sleep-mode current
threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400mV.
When in Sleep-mode,the internal COMP voltage is clamped at 400mV and the high-side MOSFET is inhibited,
and the device draws only 40μA (typical)input quiescent current.Since the device is not switching,the output
voltage begins to decay.The voltage control loop responds to the falling output voltage by increasing the internal
COMP voltage.The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal
COMP voltage above 400mV.The output voltage recovers to the regulated value,and internal COMP voltage
eventually falls below the Sleep-mode threshold at which time the device again enters Sleep-mode.
OUT FBT FBB V 0.75R R 0.75
LMR14030
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Feature Description (continued)
8.3.4Low Dropout Operation and Bootstrap Voltage (BOOT)
The LMR14030provides an integrated bootstrap voltage regulator.A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET.The BOOT capacitor is refreshed when the
high-side MOSFET is off and the external low side diode conducts.The recommended value of the BOOT
capacitor is 0.1μF.A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output,the high-side MOSFET of the LMR14030will
operate at approximate 97%duty cycle.When the high-side MOSFET is continuously on for 5or 6switching
cycles (5or 6switching cycles for frequency lower than 1MHz,and 10or 11switching cycles for frequency
higher than 1MHz)and the voltage from BOOT to SW drops below 3.2V,the high-side MOSFET is turned off
and an integrated low side MOSFET pulls SW low to recharge the BOOT capacitor.
Since the gate drive current sourced from the BOOT capacitor is small,the high-side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor.Thus the effective duty cycle of
the switching regulator can be high,approaching 97%.The effective duty cycle of the converter during dropout is
mainly influenced by the voltage drops across the power MOSFET,the inductor resistance,the low side diode
voltage and the printed circuit board resistance.
8.3.5Adjustable Output Voltage
The internal voltage reference produces a precise 0.75V (typical)voltage reference over the operating
temperature.The output voltage is set by a resistor divider from output voltage to the FB pin.It is recommended
to use 1%tolerance or better and temperature coefficient of 100ppm or lower divider resistors.Select the low
side resistor R FBB for the desired divider current and use Equation 1to calculate high-side R FBT .Larger value
divider resistors are good for efficiency at light load.However,if the values are too high,the regulator will be
more susceptible to noise and voltage errors from the FB input current may become noticeable.R FBB in the
range from 10k ?to 100k ?is recommended for most applications.
Figure 14.Output Voltage Setting
(1)
8.3.6Enable and Adjustable Under-voltage Lockout
The LMR14030is enabled when the VIN pin voltage rises above 3.7V (typical)and the EN pin voltage exceeds
the enable threshold of 1.2V (typical).The LMR14030is disabled when the VIN pin voltage falls below 3.52V
(typical)or when the EN pin voltage is below 1.2V.The EN pin has an internal pull-up current source (typically
I EN =1μA)that enables operation of the LMR14030when the EN pin is floating.
Many applications will benefit from the employment of an enable divider R ENT and R ENB in Figure 15to establish
a precision system UVLO level for the stage.System UVLO can be used for supplies operating from utility power
as well as battery power.It can be used for sequencing,ensuring reliable operation,or supply protection,such
as a battery.An external logic signal can also be used to drive EN input for system sequencing and protection.
When EN terminal voltage exceeds 1.2V,an additional hysteresis current (typically I HYS =3.6μA)is sourced out
of EN terminal.When the EN terminal is pulled below 1.2V,I HYS current is removed.This additional current
facilitates adjustable input voltage UVLO https://www.wendangku.net/doc/a614465426.html,e Equation 2and Equation 3to calculate R ENT and R ENB for desired UVLO hysteresis voltage.
S T 1.045W | N+] R (k )32537 : u SS
REF SS SS C (nF)V (V)t (ms)I (A)K 2EN
ENB START EN EN ENT V R V V I R START STOP
ENT HYS V V R I
LMR14030
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Feature Description (continued)
Figure 15.System UVLO By Enable Dividers
(2)
(3)
where V START is the desired voltage threshold to enable LMR14030,V STOP is the desired voltage threshold to
disable device.
8.3.7External Soft-start
The LMR14030has soft-start pin for programmable output ramp up time.The soft-start feature is used to prevent
inrush current impacting the LMR14030and its load when power is first applied.The soft-start time can be
programed by connecting an external capacitor C SS from SS pin to GND.An internal current source (typically I SS =3μA)charges C SS and generates a ramp from 0V to V REF .The soft-start time can be calculated by
Equation 4:
(4)
The internal soft-start resets while device is disabled or in thermal shutdown.
8.3.8Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the LMR14030can be programmed by the resistor R T from the RT/SYNC pin and
GND pin.The RT/SYNC pin can’t be left floating or shorted to ground.To determine the timing resistance for a
given switching frequency,use Equation 5or the curve in Figure 16.Table 1gives typical R T values for a given
f SW .
(5)
Hi-Z
Clock
Source Lo-Z Clock Source
LMR14030
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Feature Description (continued)
Figure 16.R T vs Frequency Curve
Table 1.Typical Frequency Setting R T Resistance
f SW (kHz)
R T (k ?)200
127350
71.5500
49.9750
32.41000
23.71500
15.82000
11.5220010.5
The LMR14030switching action can also be synchronized to an external clock from 250kHz to 2.3MHz.
Connect a square wave to the RT/SYNC pin through either circuit network shown in Figure 17.Internal oscillator
is synchronized by the falling edge of external clock.The recommendations for the external clock include:high
level no lower than 1.7V,low level no higher than 0.5V and have a pulse width greater than 30ns.When using
a low impedance signal source,the frequency setting resistor R T is connected in parallel with an AC coupling
capacitor C COUP to a termination resistor R TERM (e.g.,50Ω).The two resistors in series provide the default
frequency setting resistance when the signal source is turned off.A 10pF ceramic capacitor can be used for
C COUP .Figure 18,Figure 19and Figure 20show the device synchronized to an external system clock.
Figure 17.Synchronizing to an External Clock
OUT IND OUT D ON IN_MAX OUT DS_O SW(ma N D x)I R V V 1t |V I R V §·u u ¨?¨? u ?1iL (500 mA/DIV)
SW (5 V/DIV)
SYNC (2 V/DIV)
iL (1 A/DIV)
SW (5 V/DIV)SYNC (2 V/DIV)iL (500 mA/DIV)
SW (5 V/DIV)
SYNC (2 V/DIV)
LMR14030
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Equation 6calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio.Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
(6)
where
?I OUT =Output current
?R IND =Inductor series resistance
?V IN_MAX =Maximum input voltage
?V OUT =Output voltage
?V D =Diode voltage drop
?R DS_ON =High-side MOSFET switch on resistance
?t ON =Minimum on time
8.3.9Over Current and Short Circuit Protection
The LMR14030is protected from over current condition by cycle-by-cycle current limiting on the peak current of
the high-side MOSFET.High-side MOSFET over-current protection is implemented by the nature of the Peak
Current Mode control.The high-side switch current is compared to the output of the Error Amplifier (EA)minus
slope compensation every switching cycle.Please refer to Functional Block Diagram for more details.The peak
current of high-side switch is limited by a clamped maximum peak current threshold which is constant.So the
peak current limit of the high-side switch is not affected by the slope compensation and remains constant over
the full duty cycle range.
LMR14030
ZHCSDJ7A–FEBRUARY2015–REVISED https://www.wendangku.net/doc/a614465426.html, The LMR14030also implements a frequency fold-back to protect the converter in severe over-current or short conditions.The oscillator frequency is divided by2,4,and8as the FB pin voltage decrease to75%,50%,25% of V REF.The frequency fold-back increases the off time by increasing the period of the switching cycle,so that it provides more time for the inductor current to ramp down and leads to a lower average inductor current.Lower frequency also means lower switching loss.Frequency fold-back reduces power dissipation and prevents overheating and potential damage to the device.
8.3.10Overvoltage Protection
The LMR14030employs an output overvoltage protection(OVP)circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low output capacitance.The OVP feature minimizes output overshoot by turning off high-side switch immediately when FB voltage reaches to the rising OVP threshold which is nominally109%of the internal voltage reference V REF.When the FB voltage drops below the falling OVP threshold which is nominally107%of V REF,the high-side MOSFET resumes normal operation.
8.3.11Thermal Shutdown
The LMR14030provides an internal thermal shutdown to protect the device when the junction temperature exceeds170°C(typical).The high-side MOSFET stops switching when thermal shundown activates.Once the die temperature falls below158°C(typical),the device reinitiates the power up sequence controlled by the internal soft-start circuitry.
R T
C IN FBT
FBB
LMR14030
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9Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification,and TI does not warrant its accuracy or completeness.TI’s customers are
responsible for determining suitability of components for their purposes.Customers should
validate and test their design implementation to confirm system functionality.
9.1Application Information
The LMR14030is a step down DC-to-DC regulator.It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 3.5A.The following design procedure can be used to select
components for the LMR14030.This section presents a simplified discussion of the design process.
9.2Typical Application
The LMR14030only requires a few external components to convert from wide voltage range supply to a fixed
output voltage.A schematic of 5V/3.5A application circuit is shown in Figure 21.The external components have
to fulfill the needs of the application,but also the stability criteria of the device’s control loop.
Figure 21.Application Circuit,5V Output
9.2.1Design Requirements
This example details the design of a high frequency switching regulator using ceramic output capacitors.A few
parameters must be known in order to start the design process.These parameters are typically determined at the
system level:
Input Voltage,V IN
7V to 36V,Typical 12V Output Voltage,V OUT
5.0V Maximum Output Current I O_MAX
3.5A Transient Response 0.35A to 3.5A
5%Output Voltage Ripple
50mV Input Voltage Ripple
400mV Switching Frequency f SW
500kHz Soft-start time 5ms
IND OUT SW OUT S L OUT OUT
_W C K I C C 8|i |V 8K K K K K OUT_ESR L IND OUT V i ESR K I ESR K K K IN_MAX OUT
OUT MIN OUT IN SW D IN_MAX V V V L I |K V K K K OUT IN_MAX OUT L IN _MAX SW V (V V )V |i L K K K S T 1.045W | N+] R (k )32537 : u OUT FBT FBB V 0.75R R 0.75 LMR14030
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9.2.2Detailed Design Procedure
9.2.2.1Output Voltage Set-Point
The output voltage of LMR14030is externally adjustable using a resistor divider network.The divider network is
comprised of top feedback resistor R FBT and bottom feedback resistor R FBB .Equation 7is used to determine the
output voltage:
(7)
Choose the value of R FBT to be 100k ?.With the desired output voltage set to 5V and the V FB =0.75V,the R FBB value can then be calculated using Equation 7.The formula yields to a value 17.65k ?.Choose the closest
available value of 17.8k ?for R FBB .
9.2.2.2Switching Frequency
For desired frequency,use Equation 8to calculate the required value for R T .
(8)
For 500kHz,the calculated R T is 49.2k ?and standard value 49.9k ?can be used to set the switching
frequency at 500kHz.
9.2.2.3Output Inductor Selection
The most critical parameters for the inductor are the inductance,saturation current and the RMS current.The
inductance is based on the desired peak-to-peak ripple current Δi L .Since the ripple current increases with the
input voltage,the maximum input voltage is always used to calculate the minimum inductance L MIN .Use
Equation 10to calculate the minimum value of the output inductor.K IND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current.A reasonable value of K IND should be
20%-40%.During an instantaneous short or over current operation event,the RMS and peak inductor current
can be high.The inductor current rating should be higher than current limit.
(9)
(10)
In general,it is preferable to choose lower inductance in switching power supplies,because it usually
corresponds to faster transient response,smaller DCR,and reduced size for more compact designs.But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely trigged.It also generates more conduction loss since the RMS current is slightly higher.
Larger inductor current ripple also implies larger output voltage ripple with same output capacitors.With peak
current mode control,it is not recommended to have too small of an inductor current ripple.A larger peak current
ripple improves the comparator signal to noise ratio.
For this design example,choose K IND =0.4,the minimum inductor value is calculated to be 6.12μH,and a
nearest standard value is chosen:6.5μH.A standard 6.5μH ferrite inductor with a capability of 5A RMS current
and 7A saturation current can be used.
9.2.2.4Output Capacitor Selection
The output capacitor(s),C OUT ,should be chosen with care since it directly affects the steady state output voltage
ripple,loop stability and the voltage over/undershoot during load current transients.
The output ripple is essentially composed of two parts.One is caused by the inductor current ripple going
through the Equivalent Series Resistance (ESR)of the output capacitors:
(11)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
(12)
22OUT 22OS OUT OH OL
OUT I I C (V V )V L !u OH OL O SW U US T 3(I I )C |9K K LMR14030
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The two components in the voltage ripple are not in phase,so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate.When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The regulator’s control loop usually needs three or more clock cycles to respond to the output voltage droop.The
output capacitance must be large enough to supply the current difference for three clock cycles to maintain the
output voltage within the specified range.Equation 13
Equation 13shows the minimum output capacitance needed for specified output undershoot.When a sudden
large load decrease happens,the output capacitors absorb energy stored in the inductor.The catch diode can’t
sink current so the energy stored in the inductor results in an output voltage overshoot.Equation 14calculates
the minimum capacitance required to keep the voltage overshoot within a specified range.
(13)
(14)
where
?K IND =Ripple ratio of the inductor ripple current (Δi L /I OUT )
?I OL =Low level output current during load transient
?I OH =High level output current during load transient
?V US =Target output voltage undershoot
?V OS =Target output voltage overshoot
For this design example,the target output ripple is 50mV.Presuppose ΔV OUT_ESR =ΔV OUT_C =50mV,and
chose K IND =0.4.Equation 11yields ESR no larger than 35.7m ?and Equation 12yields C OUT no smaller than 7
μF.For the target over/undershoot range of this design,V US =V OS =5%×V OUT =250mV.The C OUT can be
calculated to be no smaller than 75.6μF and 30.8μF by Equation 13and Equation 14respectively.In summary,
the most stringent criteria for the output capacitor is 75.6μF.Two 47μF,16V,X7R ceramic capacitors with 5
m ?ESR are used in parallel.
9.2.2.5Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25%higher than the maximum input voltage.The
current rating for the diode should be equal to the maximum output current for best reliability in most
applications.In cases where the input voltage is much greater than the output voltage the average diode current
is lower.In this case it is possible to use a diode with a lower average current rating,approximately (1-D)×I OUT however the peak current rating should be higher than the maximum load current.A 4A to 5A rated diode is a
good starting point.
9.2.2.6Input Capacitor Selection
The LMR14030device requires high frequency input decoupling capacitor(s)and a bulk input capacitor,
depending on the application.The typical recommended value for the high frequency decoupling capacitor is 4.7
μF to 10μF.A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is recommended.
To compensate the derating of ceramic capacitors,a voltage rating of twice the maximum input voltage is
recommended.Additionally,some bulk capacitance can be required,especially if the LMR14030circuit is not
located within approximately 5cm from the input voltage source.This capacitor is used to provide damping to the
voltage spike due to the lead inductance of the cable or the trace.For this design,two 2.2μF,X7R ceramic
capacitors rated for 100V are used.A 0.1μF for high-frequency filtering and place it as close as possible to the
device pins.
9.2.2.7Bootstrap Capacitor Selection
Every LMR14030design requires a bootstrap capacitor (C BOOT ).The recommended capacitor is 0.1μF and rated
16V or higher.The bootstrap capacitor is located between the SW pin and the BOOT pin.The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
SS
SS SS REF t (ms)I (A)C (nF)V (V)
K 2 LMR14030
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9.2.2.8Soft-start Capacitor Selection
Use Equation 15in order to calculate the soft-start capacitor value:
(15)
where
?C SS =Soft-start capacitor value
?I SS =Soft-start charging current (3μA)
?t SS =Desired soft-start time
For the desired soft-start time of 5ms and soft-start charging current of 3.0μA,Equation 15yields a soft-start
capacitor value of 20nF,a standard 22nF ceramic capacitor is used.
iL (500 mA/DIV)
VOUT(ac) (10 mV/DIV)SW (5 V/DIV)
VOUT(ac) (200 mV/DIV)
IOUT (1 A/DIV)
iL (200 mA/DIV)
VOUT(ac) (10 mV/DIV)
SW (5 V/DIV)iL (200 mA/DIV)
VOUT(ac) (10 mV/DIV)
SW (5 V/DIV)
VOUT (1 V/DIV)EN (1 V/DIV)
VIN (5 V/DIV)
iL (2 A/DIV)
VOUT (1 V/DIV)
VIN (5 V/DIV)
LMR14030
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9.2.3Application Curves
Unless otherwise specified the following conditions apply:V IN =12V,f SW =500kHz,L =5.6μH,C OUT =47μF x 2,T A =
25°C.
LMR14030
ZHCSDJ7A–FEBRUARY2015–REVISED https://www.wendangku.net/doc/a614465426.html, Unless otherwise specified the following conditions apply:V IN=12V,f SW=500kHz,L=5.6μH,C OUT=47μF x2,T A=
VOUT (1 V/DIV)
VOUT (1 V/DIV)
iL (2 A/DIV)
iL (2 A/DIV)