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Preliminary Rev. 0.4 5/06Copyright ? 2006 by Silicon Laboratories Si530/531

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si530/531

C R Y S TA L O S C I L L A T O R (XO)(10MH Z T O 1.4GH Z )

Features

Applications

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL ?

circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available with any-rate output frequency from 10 to 945MHz and select frequencies to 1400MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition,DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage,output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators.

Functional Block Diagram

Available with any-rate output frequencies from 10MHz to 945MHz and select frequencies to 1.4GHz

3rd generation DSPLL ? with superior jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency ensures high reliability and low aging

Available CMOS, LVPECL, LVDS, and CML outputs

3.3, 2.5, and 1.8V supply options Industry-standard 5x 7mm package and pinout

Pb-free/RoHS-compliant

SONET/SDH Networking SD/HD video

Clock and data recovery

FPGA/ASIC clock generation

Ordering Information:

See page 6.

Si5602

P R E L I M I N A R Y D A TA S H E E T

Si530/531

2Preliminary Rev. 0.4

Si530/531

Preliminary Rev. 0.4

3

500 MHz

φJ 12kHz to 20MHz (OC-48)50kHz to 80MHz (OC-192)——0.270.30——ps Phase Jitter (RMS)*

for F OUT of 125 to 500MHz

φJ

12kHz to 20MHz (OC-48)

—

0.50

—

ps

*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.

Table 5. CLK± Output Period Jitter

Parameter

Symbol Test Condition

Min Typ Max Units Period Jitter*

for F OUT < 160MHz

J PER

RMS —1—ps

Peak-to-Peak

—

5

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N =1000 cycles.

Si530/531

4Preliminary Rev. 0.4

Si530/531

Preliminary Rev. 0.4

5

(Top View)

Si530

LVDS/LVPECL/CML

Si530CMOS

Si531

LVDS/LVPECL/CML

Si530/531

6

Preliminary Rev. 0.4

Si530/531

Preliminary Rev. 0.47

Si530/531

8Preliminary Rev. 0.4

Si530/531

Preliminary Rev. 0.49

Si530/531

10

Preliminary Rev. 0.4

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.