ADE7878
Polyphase Multifunction Energy Metering IC
with per Phase Active and Reactive Powers
ADE7878 Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 https://www.wendangku.net/doc/b1785867.html, Fax: 781.461.3113 ?2010 Analog Devices, Inc. All rights reserved.
FEATURES
Highly accurate; supports EN 50470-1, EN 50470-3,
IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards Compatible with 3-phase, 3- or 4-wire (delta or wye), and other 3-phase services
Supplies total (fundamental and harmonic) active/reactive/ apparent energy and fundamental active/reactive energy on each phase and on the overall system
Less than 0.1% error in active and reactive energy over a dynamic range of 1000 to 1 at T A = 25°C
Less than 0.2% error in active and reactive energy over a dynamic range of 3000 to 1 at T A = 25°C
Supports current transformer and di/dt current sensors Dedicated ADC channel for neutral current input
Less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at T A = 25°C
Supplies sampled waveform data on all three phases and on neutral current
Selectable no load threshold levels for total and fundamental active and reactive powers, as well as for apparent powers
Low power battery mode monitors phase currents for antitampering detection
Battery supply input for missing neutral operation
Phase angle measurements in both current and voltage channels with a typical 0.3° error
Wide-supply voltage operation: 2.4 V to 3.7 V Reference: 1.2 V (drift 10 ppm/°C typical) with external overdrive capability
Single 3.3 V supply
40-lead lead frame chip scale package (LFCSP), Pb-free Operating temperature: ?40° to +85°C
Flexible I2C, SPI, and HSDC serial interfaces APPLICATIONS
Energy metering systems GENERAL DESCRIPTION
The ADE78781 is a high accuracy, 3-phase electrical energy measurement IC with serial interfaces and three flexible pulse outputs. The ADE7878 incorporates second-order sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), a digital integrator, reference circuitry, and all the signal processing required to perform total (fundamental and harmonic) active, reactive, and apparent energy measurement and rms calculations, as well as fundamental only active and reactive energy measurement and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The DSP program is stored into internal ROM memory.
The ADE7878 is suitable for measuring active, reactive, and apparent energy in various 3-phase configurations, such as wye or delta services, with both three and four wires. The ADE7878 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2, and CF3 logic outputs provide a wide choice of power information: total active, reactive, and apparent powers, or the sum of the current rms values, and fundamental active and reactive powers.
The ADE7878 contains waveform sample registers that allow access to all ADC outputs. The device also incorporates power quality measurements, such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement, and angles between phase voltages and currents. Two serial interfaces, SPI and I2C, can be used to communicate with the ADE7878. A dedicated high speed interface, the high speed data capture (HSDC) port, can be used in conjunction with I2C to provide access to the ADC outputs and real-time power information. The ADE7878 also has two interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled interrupt event has occurred. For the ADE7878, three specially designed low power modes ensure the continuity of energy accumulation when the ADE7878 is in a tampering situation.
The ADE7878 is available in a 40-lead LFCSP, Pb-free package.
1 U.S. patents pending.
ADE7878
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TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings .......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 14 Test Circuit ...................................................................................... 17 Terminology .................................................................................... 18 Power Management ........................................................................ 19 PSM0—Normal Power Mode ................................................... 19 PSM1—Reduced Power Mode.................................................. 19 PSM2—Low Power Mode ......................................................... 19 PSM3—Sleep Mode .................................................................... 20 Power-Up Procedure .................................................................. 20 Hardware Reset ........................................................................... 21 Software Reset Functionality .................................................... 21 Theory of Operation ...................................................................... 24 Analog Inputs .............................................................................. 24 Analog-to-Digital Conversion .................................................. 24 Antialiasing Filter ................................................................... 25 ADC Transfer Function ......................................................... 25 Current Channel ADC ............................................................... 25 Current Waveform Gain Registers ....................................... 26 Current Channel HPF ........................................................... 26 Current Channel Sampling ................................................... 27 di/dt Curent Sensor and Digital Integrator ............................. 27 Voltage Channel ADC ................................................................ 28 Voltage Waveform Gain Registers ........................................ 28 Voltage Channel HPF ............................................................ 28 Voltage Channel Sampling .................................................... 28 Changing Phase Voltage Datapath ........................................... 29 Power Quality Measurements (29)
Zero Crossing Detection ....................................................... 29 Zero-Crossing Timeout ......................................................... 30 Phase Sequence Detection .................................................... 30 Time Interval Between Phases ............................................. 31 Period Measurement .............................................................. 32 Phase Voltage Sag Detection ................................................. 32 Peak Detection ........................................................................ 33 Overvoltage and Overcurrent Detection ............................ 34 Neutral Current Mismatch ................................................... 35 Phase Compensation ................................................................. 35 Reference Circuit ........................................................................ 37 Digital Signal Processor ............................................................. 37 Root Mean Square Measurement ............................................. 37 Current RMS Calculation ..................................................... 38 Current Mean Absolute Value Calculation ......................... 39 Voltage Channel RMS Calculation ...................................... 40 Voltage RMS Offset Compensation ..................................... 41 Active Power Calculation .......................................................... 41 Total Active Power Calculation ............................................ 41 Fundamental Active Power Calculation .............................. 43 Active Power Gain Calibration ............................................. 43 Active Power Offset Calibration .......................................... 43 Sign of Active Power Calculation ......................................... 43 Active Energy Calculation .................................................... 44 Integration Time Under Steady Load .................................. 45 Energy Accumulation Modes ............................................... 46 Line Cycle Active Energy Accumulation Mode ................. 46 Reactive Power Calculation ...................................................... 47 Reactive Power Gain Calibration ......................................... 48 Reactive Power Offset Calibration ....................................... 48 Sign of Reactive Power Calculation ..................................... 48 Reactive Energy Calculation ................................................. 49 Integration Time Under A Steady Load .............................. 51 Energy Accumulation Modes ............................................... 51 Line Cycle Reactive Energy Accumulation Mode ............. 51 Apparent Power Calculation ..................................................... 52 Apparent Power Gain Calibration ....................................... 53 Apparent Power Offset Calibration . (53)
ADE7878
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Apparent Power Calculation Using VNOM ........................ 53 Apparent Energy Calculation ................................................ 53 Integration Time Under Steady Load ................................... 54 Energy Accumulation Mode .................................................. 54 Line Cycle Apparent Energy Accumulation Mode ............. 54 Waveform Sampling Mode ........................................................ 55 Energy-to-Frequency Conversion ............................................ 55 Synchronizing Energy Registers with CFx Outputs ........... 57 CF Outputs for Various Accumulation Modes ................... 57 Sign of Sum-of-Phase Powers in the CFx Datapath ........... 59 No Load Condition ..................................................................... 59 No Load Detection Based On Total Active, Reactive Powers ................................................................................................... 59 No Load Detection Based on Fundamental Active and Reactive Powers .. (60)
No Load Detection Based on Apparent Power ................... 60 Checksum Register ..................................................................... 60 Interrupts ..................................................................................... 62 Using the Interrupts with an MCU ...................................... 62 Serial Interfaces ........................................................................... 63 Serial Interface Choice ........................................................... 63 I 2C-Compatible Interface ....................................................... 63 SPI-Compatible Interface ...................................................... 65 HSDC Interface ....................................................................... 65 ADE7878 Evaluation Board ...................................................... 69 Die Version .................................................................................. 69 Registers List .................................................................................... 70 Outline Dimensions ........................................................................ 90 Ordering Guide (90)
REVISION HISTORY
2/10—Revision 0: Initial Version
ADE7878
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FUNCTIONAL BLOCK DIAGRAM
R E S E T R E F C L K I N C L K O U T I A P I A N V A P I B P I B N V B P I C P I C N
V C P V N S C L K
/S C L
S D A
H S D
A
I N P I N N 08510-201
Figure 1.
ADE7878
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SPECIFICATIONS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V , on-chip reference, CLKIN = 16.384 MHz, T MIN to T MAX = ?40°C to +85°C. Table 1.
Parameter 1, 2Min Typ Max Unit Test Conditions/Comments ACCURACY
Active Energy Measurement
Active Energy Measurement Error (per Phase)
Total Active Power
0.1
%
Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off
0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;
integrator off
0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;
integrator on
Fundamental Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;
integrator off
0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;
integrator off
0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;
integrator on
Phase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60° AC Power Supply Rejection
VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =
± 100 mV rms
Output Frequency Variation 0.01 % DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation
0.01 % Total Active Energy Measurement Bandwidth
2 kHz REACTIVE ENERGY MEASUREMENT Reactive Energy Measurement Error (per Phase)
Total Active Power
0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off
0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4; integrator off
0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on
Fundamental Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off
0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4; integrator off
0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on
Phase Error Between Channels
Line frequency = 45 Hz to 65 Hz, HPF on PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60°
AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx = ± 100 mV rms Output Frequency Variation
0.01
%
ADE7878
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Parameter 1, 2
Min Typ Max Unit Test Conditions/Comments
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation
0.01 %
Total Reactive Energy Measurement Bandwidth
2 kHz
RMS MEASUREMENTS
I rms and V rms Measurement Bandwidth
2 kHz I rms and V rms Measurement Error (PSM0 Mode)
0.1 % Over a dynamic range of 1000 to 1, PGA = 1 MEAN ABSOLUTE VALUE (MAV) MEASUREMENT
Imav Measurement Bandwidth (PSM1 Mode)
260 Hz
Imav Measurement Error (PSM1 Mode) 0.5 % Over a dynamic range of 100 to 1, PGA = 1 ANALOG INPUTS
Maximum Signal Levels
±500
mV peak
Differential inputs between the following pins: IAP and IAN, IBP and IBN, ICP and ICN; single-ended inputs between the following pins: VAP and VN, VBP and VN, VCP and VN Input Impedance (DC)
IAP , IAN, IBP , IBN, ICP , ICN, VAP , VBP , VCP Pins 400 kΩ
VN Pin
130 kΩ
ADC Offset Error ±20 mV PGA = 1, uncalibrated error, see the Terminology section Gain Error
±4 % External 1.2 V reference
WAVEFORM SAMPLING
Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS
Current and Voltage Channels See Waveform Sampling Mode section Signal-to-Noise Ratio, SNR
70 dB PGA = 1 Signal-to-Noise-and-Distortion Ratio, SINAD
65 dB PGA = 1
Bandwidth (?3 dB)
2 kHz TIME INTERVAL BETWEEN PHASES
Measurement Error
0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on CF1, CF2, CF3 PULSE OUTPUTS
Maximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139 Duty Cycle
50
%
If CF1, CF2, or CF3 frequency > 6.25 Hz and CFDEN is even and > 1
(1 + 1/CFDEN) × 50% If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is odd and > 1
Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz and
nominal phase currents are larger than 10% of full scale
REFERENCE INPUT REF IN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V ? 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 1.2 V at REF IN/OUT pin at T A = 25°C PSM0 and PSM1 Modes Reference Error ±0.9 mV max Output Impedance 1.4 kΩ min Temperature Coefficient 10 50 ppm/°C
ADE7878
1 See the Typical Performance Characteristics section.
2 See the Terminology section for a definition of the parameters.
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ADE7878
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TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V , on-chip reference, CLKIN = 16.384 MHz, T MIN to T MAX = ?40°C to +85°C. Table 2. I 2C-Compatible Interface Timing Parameter
Standard Mode Fast Mode Parameter Symbol Min Max Min Max Unit SCL Clock Frequency f SCL 0 100 0 400 kHz Hold Time (Repeated) Start Condition t HD;STA 4.0 0.6 μs Low Period of SCL Clock t LOW 4.7 1.3 μs High Period of SCL Clock t HIGH 4.0 0.6 μs Set-Up Time for Repeated Start Condition t SU;STA 4.7 0.6 μs Data Hold Time t HD;DAT 0 3.45 0 0.9 μs Data Setup Time t SU;DAT 250 100 ns Rise Time of Both SDA and SCL Signals t r 1000 20 300 ns Fall Time of Both SDA and SCL Signals t f 300 20 300 ns Setup Time for Stop Condition t SU;STO 4.0 0.6 μs Bus Free Time Between a Stop and Start Condition t BUF 4.7 1.3 μs Pulse Width of Suppressed Spikes t SP N/A 1 50 ns
1
N/A means not applicable.
CONDITION
CONDITION CONDITION CONDITION
08510-002
Figure 2. I 2
C-Compatible Interface Timing
ADE7878
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MOSI
MISO
SCLK
SS
08510-003
Figure 3. SPI Interface Timing
ADE7878
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Table 4. HSDC Interface Timing Parameter
Parameter Symbol Min Max Unit HSA to SCLK Edge t SS 0 ns HSCLK Period 125 ns HSCLK Low Pulse Width t SL 50 ns HSCLK High Pulse Width t SH 50 ns Data Output Valid After HSCLK Edge t DAV 40 ns Data Output Fall Time t DF 20 ns Data Output Rise Time t DR 20 ns HSCLK Rise Time t SR 10 ns HSCLK Fall Time t SF 10 ns HSD Disable After HSA Rising Edge t DIS 5 ns HSA High After HSCLK Edge t SFS 0
ns
HSD
HSCLK
HSA
Figure 4. HSDC Interface Timing
1.6V
08510-005
Figure 5. Load Circuit for Timing Specifications
ADE7878
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ABSOLUTE MAXIMUM RATINGS
T A = 25°C, unless otherwise noted. Table 5. Absolute Maximum Ratings
Parameter Rating
VDD to AGND ?0.3 V to +3.7 V
VDD to DGND ?0.3 V to +3.7 V
Analog Input Voltage to AGND, IAP , IAN, IBP , IBN, ICP , ICN, VAP , VBP , VCP , VN
?2 V to +2 V
Analog Input Voltage to INP and INN ?2 V to +2 V
Reference Input Voltage to AGND
?0.3 V to VDD + 0.3 V Digital Input Voltage to DGND ?0.3 V to VDD + 0.3 V Digital Output Voltage to DGND ?0.3 V to VDD + 0.3 V Operating Temperature
Industrial Range
?40°C to +85°C Storage Temperature Range ?65°C to +150°C Junction Temperature 150°C Lead Temperature Range (Soldering, 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE
θJA is specified equal to 29.3°C/W; θJC is specified equal to 1.8°C/W .
Table 6. Thermal Resistance
Package Type θJA θJC Unit 40-Lead LFCSP
29.3
1.8 °C/W
ESD CAUTION
ADE7878
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1NC 2PM03PM14RESET 5DVDD 6DGND 7IAP 8IAN 9IBP 10
NC 23VAP 24AVDD 25AGND 26VDD 27CLKIN 28CLKOUT 29IRQ030NC NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND.
22VBP 21NC
11N C 12I B N 13I C P 15I N P 17R E F I N /O U T 16I N N
18V N 19V C P 20
N C
14I C N 33C F 134C F
235C F 3/H S C L K 36S C L K /S C L 37M I S O /H S D 38M O S I /S D A 39S S /H S A 40N C 32I R Q 131
N C
08510-106
Figure 6. Pin Configuration
ADE7878
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ADE7878
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TYPICAL PERFORMANCE CHARACTERISTICS
–0.40
–0.35
–0.30–0.25–0.20–0.15–0.10E R R O R (%)
–0.0500.050.100.01
0.1
1
10
100FULL-SCALE CURRENT (%)
08510-301
Figure 7. Total Active Energy Error As Percentage of Reading (Gain = +1, pF = 1) over Temperature with Internal Reference and Integrator Off
–0.25
–0.20–0.15–0.10–0.0500.050.100.1545
47495153555759616365LINE FREQUENCY (Hz)
E R R O R (%)
08510-305
Figure 8. Total Active Energy Error As Percentage of Reading (Gain = +1, pF = 1) over Frequency with Internal Reference and Integrator Off
–0.15
–0.10
–0.05
0.05
0.10
0.15
E R R O R (%)
0.01
0.11
10100
FULL-SCALE CURRENT (%)
08510-306
Figure 9. Total Active Energy Error As Percentage of Reading (Gain = +1, pF = 1) over Power Supply with Internal Reference and Integrator Off –0.60
–0.40–0.2000.200.400.60
0.800.1
110100
FULL-SCALE CURRENT (%)
E R R O R
(%)
08510-308
Figure 10. Total Active Energy Error As Percentage of Reading (Gain = +16)
over Temperature with Internal Reference and Integrator On
–0.50
–0.40–0.30–0.20–0.1000.100.200.300.400.01
0.11
10100
FULL-SCALE CURRENT (%)
E R R O R (%)
08510-311
Figure 11. Total Reactive Energy Error As Percentage of Reading (Gain = +1, pF = 0) over Temperature with Internal Reference and Integrator Off
–0.25
–0.20–0.15
–0.10–0.050
0.050.1045
4749
515355575961
6365
LINE FREQUENCY (Hz)
E R R O R (%)
08510-315
Figure 12. Total Reactive Energy Error As Percentage of Reading (Gain = +1)
over Frequency with Internal Reference and Integrator Off
ADE7878
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–0.30
–0.20–0.1000.100.200.30
0.010.11
10100FULL-SCALE CURRENT (%)
E R R O R
(%)
08510-316
Figure 13. Total Reactive Energy Error As Percentage of Reading (Gain = +1)
over Power Supply with Internal Reference and Integrator Off
–0.40
–0.30
–0.20–0.1000.100.200.30
0.400.500.600.1
110100
FULL-SCALE CURRENT (%)
E R R
O R (%)
08510-318
Figure 14. Total Reactive Energy Error As Percentage of Reading (Gain = +16)
over Temperature with Internal Reference and Integrator On
–0.25
–0.20–0.15–0.10–0.0500.050.100.150.20E R R O R (%)
45
47
49
51
53
55
57
59
61
63
65
LINE FREQUENCY (Hz)
08510-335
Figure 15. Fundamental Active Energy Error As Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off –0.15
–0.10
–0.05
0.050.10
0.15
0.01
0.10 1.0010.00100.00
FULL-SCALE CURRENT (%)
E R R O R (%
)
08510-337
Figure 16. CF Fundamental Active Energy Error As a Percentage of Reading
(Gain = +1) with Internal Reference and Integrator Off
–0.30
–0.20–0.1000.100.200.300.400.500.600.700.10
1.0010.00100.00
FULL-SCALE CURRENT (%)
E R
R O R (%)
08510-338
Figure 17. Fundamental Active Energy Error As Percentage of Reading (Gain = +16) over Temperature with Internal Reference and Integrator On
–0.25
–0.20–0.15–0.10–0.0500.050.100.15
45
47495153
555759616365
LINE FREQUENCY (Hz)
E R R O R (%)
08510-345
Figure 18. Fundamental Reactive Energy Error As Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off
ADE7878
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–0.15
–0.10
–0.05
0.05
0.10
0.15
0.01
0.10 1.0010.00100.00FULL-SCALE CURRENT (%)E R R O R (%)
08510-347
–0.40
–0.30
–0.20
–0.1000.100.20
0.30
0.40
0.500.10
1.0010.00100.00
FULL-SCALE CURRENT (%)
E R R O R (%)
08510-348
Figure 19. CF Fundamental Reactive Energy Error As a Percentage of Reading
(Gain = +1) with Internal Reference and Integrator Off Figure 20. Fundamental Reactive Energy Error As Percentage of Reading (Gain = +16) over Temperature with Internal Reference and Integrator On
ADE7878
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TEST CIRCUIT
?08510-099
Figure 21. Test Circuit
ADE7878
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TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the ADE7878 is defined by
Measurement Error =
%1007878×?Energy
True Energy
True ADE by Registered Energy (1)
Phase Error Between Channels
The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers.
Power Supply Rejection (PSR)
This quantifies the ADE7878 measurement error as a percen-tage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (120 mV rms at 100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied ±10%. Any error introduced is expressed as a percentage of the reading.
ADC Offset Error
This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magni-tude of the offset depends on the gain and input range selection (see the Typical Performance Characteristics section). However, a HPF removes the offset from the current and voltage channels and the power calculation remains unaffected by this offset. Gain Error
The gain error in the ADCs of the ADE7878 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). The difference is expressed as a percentage of the ideal code. CF Jitter
The period of pulses at one of the CF1, CF2, or CF3 pins is
continuously measured. The maximum, minimum, and average values of four consecutive pulses are computed as follows:
Maximum = max (Period 0, Period 1, Period 2, Period 3) Minimum = min (Period 0, Period 1, Period 2, Period 3) Average =
4
3
210Period Period Period Period +++
The CF jitter is then computed as
%100×?=Average
Minimum
Maximum CF JITTER (2)
ADE7878
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POWER MANAGEMENT
The ADE7878 has four modes of operation, determined by the state of the PM0 and PM1 pins (see Table 8). These pins provide complete control of the ADE7878 operation and can easily be connected to an external microprocessor I/O. The PM0 and PM1 pins have internal pull-up resistors. Table 10 and Table 11 list actions that are recommended before and after setting a new power mode.
Table 8. ADE7878 Power Supply Modes
Power Supply Modes
PM1 PM0 PSM0, Normal Power Mode 0 1 PSM1, Reduced Power Mode 0 0 PSM2, Low Power Mode 1 0 PSM3, Sleep Mode
1
1
PSM0—NORMAL POWER MODE
In PSM0 mode, the ADE7878 is fully functional. The PM0 pin is set to high and the PM1 pin is set to low for the ADE7878 to enter this mode. If the ADE7878 is in one of PSM1, PSM2, or PSM3 modes and is switched into PSM0 mode, then all control registers take the default values with the exception of the threshold register, LPOILVL[7:0], which is used in PSM2 mode, and the CONFIG2[7:0] register, both of which maintain their values. The ADE7878 signals the end of the transition period by triggering the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition is finished. The status bit is cleared and the IRQ1 pin is set back to high by writing STATUS1[31:0] register with the corresponding bit set to 1. Bit 15 (RSTDONE) in the interrupt mask register does not have any functionality attached even if the IRQ1 pin goes low when Bit 15 (RSTDONE) in the STATUS1[31:0] register is set to 1. This makes the RSTDONE interrupt unmaskable.
PSM1—REDUCED POWER MODE
In this mode, the ADE7878 measures the mean absolute values (mav) of the 3-phase currents and stores the results in the AIMAV[19:0], BIMAV[19:0], and CIMAV[19:0] 20-bit
registers. This mode is useful in missing neutral cases in which the voltage supply of the ADE7878 is provided by an external battery. The serial ports, I 2C or SPI, are enabled in this mode and the active port can be used to read the AIMAV , BIMAV , and CIMAV registers. It is not recommended to read any of the other registers because their values are not guaranteed in this mode. Similarly, a write operation is not taken into account by the ADE7878 in this mode. In summary, in this mode, it is not recommended to access any register other than AIMAV ,
BIMAV , and CIMAV . The circuit that measures these estimates of rms values is also active during PSM0; therefore, its calibration can be completed in either PSM0 mode or in PSM1 mode. Note
that the ADE7878 does not provide any register to store or process the corrections resulting from the calibration process. The external microprocessor should store the gain values in connection with these measurements and use them during PSM1 (see the Current Mean Absolute Value Calculation section for more details on the xIMAV registers).
The 20-bit mean absolute value measurements done in PSM1, although available also in PSM0, are different from the rms measurements of phase currents and voltages executed only in PSM0 and stored in xIRMS and xVRMS 24-bit registers. See the Current Mean Absolute Value Calculation section for details. If the ADE7878 is set in PSM1 mode while still in PSM0, the ADE7878 immediately begins the mean absolute value calcula-tions without any delay. The xIMAV registers can be accessed at any time; however, if the ADE7878 is set in PSM1 mode while still in PSM2 or PSM3 modes, the ADE7878 signals the start of the mean absolute value computations by triggering the IRQ1 pin low. The xIMAV registers can be accessed only after this moment.
PSM2—LOW POWER MODE
In this mode, the ADE7878 compares all phase currents against a threshold for a period of 0.02 × (LPLINE + 1) seconds,
independent of the line frequency. LPLINE are Bits[7:3] of the LPOILVL[7:0] register (see Table 9). Table 9. LPOILVL Register
Bit Mnemonic Default Description [2:0] LPOIL 111 Threshold is put at a value
corresponding to full scale multiplied by LPOIL/8.
[7:3] LPLINE 00000 The measurement period is
(LPLINE + 1)/50 sec.
The threshold is derived from Bits[2:0] (LPOIL) of the LPOILVL[7:0] register as LPOIL/8 of full scale. Every time one phase current becomes greater than the threshold, a counter is incremented. If every phase counter remains below LPLINE + 1 at the end of the measurement period, then the IRQ0 pin is triggered low. If a single phase counter becomes greater or equal to LPLINE + 1 at the end of the measurement period, the IRQ1 pin is triggered low. illustrates how the ADE7878 behaves in PSM2 mode when LPLINE = 2 and LPOIL = 3. The test period is three 50 Hz cycles (60 ms), and the Phase A current rises above the LPOIL threshold three times. At the end of the test period, the Figure 22IRQ1 pin is triggered low. The I 2C or SPI port is not functional during this mode. The PSM2 mode reduces the power consumption required to mon-itor the currents when there is no voltage input and the voltage supply of the ADE7878 is provided by an external battery. If the
ADE7878
Rev. 0 | Page 20 of 92
0IRQ pin is triggered low at the end of a measurement period, this signifies all phase currents stayed below threshold and, therefore, there is no current flowing through the system. At this point, the external microprocessor should set the ADE7878 in Sleep Mode PSM3. If the 1IRQ pin is triggered low at the end of the measurement period, this signifies that at least one current input is above the defined threshold and current is flowing through the system, although no voltage is present at the ADE7878 pins. This situation is often called missing neutral and is considered a tampering situation, at which point the external microprocessor should set the ADE7878 in PSM1 mode, measure mean absolute values of phase currents, and integrate the energy based on their values and the nominal voltage.
It is recommended to use the ADE7878 in PSM2 mode when Bits[2:0] (PGA1) of the Gain[15:0] register are equal to 1 or 2. These bits represent the gain in the current channel datapath. It is not recommended to use the ADE7878 in PSM2 mode when the PGA1 bits are equal to 4, 8, or 16.
PSM3—SLEEP MODE
In this mode, the ADE7878 has most of the internal circuits turned off and the current consumption is at its lowest level. The I 2C, HSDC, and SPI ports are not functional during this mode, and the RESET, SCLK/SCL, MOSI/SDA, and SS/HSA pins should be set high.
POWER-UP PROCEDURE
The ADE7878 contains an on-chip power supply monitor that supervises the power supply (VDD). At power-up, until VDD reaches 2 V ± 10%, the chip is in an inactive state. As VDD crosses this threshold, the power supply monitor keeps the chip in this inactive state for an additional 26 ms, allowing VDD to achieve 3.3 V ? 10%, the minimum recommended supply voltage. Because the PM0 and PM1 pins have internal pull-up resistors and the external microprocessor keeps them high, the ADE7878 always powers-up in sleep mode (PSM3). Then, an external circuit (that is, a microprocessor) sets the PM1 pin to a low level, allowing the ADE7878 to enter normal mode (PSM0). The passage from PSM3 mode, in which most of the internal circuitry is turned off, to PSM0 mode, in which all functionality is enabled, is accomplished in less than 40 ms (see Figure 23 for details).
When the ADE7878 enters PSM0 mode, the I 2C port is the active serial port. If the SPI port is used, then the SS/HSA pin must be toggled three times high to low. This action selects the SPI port for further use. If I 2C is the active serial port, Bit 1 (I2C_LOCK) of CONFIG2[7:0] must be set to 1 to lock it in. From this moment, the ADE7878 ignores spurious toggling of the SS/HSA pin, and an eventual switch to use the SPI port is no longer possible. Likewise, if SPI is the active serial port, any write to the CONFIG2[7:0] register locks the port, at which time a switch to use the I 2C port is no longer possible.
POR TIMER TURNED ON
ADE7878POWERED UP
ADE7878ENTER PSM3MICROPROCESSOR SETS ADE7878IN PSM0
CHOICE BETWEEN I 2C AND SPI
RSTDONE INTERRUPT TRIGGERED
08510-009
Figure 23. Power-Up Procedure
DF12型手扶拖拉机变速驱动系统设计
本科毕业设计 题目：DF12型手扶拖拉机变速驱动系统设计 学院： 姓名： 学号： 专业：机械设计制造及其自动化 年级： 指导教师：
摘要 随着变型运输拖拉机和农用运输车的发展，原来依靠农村运输业发展起来的小四轮拖拉机逐步转向田间地头。然而，目前小四轮拖拉机田间作业能力差，又没有很多配套的农业机械，农忙季节短，致使大量小四轮拖拉机一年中作业时间短，被迫长期闲置着。这影响了农村专业户的作业效益，也造成了不应该有的资源浪费。针对这些情况，我们在原有小四轮拖拉机的基础上稍微作些改动，使它的功能延伸。譬如可在原来小四轮拖拉机的基础上，改变座位、方向盘、离合、油门、刹车的方位，把拖拉机变成倒开式，在变速箱后安装挖掘装置、铲运装置或装载装置而成。 本次毕业设计是对机械专业学生在毕业前的一次全面训练，目的在于巩固和扩大学生在校期间所学的基础知识和专业知识，训练学生综合运用所学知识分析和解决问题的能力。是培养、锻炼学生独立工作能力和创新精神之最佳手段。毕业设计要求每个学生在工作过程中，要独立思考，刻苦钻研，有所创造的分析、解决技术问题。通过毕业设计，使学生掌握改造方案的拟定、比较、分析及进行必要的计算。 关键字：齿轮操纵机构轴轴承锁定机构
DESING of a CERTAIN TYPE of TRACTOR GEARBOX With variant transport tractors and agricultural the development of carriage car, depends on rural transportation industry to develop the small four-wheel tractor to field edge of a field. However, at present, small four-wheel the tractor field work ability is poor, and not many ancillary agricultural machinery, busy season is short, resulting in a large number of small four-wheel tractor year short operation time, forced long-term idle. The influence of rural specialist work benefit, also cause should not be some waste of resources. In light of these circumstances, we in the original small four-wheel tractor based on slightly to make some changes, make it functional extension. For example, in the original small four-wheel tractor based on, change seats, steering wheel, clutch, throttle, brake position, the tractor into inverted open, in a gearbox installed after digging device, lifting device or a loading device. The graduation design is about mechanical speciality students before graduation and a comprehensive training, purpose is to consolidate and expand the students learn the basic knowledge and professional knowledge, training students' comprehensive use of the knowledge the ability to analyze and solve problems. Is training, training students the ability to work independently and the spirit of innovation is the best means. Graduation design requirements of each student in the course of the work, we need to think independently, study assiduously, create somewhat analysis, solving technical problems. Through the graduation project, so that students master the transformation plan formulation, comparison, analysis and necessary calculation. Key words:Gear Manipulation of body Axis Bearing Locking mechanism
电动车辆无级变速驱动系统、变速控制系统及方法与设计方案
一种电动车辆技术领域的电动车辆无级变速驱动系统、变速控制系统及方法，包括：第一驱动电机、行星轮系、第二驱动电机和第三输出机构，其中，行星轮系设有齿圈、行星支架、太阳轮和若干行星齿轮，行星齿轮周向均布在行星支架上，行星支架和齿圈之一与第二驱动电机的输出轴啮合、另一与第三输出机构啮合，齿圈与行星齿轮啮合，太阳轮与第一驱动电机输出端连接并与行星齿轮啮合。本技术采用行星减速机构，通过第二驱动电机带动行星支架或者齿圈的转动达到所需要的减速比，完成电动车的无级变速，实现换挡自动化。 技术要求 1.一种电动车辆无级变速驱动系统，其特征在于，包括：第一驱动电机、行星轮系、第二驱动电机和第三输出机构，其中：行星轮系设有齿圈、行星支架、太阳轮和若干行星齿轮，行星齿轮周向均布在行星支架上，行星支架和齿圈之一与第二驱动电机的输出轴啮合、另一与第三输出机构啮合，齿圈与行星齿轮啮合，太阳轮与第一驱动电机输出端连 接并与行星齿轮啮合。 2.根据权利要求1所述的电动车辆无级变速驱动系统，其特征是，所述的齿圈、行星支架和太阳轮均套设在主轴上。 3.根据权利要求1所述的电动车辆无级变速驱动系统，其特征是，所述第三输出机构设有轮轴，所述的轮轴与电动车辆的驱动轴固定连接。 4.根据权利要求2所述的电动车辆无级变速驱动系统，其特征是，所述的第一驱动电机包括转子总成和绕线定子，其中，转子总成设有转子内衬套，转子内衬套一端固定有太阳轮。 5.根据权利要求2所述的电动车辆无级变速驱动系统，其特征是，所述第一驱动电机的输出端与太阳轮通过减速机构相连，所述的减速机构为皮带、链条、齿轮传动机构中任意 一种。
6.一种应用于上述任一权利要求所述电动车辆无级变速驱动系统的变速控制系统，其特征在于，包括：行车电脑、制动传感器、变速传感器、第一驱动电机控制单元、第二驱动电机控制单元、第一转速传感器和第二转速传感器，其中， 制动传感器与行车电脑相连并输出制动信号； 变速传感器与行车电脑相连并输出加速信号或减速信号； 行车电脑与第一驱动电机控制单元、第二驱动电机控制单元相连并传输两驱动电机的控制信息； 第一转速传感器与行车电脑相连并输出第一驱动电机转速信息； 第二转速传感器与行车电脑相连并输出第二驱动电机转速信息。 7.根据权利要求6所述电动车辆无级变速驱动系统的变速控制系统，其特征在于，所述的变速控制系统还包括：第一电流传感器、第二电流传感器、第一电压传感器、第二电压传感器、第一扭矩传感器和第二扭矩传感器，其中， 第一扭矩传感器与行车电脑相连并输出第一驱动电机扭矩信息； 第二扭矩传感器与行车电脑相连并输出第二驱动电机扭矩信息； 第一电流传感器、第一电压传感器与第一驱动电机控制单元相连并分别输出第一驱动电机的输入电流和输入电压信息； 第二电流传感器、第二电压传感器与第二驱动电机控制单元相连并分别输出第二驱动电机的输入电流和输入电压信息。 8.一种基于权利要求6或7所述变速控制系统的电动车辆变速控制方法，其特征在于，包括以下步骤： S1，首先判断输入信号是否为制动信号，若为制动信号，则第一驱动电机和第二驱动电机停转，电动车辆停车，否则判断为变速信号；