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sn74lv595a

>2.3 V at V CC = 3.3 V, T A = 25°C D

Support Mixed-Mode Voltage Operation on All Ports

D 8-Bit Serial-In, Parallel-Out Shift ESD Protection Exceeds JESD 22? 2000-V Human-Body Model (A114-A)? 200-V Machine Model (A115-A)? 1000-V Charged-Device Model (C101)

SN54LV595A ...J OR W PACKAGE SN74LV595A ...D, DB, NS,OR PW PACKAGE (TOP VIEW)SN54LV595A ...FK PACKAGE

(TOP VIEW)

NC ? No internal connection

12345678161514131211109

Q B Q C Q D Q E Q F Q G Q H GND V CC Q A SER OE RCLK SRCLK SRCLR Q H ′3212019910111213456781817161514SER OE NC RCLK SRCLK Q D Q E NC Q F Q G Q N C S R C L R H G N D N C C Q B V C C Q A Q H Q ′

SN74LV595A ...RGY PACKAGE (TOP VIEW)11689234567151413121110Q A SER OE RCLK SRCLK SRCLR Q C Q D Q E Q F Q G Q H Q Q V G N D C C B

H ′description/ordering information

The ’LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V V CC operation.

ORDERING INFORMATION

T A PACKAGE ?

ORDERABLE PART NUMBER TOP-SIDE MARKING QFN ? RGY

Reel of 1000SN74LV595ARGYR LV595A Tube of 40SN74LV595ADG3SOIC ? D

Reel of 2500SN74LV595ADR LV595A 40°C to 85°C SOP ? NS

Reel of 2000SN74LV595ANSR 74LV595A ?SSOP ? DB

Reel of 2000SN74LV595ADBR LV595A Tube of 90SN74LV595APW ? PW

Reel of 2000SN74LV595APWRG3TSSOP Reel of 250SN74LV595APWT LV595A CDIP ? J

Tube of 25SNJ54LV595AJ SNJ54LV595AJ ?55°C to 125°C

CFP ? W Tube of 150SNJ54LV595AW SNJ54LV595AW LCCC ? FK Tube of 55SNJ54LV595AFK SNJ54LV595AFK ?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at https://www.wendangku.net/doc/bb1123603.html,/sc/package.

UNLESS OTHERWISE NOTED this doc ument c ontains PRODUCTION Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011

description/ordering information (continued)

These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.

The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except Q H′ are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS

SER SRCLK SRCLR RCLK OE

FUNCTION

X X X X H Outputs Q A?Q H are disabled.

X X X X L Outputs Q A?Q H are enabled.

X X L X X Shift register is cleared.

L↑H X X First stage of the shift register goes low.

Other stages store the data of previous stage, respectively.

H↑H X X First stage of the shift register goes high.

Other stages store the data of previous stage, respectively.

X X X↑X Shift-register data is stored in the storage register.

SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011logic diagram (positive logic)

Q A

Q B

Q C

Q D

Q E

Q F

Q G

Q H Q H ′

SRCLR

RCLK

SRCLK

SER Pin numbers shown are for the D, DB, J, NS, PW, RGY , and W packages.

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011

timing diagram

SRCLK

SER

RCLK

SRCLR

Q A

Q B

Q C

Q D

Q E

Q F

Q G

Q H

Q H′

NOTE:

implies that the output is in 3-State mode.

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)?Supply voltage range, V CC?0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V I (see Note 1) ?0.5 V to 7 V Voltage range applied to any output in the high-impedance

or power-off state, V O(see Note 1) ?0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .

Output voltage range applied in the high or low state, V O (see Notes 1 and 2) ?0.5 V to V CC + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I IK (V I < 0) ?20 mA Output clamp current, I OK (V O < 0) ?50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I O (V O = 0 to V CC) ±35 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V CC or GND ±70 mA Package thermal impedance, θJA(see Note 3):D package 73°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3):DB package 82°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3):NS package 64°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3):PW package 108°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 4):RGY package 39°C/W Storage temperature range, T stg?65°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

?Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1.The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2.This value is limited to 5.5 V maximum.

3.The package thermal impedance is calculated in accordance with JESD 51-7.

4.The package thermal impedance is calculated in accordance with JESD 51-

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011

recommended operating conditions (see Note 5)

SN54LV595A SN74LV595A

MIN MAX MIN MAX

UNIT V CC Supply voltage2 5.52 5.5V

V CC = 2 V 1.5 1.5

High level input voltage V CC = 2.3 V to 2.7 V V CC×0.7V CC×0.7

V IH High-level input voltage

V CC = 3 V to 3.6 V V CC×0.7V CC×0.7

V CC = 4.5 V to 5.5 V V CC×0.7V CC×0.7

V CC = 2 V0.50.5

Low level input voltage V CC = 2.3 V to 2.7 V V CC×0.3V CC×0.3

V IL Low-level input voltage

V CC = 3 V to 3.6 V V CC×0.3V CC×0.3

V CC = 4.5 V to 5.5 V V CC×0.3V CC×0.3

V I Input voltage0 5.50 5.5V

High or low state0V CC0V CC

V O Output voltage

3-state0 5.50 5.5

V CC = 2 V?50?50μA

High level output current V CC = 2.3 V to 2.7 V?2?2

I OH High-level output current

V CC = 3 V to 3.6 V?8?8

V CC = 4.5 V to 5.5 V?16?16

V CC = 2 V5050μA

Low level output current V CC = 2.3 V to 2.7 V22

I OL Low-level output current

V CC = 3 V to 3.6 V88

V CC = 4.5 V to 5.5 V1616

V CC = 2.3 V to 2.7 V200200

V CC = 3 V to 3.6 V100100

Δt/Δv Input transition rise or fall rate

V CC = 4.5 V to 5.5 V2020

ns/V

T A Operating free-air temperature?55125?4085°C NOTE 5:All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or

c c

SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)SN54LV595A SN74LV595A PARAMETER TEST CONDITIONS

V CC MIN TYP MAX MIN TYP MAX UNIT

I OH = ?50 μA

2 V to 5.5 V V CC ?0.1V CC ?0.1I OH = ?2 mA

2.3 V 22Q H ′

I OH = ?6 mA 2.48 2.48V OH Q A ?Q H

I OH = ?8 mA 3 V 2.48 2.48V Q H ′

I OH = ?12 mA 45 V 3.8 3.8Q A ?Q H I OH = ?16 mA

4.5 V 3.8 3.8I OL = 50 μA

2 V to 5.5 V 0.10.1I OL = 2 mA

2.3 V 0.40.4Q H ′

I OL = 6 mA 0.440.44V OL Q A ?Q H

I OL = 8 mA 3 V 0.440.44V Q H ′

I OL = 12 mA 45 V 0.550.55Q A ?Q H

I OL = 16 mA 4.5 V 0.550.55I I

V I = 5.5 V or GND 0 to 5.5 V ±1±1μA I OZ

V O = V CC or GND,Q A ?Q H 5.5 V ±5±5μA I CC

V I = V CC or GND,I O = 0 5.5 V 2020μA I off

V I or V O = 0 to 5.5 V 055μA C i V I = V CC or GND 3.3 V 3.5 3.5pF timing requirements over recommended operating free-air temperature range, V CC = 2.5 V ±0.2 V (unless otherwise noted) (see Figure 1)

T A = 25°C

SN54LV595A SN74LV595A MIN

MAX MIN MAX MIN MAX UNIT SRCLK high or low

77.57.5RCLK high or low

77.57.5t w Pulse duration SRCLR low

6 6.5 6.5ns SER before SRCLK ↑

5.5 5.5 5.5SRCLK ↑ before RCLK ↑?

899t su Setup time SRCLR low before RCLK ↑

8.59.59.5ns SRCLR high (inactive) before SRCLK ↑

444t h

Hold time SER after SRCLK ↑ 1.5 1.5 1.5ns ?This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift

PRODUCT PREVIEW information concerns products in the formative or c c

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

c c

WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011

timing requirements over recommended operating free-air temperature range, V CC= 3.3 V±0.3 V (unless otherwise noted) (see Figure 1)

T A= 25°C SN54LV595A SN74LV595A

UNIT

MIN MAX MIN MAX MIN MAX

SRCLK high or low 5.5 5.5 5.5

RCLK high or low 5.5 5.5 5.5

t w Pulse duration

SRCLR low555

SER before SRCLK↑ 3.5 3.5 3.5

SRCLK↑ before RCLK↑?88.58.5

t su Setup time

SRCLR low before RCLK↑899

SRCLR high (inactive) before SRCLK↑333

t h Hold time SER after SRCLK↑ 1.5 1.5 1.5ns

?This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.

timing requirements over recommended operating free-air temperature range, V CC= 5 V±0.5 V (unless otherwise noted) (see Figure 1)

T A= 25°C SN54LV595A SN74LV595A

UNIT

MIN MAX MIN MAX MIN MAX

SRCLK high or low555

RCLK high or low555

t w Pulse duration

SRCLR low 5.2 5.2 5.2

SER before SRCLK↑333

SRCLK↑ before RCLK↑?555

t su Setup time

SRCLR low before RCLK↑555

SRCLR high (inactive) before SRCLK↑ 2.5 2.5 2.5

t h Hold time SER after SRCLK↑222ns

PRODUCT PREVIEW information concerns products in the formative or

SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011switching characteristics over recommended operating free-air temperature range,V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD T A = 25°C SN54LV595A SN74LV595A PARAMETER

(INPUT)(OUTPUT)CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT C L = 15 pF 65*80*45*45f max

C L = 50 pF 60704040MHz

t PLH

8.4*14.2*1*15.8*115.8t PHL

RCLK Q A ?Q H 8.4*14.2*1*15.8*115.8t PLH

9.4*19.6*1*22.2*122.2t PHL

SRCLK Q H ′9.4*19.6*1*22.2*122.2t PHL

SRCLR Q H ′C = 15 pF 8.7*14.6*1*16.3*116.3ns t PZH

L p 8.2*13.9*1*15*115t PZL

OE Q A ?Q H 10.9*18.1*1*20.3*120.3t PHZ

8.3*13.7*1*15.6*115.6t PLZ

OE Q A ?Q H 9.2*15.2*1*16.7*116.7t PLH

11.217.2119.3119.3t PHL

RCLK Q A ?Q H 11.217.2119.3119.3t PLH

13.122.5125.5125.5t PHL

SRCLK Q H ′13.122.5125.5125.5t PHL

SRCLR Q H ′C = 50 pF 12.418.8121.1121.1ns t PZH

L p 10.817118.3118.3t PZL

OE Q A ?Q H 13.421123123t PHZ

12.218.3119.5119.5t PLZ OE Q A ?Q H 1420.9122.6122.6* On products compliant to MIL-PRF-38535, this parameter is not production tested.

PRODUCT PREVIEW information concerns products in the formative or c c

SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011switching characteristics over recommended operating free-air temperature range,V CC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD T A = 25°C SN54LV595A SN74LV595A PARAMETER

(INPUT)(OUTPUT)CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT C L = 15 pF 80*120*70*70f max

C L = 50 pF 551055050MHz

t PLH

6*11.9*1*13.5*113.5t PHL

RCLK Q A ?Q H 6*11.9*1*13.5*113.5t PLH

6.6*13*1*15*115t PHL

SRCLK Q H ′ 6.6*13*1*15*115t PHL

SRCLR Q H ′C = 15 pF 6.2*12.8*1*13.7*113.7ns t PZH

L p 6*11.5*1*13.5*113.5t PZL

OE Q A ?Q H 7.8*11.5*1*13.5*113.5t PHZ

6.1*14.7*1*15.2*115.2t PLZ

OE Q A ?Q H 6.3*14.7*1*15.2*115.2t PLH

7.915.4117117t PHL

RCLK Q A ?Q H 7.915.4117117t PLH

9.216.5118.5118.5t PHL

SRCLK Q H ′9.216.5118.5118.5t PHL

SRCLR Q H ′C = 50 pF 916.3117.2117.2ns t PZH

L p 7.815117117t PZL

OE Q A ?Q H 9.615117117t PHZ

8.115.7116.2116.2t PLZ OE Q A ?Q H 9.315.7116.2116.2* On products compliant to MIL-PRF-38535, this parameter is not production tested.

PRODUCT PREVIEW information concerns products in the formative or c c

SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011switching characteristics over recommended operating free-air temperature range,V CC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD T A = 25°C SN54LV595A SN74LV595A PARAMETER

(INPUT)(OUTPUT)CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT C L = 15 pF 135*170*115*115f max

C L = 50 pF 1201409595MHz

t PLH

4.3*7.4*1*8.5*18.5t PHL

RCLK Q A ?Q H 4.3*7.4*1*8.5*18.5t PLH 4.5*8.2*1*9.4*19.4t PHL

SRCLK Q H ′ 4.5*8.2*1*9.4*19.4t PHL

SRCLR Q H ′C = 15 pF 4.5*8*1*9.1*19.1ns t PZH

L p 4.3*8.6*1*10*110t PZL

OE Q A ?Q H 5.4*8.6*1*10*110t PHZ

2.4*6*1*7.1*17.1t PLZ

OE Q A ?Q H 2.7* 5.1*1*7.2*17.2t PLH

5.69.4110.5110.5t PHL

RCLK Q A ?Q H 5.69.4110.5110.5t PLH

6.410.2111.4111.4t PHL

SRCLK Q H ′ 6.410.2111.4111.4t PHL

SRCLR Q H ′C = 50 pF 6.410111.1111.1ns t PZH

L p 5.710.6112112t PZL

OE Q A ?Q H 6.810.6112112t PHZ

3.510.3111111t PLZ OE Q A ?Q H 3.410.3111111* On products compliant to MIL-PRF-38535, this parameter is not production tested.

noise characteristics, V CC = 3.3 V, C L = 50 pF, T A = 25°C (see Note 6)

SN74LV595A PARAMETER

MIN TYP MAX UNIT V OL(P)

Quiet output, maximum dynamic V OL 0.3V V OL(V)

Quiet output, minimum dynamic V OL ?0.2V V OH(V)

Quiet output, minimum dynamic V OH 2.8V V IH(D)

High-level dynamic input voltage 2.31V V IL(D)Low-level dynamic input voltage 0.99V

NOTE 6:Characteristics are for surface-mount packages only.

operating characteristics, T A = 25°C

PARAMETER

TEST CONDITIONS V CC TYP UNIT 50 pF f 10 MHz 3.3 V

111C pd Power dissipation capacitance C L = 50 pF, f = 10 MHz 5 V 114pF

PRODUCT PREVIEW information concerns products in the formative or c c

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

WITH 3-STATE OUTPUT REGISTERS

SCLS414O ? APRIL 1998 ? REVISED JANUARY 2011

PARAMETER MEASUREMENT INFORMATION

V CC

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at V CC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V OL

V OH

≈V CC

0 V

≈0 V

V CC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t PLH/t PHL

t PLZ/t PZL

t PHZ/t PZH

Open Drain

Open

V CC

GND

V CC

TEST S1

V CC

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, Z O = 50 Ω, t r≤3 ns, t f≤ 3 ns.

D.The outputs are measured one at a time, with one input transition per measurement.

E.t PLZ and t PHZ are the same as t dis.

F.t PZL and t PZH are the same as t en.

G.t PHL and t PLH are the same as t pd.

H.All parameters and waveforms are not applicable to all devices.

From Output

Under Test

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

From Output

Under Test

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

Figure 1. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package

Drawing Pins Package Qty Eco Plan (2)Lead/

Ball Finish

MSL Peak Temp (3)Samples

(Requires Login)

SN74LV595AD ACTIVE SOIC D1640Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ADE4ACTIVE SOIC D1640Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ADG4ACTIVE SOIC D1640Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ADR ACTIVE SOIC D162500Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ADRE4ACTIVE SOIC D162500Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ADRG3ACTIVE SOIC D162500Green (RoHS

& no Sb/Br)

CU SN Level-1-260C-UNLIM

SN74LV595ADRG4ACTIVE SOIC D162500Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ANSR ACTIVE SO NS162000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ANSRE4ACTIVE SO NS162000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595ANSRG4ACTIVE SO NS162000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595APWR ACTIVE TSSOP PW162000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595APWRE4ACTIVE TSSOP PW162000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595APWRG3ACTIVE TSSOP PW162000Green (RoHS

& no Sb/Br)

CU SN Level-1-260C-UNLIM

SN74LV595APWRG4ACTIVE TSSOP PW162000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595APWT ACTIVE TSSOP PW16250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595APWTE4ACTIVE TSSOP PW16250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LV595APWTG4ACTIVE TSSOP PW16250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Addendum-Page 1

Orderable Device Status (1)Package Type Package

Drawing Pins Package Qty Eco Plan (2)Lead/

Ball Finish

MSL Peak Temp (3)Samples

(Requires Login)

SN74LV595ARGYR ACTIVE VQFN RGY163000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

SN74LV595ARGYRG4ACTIVE VQFN RGY163000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check https://www.wendangku.net/doc/bb1123603.html,/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LV595A :

?Automotive: SN74LV595A-Q1

?Enhanced Product: SN74LV595A-EP

NOTE: Qualified Version Definitions:

Addendum-Page 2

?Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects ?Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LV595ADR SOIC

D 162500330.016.4 6.510.3 2.18.016.0Q1SN74LV595ANSR SO

NS 162000330.016.48.210.5 2.512.016.0Q1SN74LV595APWR TSSOP

PW 162000330.012.47.0 5.6 1.68.012.0Q1SN74LV595APWR TSSOP

PW 162000330.012.4 6.9 5.6 1.68.012.0Q1SN74LV595APWRG3TSSOP

PW 162000330.012.47.0 5.6 1.68.012.0Q1SN74LV595APWT TSSOP

PW 16250330.012.4 6.9 5.6 1.68.012.0Q1SN74LV595ARGYR VQFN RGY 163000

330.012.4 3.8 4.3 1.58.012.0Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74LV595ADR SOIC D162500333.2345.928.6 SN74LV595ANSR SO NS162000346.0346.033.0 SN74LV595APWR TSSOP PW162000364.0364.027.0 SN74LV595APWR TSSOP PW162000346.0346.029.0 SN74LV595APWRG3TSSOP PW162000364.0364.027.0 SN74LV595APWT TSSOP PW16250346.0346.029.0

SN74LV595ARGYR VQFN RGY163000346.0346.029.0