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HF88M04中文资料

King Billion Electronics Co., Ltd

駿 億 電 子 股 份 有 限 公 司

HF88M04

January 16, 2004 Page 1 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

- Table of Contents -

1 Function Description______________________________________________________________

2 2 Features ________________________________________________________________________2

3 Functional block diagram __________________________________________________________3

4 Pin Description __________________________________________________________________4

5 Pad Location ____________________________________________________________________5 6

Device Operation _________________________________________________________________6

6.1 Retrieve data in Data File ____________________________________________________________8 6.2 Loading the Address Counter _________________________________________________________8 6.3 Sequential Read Mode and Auto Increment of Address Counter ____________________________9 6.4 Output data to External I/O __________________________________________________________9 6.5 Reading Input pin status _____________________________________________________________9 6.6

Retrieving the Contents of Expansion I/O registers _______________________________________9

7 Timing Diagrams ________________________________________________________________10

7.1 Data File Read Cycle _______________________________________________________________11 7.2 Interrupted by I/O when Loading Address Counter______________________________________12 7.3 Setting and Reading the I/O Mode for P0 and P1________________________________________13 7.4 Reading P0 and P1 in Mixed-I/O Mode ________________________________________________14 7.5 Reading the input pins ______________________________________________________________15 7.6

Output to P0 and P1 Ports___________________________________________________________16

8 Absolute Maximum Rating ________________________________________________________16 9 AC Electrical Characteristics ______________________________________________________16 10

DC Electrical Characteristics ____________________________________________________17

11 Application Circuit Diagram _______________________________________________________17 12

Updated History _______________________________________________________________19

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King Billion Electronics Co., Ltd

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HF88M04

January 16, 2004 Page 2 of 19

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1 Function Description

The HF88M04 is a command interfaced 512K x 8 bit Mask ROM. It features command mode interface with external CPU or MCU. In other words, it uses only 8-bit data bus and a few additional control pins to load addresses and provide the ROM access as well as expansion I/O ports capability. This design not only reduces pin count required to access data in ROM dramatically but also allows for systems expansion to higher capacity memories while using the existing board design. The application areas include voice, graphic, data storage in consumer product.

2 Features

9 Data File Mode with only 11 pin interface

9 Sixteen-bit Expansion I/O pins with three-state mode 9 V oltage range 2.4V ~ 5.5V 9 Organization

- Memory Cell Array: 512K x 8

9 Sequential Read Operation in Data File Operation Mode - Sequential Access : 120ns (min.) at V DD = 5.0V 9 Command/Address/Data Multiplexed I/O port 9 Low Operation Current (Typical) - 10μA Standby mode Current - 10mA Active Read Current 9 Package bare chip, PLCC32

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King Billion Electronics Co., Ltd

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HF88M04

January 16, 2004 Page 3 of 19

V1.11

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3 Functional block diagram

MEMORY CELL ARRAY SENSE AMP.

OEn X BUFFER &DECODER [D7.. D0]

CONTROL LOGIC

Y BUFFER &DECODER

CEn [P00..P07][P10..P17]

[AC18..A0]

AC0AC1AC2

P0DIR0P1DIR1

WEn

RS2..RS0

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King Billion Electronics Co., Ltd

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HF88M04

January 16, 2004

Page 4 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use. 4 Pin Description

HF88M04-PLCC32

11298765429282427330

312232513

1415181920

21

2232161121726P01P02P03P04P05P06P07P 14P16P15OE P10P 17R S 1

R S 2R S 0P12P13D0

D 1D 2D 4D 5D 6

D7

CE V D D V S S W E P00D 3P11

Symbol Pin No. I/O Description VDD 32 P Positive power supply input pin. VSS 16 P Gound pin. CEn 22 I The CEn (Chip Enable) input is the device selection and power control for

internal Mask ROM array. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode and the contents of the ROM and registers can be accessed. Please note that only accesses to the internal registers are inhibited, but the status of I/O registers are not affected by the CEn pin and will remain unchanged. CEn is also useful to uniquely select a certain device for applications where multiple-chip array is required.

WEn 1 I WEn controls writing to internal registers such as the Output Port Registers,

Direction Registers, Address Counter and Data on D7 ~ D0 are latched on the rising edge of the WE pulse. The WEn (Write Enable) input is internally pulled-up to VDD to prevent pin floating. So this pin should stay at ‘1’ state when inactive to prevent unintended current consumption.

OEn 24 I OEn (Output Enable) is the output control which gates ROM array data,

expansion I/O ports, Direction Registers to the data I/O pins D7 ~ D0. The internal Address Counter will automatically increment by one with each rising edge of OEn pin in Sequentially Read mode.

RS2~RS0 I Register Select pins RS2 ~ RS0 for accessing ROM data, Address Counter,

as well as expansion I/O ports.

P17 ~ P10 I/O Bi-directional I/O port P1. P07 ~ P00 I/O Bi-directional I/O port P0.

D7 ~ D0 21 ~ 17, 15 ~13 IO The Bi-directional Data I/O pins are used to input Starting Address, setting

the Expansion I/O direction and Output Registers, and to output ROM array

data during read operations, contents of I/O Registers and status of input pins. The D7 ~ D7 float to high-impedance when the chip is deselected (CEn high) or when the outputs are disabled.

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King Billion Electronics Co., Ltd

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HF88M04

January 16, 2004

Page 5 of 19

V1.11

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5 Pad Location

P16

P15

P10

P11P13

P12D7

D6

D5

D4

D3

D2

D1

D0

P00

P01

P02

P03

NC

NC

NC

NC

P04

P05

P06

P07

P14

P17

WEN

VDD

VDD

VDD

RS2

RS1

RS0

OEN

CEN

VSS

VSS

VSS

Die Size: X= 2890 μm, Y=2670 μm, and substrate is connected to GND.

Pad No. Pad Name X Coord. Y Coord. Pad No. Pad Name X Coord. Y Coord. 1 P07 108.33 2431.7521 D5 2058.62 109.142 P06 108.33 2244.3122 D6 2245.78 109.14

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King Billion Electronics Co., Ltd

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HF88M04

January 16, 2004

Page 6 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use. Pad No. Pad Name X Coord. Y Coord. Pad No. Pad Name X Coord. Y Coord.

3 P05 108.33 2057.0323 D7 2745.87 105.79

4 P04 108.33 1869.5924 CEN 2745.87 229.55

5 NC 108.33 1682.3625 P12 2745.87 355.17

6 NC 108.33 1494.9226 OEN 2745.8

7 480.327 NC 108.33 1307.7427 P13 2759.4

8 1365.838 NC 108.33 1119.3428 P11 2759.48 1491.74

9 P03 108.33 932.1729 P10 2759.48 1617.6310 P02 108.33 744.7330 P15 2748.87 2427.9211 P01 108.33 557.4531 P16 2748.87 2555.1312 P00 108.33 370.0132 RS1 2107.66 2566.9213 D0 108.33 182.7233 RS2 1920.22 2566.9214 D1 395.97 109.1434 VDD 1578.76 2513.7215 D2 583.13 109.1435 VDD 1404.34 2513.7216 GND 997.39 220.7136 VDD 1229.92 2513.7217 GND 1242.34 140.9137 WEN 1029.23 2552.318 GND 1521.38 108.0938 RS0 841.19 2552.319 D3 1684.02 109.1439 P17 495.57 2552.320 D4 1871.18 109.1440 P14 308.13 2552.3

6 Device Operation

The device provides the capability of accessing the contents of ROM array by external MCU not through

standard address and data bus configuration but through minimal number of 8-bit data bus and control pins. Only 11 pins D7 ~ D0, CEn, OEn, WEn are required to use the device as a Data File device. By fixing the RS2 to ‘0’, only CEn, WEn, OEn and D0 ~ D7 are required to access the ROM array data. The CEn pin is device selection pin to uniquely select one device when more than one device are used in parallel and control the access to Mask ROM contents and internal registers. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode. Therefore, when accessing contents of ROM is not intended, CEn should stay at ‘1’ to conserve the power.

In addition to Data File mode, the device also provide the expansion I/O capability. Two ports of I/O pins (8 bit each) are provided. The I/O ports can be configured to function as output pin or high-impedance input pins. Only 14 pins, CEn, WEn, OEn, RS2, RS1 and D0 ~ D7 are required to provide the Data File function and full access to two I/O ports.

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King Billion Electronics Co., Ltd

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HF88M04

January 16, 2004

Page 7 of 19

V1.11

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There are seven internal registers used to provide the functionality of Data file as well as Expansion I/O capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except AC2. AC2 ~ AC0 are write-only and constitute the complete 19-bit Address Counter used as pointer to the data. While the P0, P1, DIR0 and DIR1 can be read as well as written. Their initial values are as indicated in the following table. When RS2 = ‘0’, the RS1 ~ RS0 are ignored, the Address Counter can be loaded or contents of Data File can be read. This is to reduce the required pin needed for external MCU to interface with the Device and also simplify the procedure for loading the address counter.

The P0, P1, DIR0, and DIR1 are used for expansion I/O registers. The P0 and P1 are output registers of Expansion I/O and DIR0 and DIR1 are the Direction Registers that determine the I/O mode of P0 and P1. Each pin can be configured as output or input mode individually by setting or resetting the corresponding pin of the DIR registers. Initially, both P0 and P1 are default to input mode at ‘Hi’ state.

DIR00

RS = 100 & OEn = '0'RS = 101 & OEn = '0'RS = 111 & OEn = '0'

RS = 110 & OEn = '0'

D0

10

Q D

Q D

P00

DIR00

10

Q

D

DIR10Q

P10D

The accesses to the internal registers will be inhibited when CEn is ‘1’. However, the status of internal registers, such as expansion I/O ports, will not be affected. For example, if a certain pin is in output mode and driving ‘Hi’, it will not change when CEn pin goes to ‘1’ state. Therefore, the users are advised to take care of the power down condition of I/O ports when entering sleep mode to prevent unnecessary power drain.

RS 2RS 1RS 0 Symbol Type Description

Initial Value

R Read data by Indirect access

AC2 W Address latch 2 for A18 ~ A16 “--------“ 0xx AC1 W Address latch 1 for A15 ~ A8

“--------“

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HF88M04

January 16, 2004

Page 8 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use. AC0 W Address latch 0 for A7 ~ A0 “--------“ 100 P0 R/W Port 0 Output Register “11111111“ 101 DIR0 R/W Direction Register 0 “00000000“ 110 P1 R/W Port 1 Output Register “11111111“ 111

DIR1

R/W

Direction Register 0

“00000000“

6.1 Retrieve data in Data File

Accesses to the ROM contents, expansion I/O, Address Counter and Direction registers are made through 8 Data I/O pins – D7 ~ D0. With Register Selection RS = “0xx”, the starting addresses can be written through Data I/Os by bringing WEn to low and back to high. Addresses are latched on the rising edge of WEn.

Once the starting address of data block is latched into the Address Counter, data may be read out by sequentially pulsing OEn with CEn staying low. When at ‘0’, the OEn gate the data of the selected address unto Data I/O pin D7 ~ D0. With the rising edge of OEn, the internal Address Counter is incremented by one automatically.

6.2 Loading the Address Counter

Before the data can be retrieved, the Address Counter must be initialized with the starting address, then the contents of ROM pointed to by Address Counter (AC) can be accessed through D7 through D0. In order to simplify the procedure of loading 19-bit Address Counter (AC), a internal pointer is implemented and used to point to next register to write in the up to three-cycle address loading sequence. Initially, with RS = “0xx” CEn goes from ‘1’ to ‘0’ and the AC pointer is initialized. The pointer is then incremented to point to next register with falling edge of each WEn pulse. So when randomly accessing data within a 256-byte page, or within a 64K-byte block mode, then only one or two-cycle address reload process is needed to access different locations within a page or block.

The Address Counter pointer will be held in reset state in the following conditions: 1. When CEn is '1' (the device is deselected).

2. By the Read pulse (OEn is '0') and RS2 = '0' (ROM is being accesses).

The inclusion of the 3rd condition is to force the address loading to start from LSB of Address Counter once the read cycle is initiated. However, the AC Pointer will not be reset when reading or writing from/to expansion I/O registers (P0, P1, DIR0, DIR1). This design is useful in certain application scenarios where in the midst of the multi-byte address loading process, an interrupt to the MCU main loop occurs. And in the interrupt service routine, manipulation of expansion I/O registers is performed, i.e., key board is scanned using P0 and P1. When the execution of program returns to main loop after

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HF88M04

January 16, 2004

Page 9 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use. interrupt service routine completed, the loading of address can still resume from where it was interrupted.

6.3 Sequential Read Mode and Auto Increment of Address Counter

With each read access to the ROM data (RS = “0xx”), the Address Counter is incremented automatically by one with rising edge of OEn to facility sequential access to a block of ROM data and avoid repeated loading of addresses.

6.4 Output data to External I/O

The device’s 16-bit Expansion I/O capability provides additional I/O ports for applications where the I/O pin are heavily used. To use as a certain pin as output pin, the corresponding bit in Direction Register must be set to ‘1’. Please refer to the following example where output 0x00 to P0 to ‘0’ is intended. 1. Set RS to “101” (DIR0).

2. Keep D7 ~ D0 at 0xff (all bits in output mode).

3. Pulse the WEn to low then high to write to write contents of D-bus to DIR0.

4. Set RS to “100” (P0 Output Register).

5. Set D7 ~ D0 to 0x00.

6.

Pulse the WEn to low then high to write contents of D-bus to P0 and drive all bits in P0 to low.

6.5 Reading Input pin status

To use expansion I/O ports as input pins and read the status from them, the corresponding bit in direction register must be set to ‘0’. Please see the following example where reading inputs from of P1 is intended. 1. Set RS to “111” (DIR1). 2. Set D7 ~ D0 to 0x00.

3. Pulse the WEn to low then high to set DIR1 to all High-Impedance input mode.

4. Set RS to “110” (P1 Output Register).

5. Pulse the OEn to low.

6.

Read P1 then set the OEn back to high.

There is one thing should be noted. For any unused (open) expansion I/O pin, it is advisable to set the port to output mode either at ‘0’ or ‘1’ state to prevent it from floating or fix it at VDD or VSS if it is set to input mode. Otherwise, the noise might cause the unnecessary power consumption.

6.6 Retrieving the Contents of Expansion I/O registers

The contents of all four registers can be read through data bus. The ability to access the contents of

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HF88M04

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registers avoids the necessity of using the RAM as mirror to keep the current status of latches in applications. However, extra care should be taken when reading P0 and P1. To read the contents of P0 and P1, the DIR0 and DIR1 should be set to output mode. Otherwise, the pin status instead of P0 and P1 will be read. The same precaution should be applied in Read-Modify-Write sequence that read back the contents of the output register of output mode pins and input status of input mode pins.

7 Timing Diagrams

Symbol Parameter Min.Typ. Max. Unit

T CE Chip selected to active width 0 50 - ns T WEL WEn active low width 100 - - ns T WEH WEn inactive low width 100 - - ns T DHeld Written data hold time 50 - - ns T OLZ Read-Write mode transient time 200 - - ns T ACE ROM data file available time 50 - - ns T OEL Output enable low duty for access ROM 250 - - ns T OEH Output enable low duty for access ROM 150 - - ns T CEHeld Chip selection signal holding time 50 - - ns T ACER Register data available time 30 - - ns T ORL Output enable low duty for access register 100 - - ns T ORH Output enable low duty for access register 100 - - ns T RCEL RS signal setup time 50 - - ns T RCEH RS signal hold time 50

- - ns

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HF88M04

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7.1 Data File Read Cycle

CEn

WEn

OEn

RS[2:0]

D[7:0]Internal Memory Address AC0

AC1AC234

56

07

Internal Memory Data xxxx34xx5634075634

1E

ZZ

ZZ

3C

ZZ

78

ZZ

1E ZZ

3C ZZ

78

ZZ 075635

0756********RS2=0, RS1 and RS0 can be any value.

Data File Read Cycle

t ACE

t CE

t WEL

t WEH

t DHeld

t OLZ

t OEL

t OEH

t RCEL

t RCEH

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HF88M04

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7.2 Interrupted by I/O when Loading Address Counter

CEn

WEn

OEn

P0_Data D[7:0]Internal Address AC0

3Dh

00h

xxxx3Dh 55h

ZZ

ZZ

BBh

78h

xx783Dh 00783Dh

Interrupted by I/O when Loading Address Counter

P0_DIR P1_Data P1_DIR RS[2:0]

000b

101b 111b 100b 110b 00h

00h

FFh 00h

FFh FFh

FFh

000b

00h

AC1

AC2t ORL t ACER

t ORH

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7.3 Setting and Reading the I/O Mode for P0 and P1

C E n

W E n

O E n

P 0_D a ta D [7:0]F 0h F 0h

0F h

Z Z

Z Z

S e ttin g a n d R e a d in g th e I /O M o d e fo r P 0 a n d P 1

P 0_D IR P 1_D a ta P 1_D IR R S [2:0]101b 111b 0F h F F h

0F h

00h F F h

00h t O R L

t A C E R

000b F 0h

101b 111b

t O R H

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7.4 C E n

W E n

O E n

P 0_D ata D [7:0]F 0h F 5h

A F h

Z Z

Z Z

R ea d in g P 0 a n d P 1 in M ix ed -I/O M o d e

P 0_D IR P 1_D ata P 1_D IR R S [2:0]101b 111b 0F h F F h

0F h

00h F F h

00h t O R L

t A C E R

000b F 0h

100b 110b

t O R H

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7.5 Reading the input pins

C E n

W E n

O E n

P 0_D a ta D [7:0]00h 55h

A A h

Z Z

Z Z

R e a d in g th e In p u t P in s

P 0_D IR P 1_D a ta P 1_D IR R S [2:0]101b 111b 00h F F h

00h

0F h F F h

F 0h 000b 00h

100b 110b

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This specification is subject to change without notice. Please contact sales person for the latest version before use. 7.6 Output to P0 and P1 Ports

C E n

W E n

O E n

P 0_D a ta D [7:0]F F h 55h

A A h

Z Z

Z Z

O u tp u t to P 0 a n d P 1 P o rts

P 0_D IR P 1_D a ta P 1_D IR R S [2:0]101b 111b F F h F F h F F h

00h F F h 00h 000b F F h

100b 110b

55h

A A h

8 Absolute Maximum Rating

Items Symbol

Rating

Supply V oltage V DD -0.3 to 6 V

Input V oltage V IN -0.3 to Vdd+0.3 V Operating Temperature T OPR -5 to 70 °C Storage Temperature T STR

-55 to 125 °C

9 AC Electrical Characteristics

READ CYCLE

There are two ways of accessing the ROM data. The first one is to assert the valid address on the Address Bus, then assert CEn “low” to enable the ROM array. The access time in this mode is specified as t ACE . The advantage of this access mode is that power consumption can be lowered. The second access mode keeps the CEn “low” while changes the addresses to access the contents of ROM data. The

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V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use. access time in this way is specified as t AA . In this device, the Address Access Time decrease monotonically with increasing voltage, and it is shorter than Chip Enable Access Time when the Operation V oltage is higher then 4.5 V . Therefore in V op higher than 4.5 V olts, it is more advisable to use the Address Access Mode to achieve faster access to ROM data when the power consumption is not a concern.

Item Symbol

2.4V

3.0V 3.3V 3.6V

4.5V

5.0V 5.5V Unit Remark

Chip Enable Access Time t ACE 280190170150150190210ns Min Address Access Time t AA 240210210210200190180ns Min

10 DC Electrical Characteristics

(V SS = 0V , V DD = 5.0 V , T OPR = 25°C unless otherwise noted)

Parameter Symbol Min. Typical Max. Unit Condition

Supply V oltage V DD 2.4 - 5.5 V Operating Current I DD - 10 - mA No load Standby Current I DD - 10 - μA No load

Input voltage V IH

V IL 2/3 0 - - 1 1/3 V DD V DD = 4V ~ 6V

Input current leakage I IL - - +/- 10μA P0, P1 Output High V oltage

V OH 2.4 - - V I OH = 0.4 mA P0, P1 Output Low V oltage

V OL - - 0.4 V I OL = 2.1 mA D Output High V oltage

V OH 2.4 - - V I OH = 14 mA D Output Low V oltage

V OL - - 0.4 V I OL = 3 mA 11 Application Circuit Diagram

This application circuit illustrates that how KB83760 MCU uses two external HF88M04s for ROM

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expansion as well as key board scan functions.

V DD

V V V DD

V DD

C 7

C 6R 1S E G 65P R T 110

C 5R 2S E G 64P R T 111C 4R 4S E G 63P R T 112C 3O E n O E n

S E G 62P R T 113C 2R 3S E G 61P R T 114C 1C E 1n C E 2n S E G 60P R T 115D 0

D 7

D 0

D 7S

E G 59P R T 116S E G 58P R T 117S E G 57P R T 100S E G 56P R T 101S E G 55P R T 102S E G 54P R T 103S E G 53P R T 104S E G 52P R T 105S E G 51P R T 106S E G 50P R T 107S E G 49R S 0S E G 48R S 1S E G 47R S 2C 7S E G 46O E n C 6S E G 45W E n C 5S E G 44C E 1n C 4S E G 43C E 2n

C 3S E G 42C 2S E G 41

D 0

C 1

S E G 40D 1S E G 39D 2S E G 38D 3S E G 37D 4S E G 36D 5S E G 35D 6S E G 34D 7S E G 33K T O N E S E G 32S D O S E G 31D T M F O R 1

S E G 30M U T E

S E G 29S E G 28S X I

S E G 27S X O S E G 26T S T P S E G 25F X I R 2

S E G 24F X O S E G 23R S T P S E G 22O P O S E G 21O P I P S E G 20O P I N S E G 19D A O

R 3

R 4

V O

R 5

S E G 66S E G 18

S E G 67S E G 17S E G 68S E G 16S E G 69S E G 15S E G 70S E G 14S E G 71S E G 13S E G 72S E G 12S E G 73S E G 11S E G 74S E G 10S E G 75S E G 9S E G 76S E G 8S E G 77S E G 7S E G 78S E G 6S E G 79S E G 5S E G 80S E G 4S E G 81S E G 3S E G 82S E G 2S E G 83S E G 1S E G 84S E G 0S E G 85CO M15S E G 86CO M14S E G 87CO M13S E G 88CO M12S E G 89CO M11S E G 90CO M10S E G 91CO M9S E G 92CO M8S E G 93CO M7S E G 94CO M6S E G 95CO M5CO M31CO M4CO M30CO M3CO M29CO M2CO M28CO M1CO M27CO M0CO M26CO M25CO M24CO M23CO M22CO M21CO M20CO M19CO M18CO M17CO M16P WMN P WMP

R5D1

D2RS 0WE n D3D4RS 2

D5RS 1D6D1

D2RS 0

WE n D3D4RS 2

D5RS 1

D6U2

HF88M04-P L CC32

11298765

4

29282427330312232513

14

15181920

212232*********P 01P 02P 03P 04P 05P 06P 07P 14

P 16P 15O E P 10P 17RS 1RS 2RS 0P 12P 13D 0

D1

D2D4D5D6

D 7

C E V D

D V S S W

E P 00D3P 11U3

HF88M04-P L CC32

11298765

4

29

28242733031223251314

1518192021

2232161121726P 01P 02P 03P 04P 05P 06P 07P 14

P 16

P 15O E P 10P 17RS 1RS 2RS 0P 12P 13D 0

D1

D2D4D5D6D 7

C E V D

D V S S W

E P 00D3P 11R2330K

R3330K

R4330K

R5

330K

U1K B 83760

727313413013113213316171819142143144

979899100646362612324252627282930313233343536374445464748

49

5051525354555657585960711011021031041051061071081091101111121131141151161221231241251261271281291110151413121411401391382221208584769392878696

89818283888990919495

1371361354142436566676869707475777879801171181191201211234567383940145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190

S E G 42S E G 41L V 2CO M0L C1L C2L V 1CO M29CO M30CO M31S E G 95G ND V O

D A O

S E G 17S E G 16S E G 15S E G 14S E G 50S E G 51S E G 52S E G 53S E G 91S E G 90S E G 89S E G 88S E G 87S E G 86S E G 85S E G 84S E G 83S E G 82S E G 81S E G 80S E G 79S E G 78S E G 77S E G 70S E G 69S E G 68S E G 67S E G 66

S E G 65

S E G 64S E G 63S E G 62S E G 61S E G 60S E G 59S E G 58S E G 57S E G 56S E G 55S E G 54S E G 43S E G 13S E G 12S E G 11S E G 10S E G 9S E G 8S E G 7S E G 6S E G 5S E G 4S E G 3S E G 2S E G 1S E G 0CO M15CO M14CO M8CO M7CO M6CO M5CO M4CO M3CO M2CO M1CO M24CO M23CO M28CO M27CO M26CO M25L V G L R0L R1L R2S E G 92S E G 93S E G 94S E G 29S E G 30S E G 38S E G 21S E G 22S E G 27S E G 28S E G 18

CO M21CO M22S E G 33S E G 32S E G 31S E G 26S E G 25S E G 24S E G 23S E G 20S E G 19

L R3L R4L V 3S E G 73S E G 72S E G 71S E T 49S E G 48S E G 47S E G 46S E G 45S E G 44S E G 40S E G 39S E G 37S E G 36S E G 35S E G 34CO M13CO M12CO M11CO M10CO M9P WMP P WMN CO M16CO M17CO M18CO M19CO M20S E G 76S E G 75S E G 74O P I N O P I P O P O R S T P F X O F X I T S T P S X O S X I V D D M U T E D T M F O S D O K E Y T O N E P R T D 7P R T D 6P R T D 5P R T D 4P R T D 3P R T D 2P R T D 1P R T D 0P R T C 7P R T C 6P R T C 5P R T C 4P R T C 3P R T C 2P R T C 1P R T C 0P R T 107P R T 106P R T 105P R T 104P R T 103P R T 102P R T 101P R T 100P R T 117P R T 116P R T 115P R T 114P R T 113P R T 112P R T 111P R T 110

C11u F

C10

1u F C21u F

C31u F

C4

1u F

C5

1u F

C61u F

C7

1u F C8

1u F C9

1u F

D1

1N4148

2

1

D21N4148

2

1

D31N41482

1

D41N41482

1

D51N41482

1

D61N4148

2

1

1N4148

2

1

K 1K 2R1330K

K 3K 4

K 5

K 6

K 7

K 8K 9K 10K 11

K 12

K 13

K 14

K 15K 16K 17K 18

K 19

K 20

K 21

K 22K 23K 24K 25

K 26

K 27

K 28

K 29K 30

K 31

K 32

K 33

K 34

K 35

P a u s e

5

E r a s e

N a m e

H O L D

M 7

A u t o

D O W N

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6

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#

4

1

8

M 10

M 1

2

M u t e

7

H F

M 6

F l a s h

P G M D i a l

M 2

M 9

M 5

3

M 4

9

M 8

R e d i a l

M 3

元器件交易网https://www.wendangku.net/doc/b72259311.html,

King Billion Electronics Co., Ltd

駿 億 電 子 股 份 有 限 公 司

HF88M04

January 16, 2004 Page 19 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

12 Updated History

Version Date Update Description 1.10 2003/8/27 Timing diagrams modified. 1.11 2004/1/16 Add the die size

元器件交易网https://www.wendangku.net/doc/b72259311.html,

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