常用分频器设计
(含0.5hz、1hz、2hz、100hz、1khz、100khz、1MHZ)
一、原理图
二、程序(输入频率为50MHZ)
module divclk(clk,div05hz,div1hz,div2hz,div100hz,div1khz,div10khz,div1mhz);
input clk;
output div05hz,div1hz,div2hz,div100hz,div1khz,div10khz,div1mhz;
reg div05hz,div1hz,div2hz,div100hz,div1khz,div10khz,div1mhz;
reg[4:0] count1;
reg[14:0] count2;
reg[8:0] count3;
reg[7:0] count4;
reg[2:0] count5;
reg[12:0] count6;
reg[10:0] count7;
always @(posedge clk)
begin
if(count1=='d25)
begin div1mhz<=~div1mhz;count1<=0;end
else
begin count1<=count1+1'b1;end
if(count2=='d25000)
begin div1khz<=~div1khz;count2<=0;end else
begin count2<=count2+1'b1;end
if(count6=='d2500)
begin div10khz<=~div10khz;count6<=0;end else
begin count6<=count6+1'b1;end
end
always @(posedge div1khz)
begin
if(count3=='d500)
begin div1hz<=~div1hz;count3<=0;end else
begin count3<=count3+1'b1;end
if(count4=='d250)
begin div2hz<=~div2hz;count4<=0;end else
begin count4<=count4+1'b1;end
if(count5=='d5)
begin div100hz<=~div100hz;count5<=0;end else
begin count5<=count5+1'b1;end
if(count5=='d1000)
begin div05hz<=~div05hz;count7<=0;end else
begin count7<=count7+1'b1;end
end
endmodule