UG516S7448JJ-PL中文资料
P r e l m i n a r y
U N I E N T I A L
SYNCHRONOUS DRAM MODULE
128M Bytes (16M x 72 bits)
PC100-COMPATIBLE SDRAM Unbuffered DIMM
based on 9 pcs 16M x 8 SDRAM with LVTTL, 4 banks & 4K Refresh
SS
43 V SS 85 V SS 127 V SS 2DQ0 44 NC 86 DQ32 128 CKE03DQ1 45 /CS2 87 DQ33 129 NC 4DQ2 46 DQMB2 88 DQ34 130 DQMB65DQ3 47 DQMB3 89 DQ35 131 DQMB7 6V DD 48 NC 90 V DD 132 NC (A13)7DQ4 49 V DD 91 DQ36 133 V DD 8DQ5 50 NC 92 DQ37 134 NC 9DQ6 51 NC 93 DQ38 135NC 10 DQ7 52 CB2 94 DQ39 136 CB611DQ8 53 CB3 95 DQ40 137 CB712 V SS 54 V SS 96 V SS 138 V SS 1 V PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
ORDERING INFORMATION
INTERNAL BANK REF. SDRAM
PACKAGE PLATING
UG516S7448JJ-PH UG516S7448JJ-PL
4 Banks
8K
TSOP-II
Gold
FEATURES
ABSOLUTE MAXIMUM RATINGS
REVISION HISTORY
Rev - A Product brief released.
Aug 22 , 2001
PART NO.? Voltage Relative to GND -0.3 to + 4.6V ? Operating Temperature 0 to + 70°C ? Storage Temperature -55°C to + 125°C ? Short circuit Output Current 50mA ? Power Dissipation 9W
? PC100 Compatible unbuffered module
?JEDEC-standard 168pin, dual inline memory module (DIMM)?Utilizes 100 MHz SDRAM components ? 128MB (16 Meg x 72)
?Single +3.3V ± 10% power supply
?Fully synchronous; all signals registered on positive edge of system clock
?Internal pipelined operation; column address can be changed every clock cycle
?Internal SDRAM banks for hiding row access/precharge ?Programmable burst lengths: 1, 2, 4, 8 or full page
?Auto Precharge, includes concurrent auto precharge,and Auto Refresh Modes ?Self Refresh Mode
?64ms, 4,096-cycle refresh
?LVTTL-compatible inputs and outputs ?Serial presence-detect (SPD)
r e r E N C O N F I D E N T Functional Block Diagram
A0 ~ An, BA0 & 1
RAS CAS
WE SDRAM U0 ~ U8SDRAM U0 ~ U8SDRAM U0 ~ U8SDRAM U0 ~ U8SDRAM U0 ~ U8
10V DD
Vss
To all SDRAMs Capacitor &Physical Dimension
0.050
Detail C
0.250
Detail A
0.250
Detail B
0.100 Max
0.157 M i n
0.050 ± 0.0039
CK1/3
pF
U0/U4U5/U8CK0/2
U1/U2U6/U3U7
10W
10W
Tolerances : ± 0.005 unless otherwise specified Units : Inches