Crosstalk Cancellation of DDR3 Memory Channel for over 1600 Mbps Data Rate

Crosstalk Cancellation of DDR3 Memory Channel for over 1600 Mbps Data Rate

Junwoo Lee, Sungwoo Han, Hyo Seog Ryu, Sang Yeop Kim, Jongho Kang, Kunwoo Park, and Joongsik Kih

# Advanced Design Team 1, Hynix Semiconductor

Icheon, Korea

junwoo.lee@https://www.wendangku.net/doc/be3914751.html,

Abstract—In this paper, we propose crosstalk cancellation methodology for high speed DDR3 memory channel whose data rate is 1600 Mbps or faster. In DDR3, DQ signal still adopts microstrip line in the motherboard in order to achieve low cost. The propagation velocity of even-mode is different from that of odd-mode in the microstrip line, which results in skew among DQs and between DQ and data strobe (DQS) as well. This crosstalk reduces timing margin a lot and it is not endurable at the high data rate. The proposed method successfully suppresses the crosstalk and it is cost effective compared with using stripline for DQ and DQS in the motherboard.

I.I NTRODUCTION

The data rate of DRAM has been dramatically increased and now it reaches up to 1600 Mbps in the DDR3 system [1]. As the data rate becomes higher, signal integrity of DRAM channel limits the speed performance. Only one dual in-line memory module (DIMM) is allowed per channel at 1600 Mbps while two DIMM per channel is possible below 1600 Mbps because of signal integrity (SI) issues. Also it is generally agreed that present DDR3 channel topology is not adequate to achieve over 1600 Mbps data rate. One of critical SI issues of DDR3 system is the channel crosstalk. The crosstalk occurs at the vias, connector, and packages but mostly it comes from the microstrip line in the motherboard. Figure 1 shows channel topology of DDR3 DQ and DQS. In DIMM, the DQ and DQS signals are routed using stripline. However motherboard still adopts microstrip line for DQ and DQS because of cost. It is not reasonable to add two more layers to the motherboard just for the memory interface. Sixteen DQs and DQS/DQSB are routed in parallel which are coupled transmission line structure. Since DQ pattern is random, one DQ can have same data with others what is called even mode or different data from others what is called odd mode. The propagation velocity of even mode is different from that of odd mode in the case of microstrip line, which results in skew and timing jitter. The length of microstrip line is around 5000 mil which is around 70 % of total channel length as shown in Fig. 1. Thus the crosstalk from the motherboard trace occupies significant portion of timing budget of DDR3 system.

Simple but powerful way to reduce the crosstalk effect at the motherboard is to use stripline just like DIMM does. There is strong possibility that next generation memory DDR4 will accept stripline at the motherboard. However cost is still problem if we remind low cost is primary concern in the computer system. In this paper, we propose a methodology

Fig. 1. Channel topology of DDR3 system

of reducing the crosstalk effect of the microstrip lines effectively by inserting mutual capacitance between neighbouring DQs. The simulation results show that proposed method can achieve comparable reduction of crosstalk with stripline method.

II.E FFECT OF CHANNEL CROSSTALK ON THE DDR3

PERFORMANCE

A.Propagation Velocity of even mode and Odd mode

The propagation velocity of transmission line can be expressed as [2]

e

p

c

v

ε

=(1)

where εe is the effective dielectric constant of the transmission line and c is the speed of light in the free-space. Since some of the field lines are in the dielectric region and some are in air for the microstrip line, the effective dielectric constant is higher than 1 and less than relative permittivity of dielectric material. The effective dielectric constant of odd-mode is different from that of even-mode because the filed lines of odd-mode differ from those of even-mode. The even-mode effective permittivity can be expressed as [3]

)1

(

1?

+

=r

e

ee

qε

ε(2) where q e is the dielectric filling factor and εr is relative dielectric constant of dielectric material. The odd-mode

337

effective permittivity is the same as (2) with the replacement of subscript “e ” by “o ”. For the stripline, the filling factor in (2) is equal to 1 both for the even-mode and odd-mode. Thus the propagation velocity of even-mode is the same with that of odd-mode for the stripline. The difference of effective dielectric constant between odd-mode and even-mode for the microstrip line is calculated in Table 1 [3]

TABLE I

C OMPARISON OF EFFECTIVE PERMITTIVITY FOR εR

=2.35 AND S /H =1.0

Dimension Effective dielectric constant W/H Even-mode (εee ) Odd-mode (εoe ) 0.05 1.82 1.69

0.10 1.83

1.70

0.25 1.87 1.70

0.50 1.91 1.72

1.00 1.97

1.75

where W is line width, H is dielectric height, and S is line to line space. We can see that effective dielectric constant of odd-mode is smaller than that of even-mode which means odd-mode velocity is faster than even-mode.

B. Simulation of tDQSQ due to Crosstalk

DDR3 has differential data strobe signals DQS and DQSB per DQ byte. Data strobe is used to capture the input data signal as a common system clock does in a pure synchronous system. Thus timing relationship between DQS and DQ is very important. DQS, DQSB to DQ skew is called tDQSQ parameter and the maximum value is restricted by the specification [4]. Figure 2 shows block diagram of DRAM input buffer side. For WRITEs, the data strobes are center-aligned relative to data and they are edge-aligned with the data for READs.

Since data strobe signals are differential, they can be regarded as an odd-mode signal all the time while DQ can be either in odd-mode or in even-mode depending on the data pattern. It means that tDQSQ can be substantially degrades due to the crosstalk from the motherboard trace. In order to evaluate the effect of the crosstalk on the DDR3 performance, tDQSQ for one byte of DQ has been simulated. Considering even-mode and odd-mode delay difference, the same pseudo random bit sequence (PRBS) signal is applied to DQ0, DQ1,

Fig. 2. Block diagram of DRAM input buffer

DQ2, DQ4, DQ5, DQ6, and DQ7 but the inverse signal of that is applied to DQ3 meaning that DQ3 is odd-mode signal and the others are even-mode signal. A 2 Gbps data rate is used for the simulation. Simulation setup is illustrated in Fig. 3. Figure 4 shows the simulation results. The skew between DQS and DQ has been measured at the every single transition of PRBS data. The minimum and maximum values of measured skews are expressed as an arrow in Fig. 4. For example, DQ0 has tDQSQ value of 50 ps to 160 ps because the skew between DQ0 and DQS is not identical at all the

transition edges. DQ0 has uncorrelated jitter to the DQS because of simultaneous switching output noise (SSO) and inter symbol interference (ISI). Figure 5 describes timing

diagram which helps to understand the simulation results

shown in Fig. 4. If DQS/DQSB edge is exactly aligned with

DQ edge, tDQSQ is zero and that is an ideal position. However DQ has jitters due to various reasons such as SSO and ISI as well as a skew due to the crosstalk or physical length difference, which results in non-zero tDQSQ.

Fig. 3. Simulation setup for the effect of channel crosstalk on the tDQSQ

Fig. 4. Simulation results of tDQSQ

338

Fig. 5. Timing diagram of DQ and DQS which illustrate tDQSQ

In Fig. 4, we can see that DQ3 edge varies around DQS edge while other DQs edges are far away from the DQS edge. It is because DQS is differential signal meaning odd-mode and DQ3 is odd-mode as well. However other DQs are even-mode signal whose propagation velocity is slower than that of odd-mode. Figure 4 shows that about 100 ps out of 240 ps total tDQSQ comes from the crosstalk of microstrip line in the motherboard.

III.P ROPOSED METHOD OF CROSSTALK CANCELLATION FOR

DDR3 MEMORY INTERFACE

As described in chapter II, the crosstalk due to the microstrip line in the motherboard is substantial and it is hard to achieve high frequency data rate over 1600 Mbps using conventional channel topology. An easy way to reduce the crosstalk is to use stripline in the motherboard instead of microstrip line. Figure 6 compares microstrip line case with stripline case. The graph in Fig. 6 shows DQ eye-diagrams at the MCH side shown in Fig. 3 which overlap one another. For the microstrip line, DQ3 and DQ6 show minimum and maximum tDQSQ, respectively as shown in Fig. 4. Thus valid window of 149 ps is determined by DQ3 and DQ6 eye-diagram. In a real situation, there exist both even-mode and odd-mode in each DQ which means the overlay shown in Fig.

6 represents single DQ eye-diagram. For stripline case, we can see that the skew between DQ3 and others reduces. Thus valid window is increased to 186 ps. The valid window measured in Fig. 6 contains correlated jitter to DQS. The tDQSQ of microstrip line case is 242 ps and that of stripline case is 169 ps. Thus we can improve tDQSQ by 73 ps by using strip line in the motherboard.

The stripline structure requires two more layers in the motherboard which increases the cost significantly. Thus we propose alternative way to suppress the even-mode and odd-mode delay difference due to the microstrip line. As shown in Fig. 7, it can be done simply by inserting a capacitor between each neighbouring DQs. Figure 8 illustrated how the inserted capacitor works. In odd-mode, the effective capacitance of each DQ increases by two times of inserted capacitance. In even-mode, the inserted capacitance does not affect the effective capacitance as shown in Fig. 8. Therefore the inserted capacitance increases the odd-mode propagation delay while even-mode propagation delay does not change. Consequently, we can cancel out the even, odd-mode delay difference by increasing odd-mode propagation delay to even-mode propagation delay. The capacitance shown in Fig. 7 and Fig. 8 is inserted by intent and it does not represent parasitic mutual capacitance. Figure 9 shows the simulation results of proposed method. The even, odd-mode skew due to the microstrip line in the motherboard is successfully cancelled out. The tDQSQ decreases to 176 ps by using proposed method which is just 7 ps higher than that of stripline case. The recommended position of the inserted capacitance is near R s placement in DIMM or around DIMM connector pad in the motherboard side shown in Fig. 1 because it will be easy to implement the capacitor using the existing pads or vias. The proposed method can achieve performance improvement of DDR3 system comparable to that achieved by stripline usage in the motherboard yet it costs only additional sixteen

capacitor components.

Fig. 6. Overlay of DQ eye-diagrams for microstrip line case and stripline case

Fig. 7. Proposed method to cancel out the crosstalk from microstrip line

339

340

Fig. 8. Even-mode and odd-mode equivalent of inserted capacitance

Fig. 9. Comparison of tDQSQ between conventional DDR3 channel and proposed method

IV.C ONCLUSION

For the SI point of view, two major factors which occupies timing budget of DDR3 system are SSO and crosstalk due to the microstrip line in the motherboard. In this paper, we proposed effective method of reducing the crosstalk. The simulation results show that the proposed method can suppress the crosstalk almost as much as stripline does. The proposed method is simple, cost effective, and easy to be implemented in a real DDR3 system.

R EFERENCES

[1]“DDR3 SDRAM UBDIMM Technical Datasheet,” Hynix

Semiconductor, Icheon, Korea

[2]David M. Pozar, “Microwave Engineering,” USA, J. Wiley & Sons,

1998, chapter 3

[3]Changhua Wan, “Analytically and accurately determined quasi-static

parameters of coupled microstrip lines,” IEEE Tran. on Microwave

Theory and Techniques., vol. 44, pp. 75-80, Jan. 1996.

[4]“DDR3 SDRAM 1Gb Technical Datasheet,” Hynix Semiconductor,

Icheon, Korea

Cross talk 产生与解决办法(YF)

Cross talk 产生与解决办法 1、OP-B 輸出能力不足 當一條掃描線上所有畫素都要顯示同一Gray level時, 每條資料線都需要相同的電壓設定,雖然每條資料線都會有各自對應的輸出緩衝器(OP-B),但是這些輸出緩衝放大器的輸入級卻是經由電壓選擇型DAC控制,且全部皆連接到同一組Gray level參考電壓．這些Gray level參考電壓又是以另外之輸出緩衝器來驅動(OP-A)． 若是OP-B輸出能力不足使得輸出電壓設定不正確,只單獨影響該條資料線上畫素顯示不正確；不過若是OP-A的輸出能力不足,則影響的就為所有輸入端對應到這組參考電壓的資料線,因此於分析時,可以利用灰階level的切換,判定為哪一輸出緩衝器有問題． 理解：IC驱动能力不足，可能IC本身问题，也有可能是LCD面板RC太大。 2、TFT漏电 液晶電容的漏電路徑,是由畫素電極漏電至共電極;而TFT的漏電路徑,則是由畫素電極漏電至資料線.因此前者漏電所造成的影響為施加在液晶電容上的跨壓變小,使的顯示器的對比降低,而後者的漏電卻會與資料線上信號的不同與極性反轉有關連性,如此便會使得顯示器產生Vertical crosstalk. 理論上來說只要適當的分析手法便可以找出顯示畫面不良的確切原因但是顯示畫面的不良很可能不會只有一項而且應用分析手法時往往會伴隨其他狀況出現,例如加快Frame rate 時也許可以使TFT漏電效應降低但是畫素電極充電時間也相對減少也有可能會造成畫面完全異常所以在分析上還必須要採取增加Gate line VGH or VGL 電壓變化等方式加以配合．测试画面： 如果产生crosstalk，就会如下图所示： 上面的图片上下左右均已产生crosstalk，通常而言，crosstalk会出现在一个方向，水平或者垂直，两个方向均有的话不是太多； 解决方法：

crosstalk 原理及改善对策

?如何改善STN LCD中的crosstalk現象 ?影響液晶顯示器(STN-LCD)功耗的因素 ?STN-LCD彩屏模組技術及設計 https://www.wendangku.net/doc/be3914751.html, 如何改善STN LCD中的crosstalk現象2006-6-2 -------------------------------------------------------------------------------- 在FPD在和許多STN LCD技術中﹐FPD在和許多其他它以其成熟的工藝和低制做成本在大部分顯示器應用領域中佔有優勢﹐例如﹕遊戲機﹑攜帶型電話﹑隨著資和許多其他需要小尺寸顯示器的產品。PDA它以其成熟的工藝和低制做成本在大部分顯示器應用領域中佔有優勢﹐例如﹕遊戲機﹑攜帶型電話﹑隨著資訊產業的在顯示器的規格中對彩色顯示器的要求更苛刻。儘管如此﹐彩色STN顯示器已經開發並被顯示器市場所接受。比較有效矩陣顯示器﹐STN LCD 要面對的困難就是crosstalk的問題。Crosstalk現象大體上講是由相鄰象素相互干涉而產生的一種可見的缺點。它就象一個半透明的尾巴﹐是從屬圖案﹐只會在某些畫面中出現。但不幸的是﹐我們的顯示質量會因此而下降(這種現象如Fig.1所示)。 Crosstalk現象是如何產生的? 產生crosstalk現象的原因有兩種﹕屏的特性和IC的性能。Fig.2所示的是LCD屏的電模型。每個電容表示一個顯示象素﹐每條線上的電阻描述該條線所代表的ITO的阻值。

啟動象素﹐電容兩邊會產生一個電壓。這個均方根電壓通過電容決定象素的亮顯。因此在同一列的象素由一個信號線驅動﹐電壓通過一個象素時會受到同一列的其他象素的影響。當通過同一行的不同象素的電壓不同時﹐crosstalk現象就會產生。 如何測量crosstalk現象? 因為crosstalk現象是一種從屬圖案﹐所以需要特定的測試模式來測量它的存在。Fig.3a和Fig.3b描述了兩種圖案可以有效的檢測crosstalk現象。這些長條會產生更多的crosstalk。實心的線條檢測驅動問題比較有效﹐虛線的長條對於檢測屏的相關問題比較有效。對於灰階或CSTN LCD﹐因為它們更易受到crosstalk現象的影響﹐所以需要橫向的灰色線條。 單色和灰階顯示的不同 Fig.4a和Fig.4b分別描述了單色和灰階顯示器的電壓和透射比(VT)的曲線。假設兩相鄰象素的均方根電壓相差Δv(如Fig.4a所示)﹐透射比相差Δt2﹐Δt2小於Δt1。因此﹐在單色STN 中具有比較陡峭變化的VT曲線的屏會減少crosstalk現象。但是﹐從Fig.4b中可以看出在灰階或CSTN顯示中Δt2大於Δt1﹐這就是說﹐灰階或CSTN顯示幕需要較為平緩的VT曲線。從Fig.4b還可以看出crosstalk現象在兩灰階處比在黑白區域嚴重。

crosstalk_param

Updated on : 04th August 2006 Abstract: This application note describes details of Astro-crosstalk commands and parameters that do not have online help. xtIgnoreTieHighLowNet When enabled, tiehigh or tielow nets will be ignored as victims in static noise analysis (xtXTalkAnalysis). Syntax: xtIgnoreTieHighLowNet 1 Ignore tiehigh/tielow nets as victim nets in static noise analysis. xtIgnoreTieHighLowNet 0 Don't ignore tiehigh or tielow nets as victim nets in static noise analysis. The default is to ignore tiehigh or tielow nets as victim nets and calculate static noise on those nets. xtDumpStageDelay Dumps the delay of each stage in the design into an output file. This information can be used to check the correlation between Astro and PrimeTime SI. You have to run the astReportTiming command to set the Astro timer to standby mode before running this command. Syntax: xtDumpStageDelay “filename” Stage delay report example: -------------------------------------------------------------------- - - Astro Stage Delay Report - - Tool : Astro - Version : W-2004.12-SP1_rel-Development for SUN.32 -- Mar 16, 2005 - Design : add16 - Date : Wed Mar 16 15:50:14 2005 - Timer : Xtalk effect is ON, DeltaTransScaling Factor = 0.00 - : Store Delta Trans and Delay is ON - - Format : Delay for stage stage_chain is: (rise_min rise_max) (fall_min fall_max) - - Stage Delay Includes Both Cell Delay and Net Delay - If Xtalk Effect is ON, Stage Delay is Normal Delay + Delta Delay - -------------------------------------------------------------------- Delay for stage buf_clk/andclk/A -> buf_clk/Z -> ffa0/CP is: (0.0000 0.0000) (0.0000 0.0000) Delay for stage buf_clk/andclk/A -> buf_clk/Z -> ffa1/CP is: (0.0000 0.0000) (0.0000 0.0000) Delay for stage ffa13/CP -> ffa13/Q -> xadd13/an4/B is: (0.1643 0.4572) (0.1721 0.4516) Delay for stage ffa13/CP -> ffa13/Q -> xadd13/xo1/B is: (0.1643 0.4572) (0.1721 0.4516) Delay for stage ffa13/CP -> ffa13/Q -> xadd13/an3/A is: (0.1642 0.4571) (0.1720 0.4515) Delay for stage ffb12/CP -> ffb12/Q -> xadd12/an4/C is: (0.1704 0.4500) (0.1731 0.4486)

crosstalk

[技术讲堂]什么是液晶串扰？ 2015-02-06FPD平板显示大讲堂平板显示大讲堂 平板显示技术交流 串扰,又称为Crosstalk,本来是指信号线因为电容耦合的原因,互相影响,造成信号传输异常。在薄膜晶体管显示器(TFT-LCD)的发展过程中,逐渐将串扰定义为一种画面显示异常的现象,即整个显示屏上一部分区域会受到另一部分区域的影响,而使画面失真。串扰是TFT-LCD显示类不良现象中比较常见的一种,是指某一区域的画面会影响到另一区域的画面。串扰在背景是中间灰阶才能容易观察出,这是由于亮度对人眼的影响。特别是在白画面背景下中间显示黑色方块,黑块周边的串扰会很明显被观察出来,这也是为什么检测串扰时使用此画面的原因。 串扰常见的有两种分别称垂直串扰和水平串扰。背景为灰阶时,中间为黑色方块。黑色方块的周边区域根据位置可以分为上、下、左、右四个区域。当上、下区域受到黑色区域的影响而变的比背景更暗时,称为垂直串扰。同理,当左、右区域受到黑色区域影响变的比背景更亮时,称为水平串扰，当然以上串扰的定义也过于笼统，串扰的形状也并非图片上所示一样，这里仅作示意。

垂直串扰产生的原因主要与数据线和TFT相关。其一为数据线与像素电极的耦合电容过大引起。对于TN型液晶来说，中间黑画面其电压较高，上下两侧与左右区域的数据线电压一致，当数据线与像素电极耦合电容过大时，中间黑色的数据线高电压会带动上下两侧像素电极电压变大，从而其色调会更暗。其二TFT 漏电流过大也会导致垂直串扰，原因是液晶显示为逐行扫描式驱动，所以当中间黑色区域给高电压信号时，其对应的扫描线为高电压打开状态，上下部分的扫描线为低电压关闭状态，当TFT关态漏电流过大时，会导致上下像素电极充入高电压，上下区域会变暗。 水平串扰产生的原因主要与共通电极（包括彩膜侧共通电极与阵列侧共通电极线）有关。主要受到数据线与共通电极的耦合电容的影响。当共通电极与数据线耦合电容较大时，中间黑画面对应的高电压会引起共通电极电压的变动，当共通电位发生变化时，像素无法充电至正确的电位。当彩膜侧共通电极阻抗过大，电压变动后无法迅速调整电位，也会发生串扰现象。 解决方法：垂直串扰主要要降低数据线与像素电极的耦合电容，主要包括增加间距，使用低介电常数绝缘层等，另外要降低TFT关态电流。水平串扰主要降低共通电极线与数据线的耦合电容，另外要降低彩膜侧共通电极的电阻，保持共通电位。 最后串扰现象最容易发生在列反转，帧反转以及Com反转模式中，在目前广泛使用的点反转显示模式中，由于电位的正负对称输入，对共通电极无法定向拉伸，所以水平串扰出现的几率较低。对于数据线与像素电极之间的耦合电容过大，主要可能会出现闪烁的不良。

cross talk 解说词

1.It is a traditional Chinese comedic performance in the form of a dialogue or, much less often, a monologue or, even less frequently, a multi-player talk show. 2.The language, rich in puns and allusions, is used in a rapid, bantering style. 3.Modern cross talk is made up of four skills - speaking (说), imitating (学), teasing (逗), and singing (唱). ●说：讲故事，还有说话和铺垫的方式。Telling story, the way of speaking and foreshadowing ●学：模仿各种人物、方言和其他声音，学唱戏曲的名家名段，现代也有学唱歌跳舞。To imitate the various characters, dialects and other sounds, learning to sing famous period of opera, it includes singing and dancing nowadays. ●逗：制造笑料。Make source of comic relief ●唱：经常被认为是唱戏，唱歌。实际上“唱”是指演唱“太平歌词”。太平歌词是相声的本功唱。“太平歌词”是用两片竹板伴唱的一种北京民间小曲。 It is said that Dongfang Shuo of Han Dynasty is the forefather of Chinese crosstalkers. It is in Qing Dynasty (1644-1911) that this popular plebeian culture began to prosper. The earliest cross talk comedian known by name is Zhang Sanlu (张三禄), who performed in the mid nineteenth century. In early years, street cross talkers in Beijing's Tian Qiao area included Qiongbupa (穷不怕), Wanrenmi (万人迷) and Li Dexi. They wrote and performed many popular pieces, making indelible contributions to the development of this art form. Although Beijing was home to the cross talk, the port city of Tianjin, with its proximity to Beijing, was a place where cross talkers must go to perform. Gradually, Tianjin became a place where any new pieces had to be first performed and recognized before being staged in Beijing. Many famous cross talkers all once performed in Tianjin for many years before their names were widely known across the country, including Ma Sanli, Hou Baolin and so on. Although Tianjin is not the birthplace of the cross talk, it is a city that once cultivated many famous cross talkers who has achieved artistic excellence of unique depth. 马季which was performed in the spring festival gala evening in 1987, and it is the most successful group-crosstalk ever. Ma ji is a real crosstalk master and he plays a very important role in the inheritance and development of crosstalk, and makes a stunning contribution. 冯巩is a typical cross talker who had changed his performance style from the traditional way to the entertainment modern way. What’s more important is the “new way to sing the old song”is a milepost of the cross talk drama, and Feng Gong is the founder of it. It is no doubt that cross talkers bring us a lot of laughter, helping us feel comfortable, eliminate fatigue and forget worries. Personally I think we should not regard the cross talk just as a recreational pastime. As we can see, the comic language expressions in this kind of art pervade many aspects of our life, especially those showed on the stage of Spring Festival Gala. For example 你摊上事儿了，

crosstalk

1.串音的本質 何謂串音：若是系統中某一個電壓源發生變化，因而擾亂到顯示器的畫面灰階顯示狀態，此種現象即被稱為畫面串音（Crosstalk）。再明確的說明，即是顯示器中的某一個顯像畫素（Pixel），因為其他畫素顯像或是操作電極狀態的變動，影響到這個畫素原本的顯像狀態時，即是顯示器的畫面串音。參考圖一的TFT LCDs的陣列佈局與等效電路，從靜態操作的直觀角度而言，只有當TFT是在開啟（ON）的狀態下，液晶畫素才可以被資料驅動線上的影像電壓訊號影響，經由TFT對液晶畫素充放電；若是TFT在關閉（OFF）的狀態下，理論上液晶畫素是與外部其他的電極或是液晶畫素隔絕，所以不會受到其他部分訊號變化的影響。但是，TFT並不是一個優良的電子開關，在TFT關閉的狀態下仍然會有漏電流的產生，參考圖二在TFT關閉的狀態下，液晶畫素電壓的改變可以用指數衰減的形式描述，影像資料電壓為V s； 另外各個電極間與半導體元件的雜散電容效應，都會影響液晶畫素的顯像狀態。 首先討論資料訊號線與液晶畫素間的雜散電容效應。參考圖一的等效電路，由於訊號線與畫素間的雜散電容，造成在訊號線上的訊號位階變動會經由雜散電容耦合至液晶畫素，液晶畫素的顯像狀態因而改變，在整體畫面上出現垂直方向上的串音現象。例如液晶電容C LC的電容值為0.4pF，液晶畫素沒

有設計儲存電容Cs ，若是訊號線與畫素間的雜散電容C ps 與C ps’為0.02pF 時，在液晶畫素上會造成大約10%的電壓誤差。參考圖三液晶電光轉移曲線，10%的電壓誤差將會造成約20%的灰階穿透率改變。但是對於黑白的液晶顯示器而言，由於是操作在液晶電光轉移曲線的兩個極端區域，所以這種灰階電壓的變化並不會影響黑白液晶顯示器的畫面品質。另外有一點要注意，由以上的例子發現，若是加大液晶畫素的儲存電容Cs ，可以有效的降低垂直串音的現象。 1.1圖框反轉（Frame Inversion ）對垂直串音的影響 由於液晶必須以交流方式驅動，以避免液晶電容內有殘餘的直流電壓成份，造成液晶分子的電化學反應。交流驅動的方式有圖框反轉（Frame Inversion ）、線反轉（Row Inversion 、Line Inversion ）、行反轉（Column Inversion ）、及點反轉（Dot Inversion ）。以下即針對不同的交流驅動方式所產生的垂直串音現象分別作討論。首先參考圖一的液晶畫素等效電路，一個液晶畫素的等效電容值C t 如（1）式，是所有的雜散電容、儲存電容、及液晶電容的總和。液晶畫素經由C ps 與C ps’的電容耦合效應，可以用耦合參數（Coupling Parameter ）α、β來表示，如（2）（3）式： （1） （2） ' 'pg pg gd ps ps S LC t C C C C C C C C ++++++=t ps C C ≡ α

cross talk 英语相声

A: Good morning everyone, today I will play a short crosstalk with my partner…Where is him? B (run up quickly, very tired): Good morning… A: You are late! We are all waiting for you! B: Oh, I am sorry, but it was an accident, I caught a car accident on my way here and I am still alive! A: What did you say? A car accident? B: Yeah. At that time, I was riding my bike, then suddenly I found that my bike wasn’t under my control. I wanted to stop it but I didn’t see a bus on the right of me, then, then…that bus hit me and I fell down. A (with the mouth open): A, a, a, a bus? You said a bus hit you? B: Yes, it is true! A: Didn’t you get hurt! B: Of course I did not, because that bus was parking there! At that time, I told me I must be dead. I did not understand until someone shouted “Do you want to take a free bus?” A: Were there any passengers on it? B: No, nobody... A: Ok, that was good. B: But the bus driver was on it, and he looked out of the

耳机Cross Talk

近来调试一个项目(MT6236平台+TI的耳机功放TPA6132+3.5寸的耳机）的耳机性能，THD+N, SNR等指标都还不错，但Cross talk 指标只有30db。后来想到，我们的FM天线是用耳机地线做天线。以一颗2.5K/100MHZ的下地慈珠做隔离。想到可能这颗慈珠的影响。把慈珠换为0R后，Cross talk指标变为55dB。不知道慈珠为什么会影响Cross talk. 另外还想到用22uH或100nH并22pF的方式来代替慈珠。后来此项目被公司停了，公司又没仪器。就没有继续分析下去。有遇到类似情况并解决的谈一下。 高阻抗的磁珠的直流电阻太大了！！！ 1)尽量选用直流电阻小的磁珠，必要时可以选择阻抗低一些的磁珠，比如选用1000欧姆@100Mhz的。 2）使用直流电阻低的功率电感来代替，要求自谐振频率在100MHz左右，1uH以上的。 3）使用100nH并联24pF的电路来代替，也是要求电感直流电阻尽量小，必要时选用绕线电感。缺点是带宽较窄，做全球FM频段有点困难，但是覆盖国内的88-108没有问题。 简单的说，Crosstalk指标就是考察左右通道的隔离度的。 举一个简单的例子，如果耳机功放左声道输出1V，右声道输出0V。 1）如果这个位置是0 Ohm电阻，那在耳机喇叭哪里测量到的还是左声道1V，右声道0V，Crosstalk为0比1，转换为dB就是负的无穷小。 2）如果这个位置电阻不为零，则电阻上有电压降，假设这个电压降为A，则左喇叭上测到的电压降为1-A，右喇叭测到的电压降为A。Crosstalk为A/(1-A) ，这就不是负的无穷小了。这个电阻越大，A就越大，A越大，Crosstalk就会越来越大。 极端条件下，如果这个电阻无穷大，就是开路，则左右声道听到声音是一样的。Crosstalk 就为0dB。