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局域网交换机中英文对照外文翻译文献

局域网交换机中英文对照外文翻译文献
局域网交换机中英文对照外文翻译文献

中英文资料外文翻译文献

英文:

LAN Switch Architecture

This chapter introduces many of the concepts behind LAN switching common to all switch vendors. The chapter begins by looking at how data are received by a switch, followed by mechanisms used to switch data as efficiently as possible, and concludes with forwarding data toward their destinations. These concepts are not specific to Cisco and are valid when examining the capabilities of any LAN switch.

1. Receiving Data—Switching Modes

The first step in LAN switching is receiving the frame or packet, depending on the capabilities of the switch, from the transmitting device or host. Switches making forwarding decisions only at Layer 2 of the OSI model refer to data as frames, while switches making forwarding decisions at Layer 3 and above refer to data as packets. This chapter's examination of switching begins from a Layer 2 point of view. Depending on the model, varying amounts of each frame are stored and examined before being switched.

Three types of switching modes have been supported on Catalyst switches:

?Cut through

?Fragment free

?Store and forward

These three switching modes differ in how much of the frame is received and examined by the switch before a forwarding decision is made. The next sections describe each mode in detail.

1.1 Cut-Through Mode

Switches operating in cut-through mode receive and examine only the first 6 bytes of a frame. These first 6 bytes represent the destination MAC address of the frame, which is sufficient information to make a forwarding decision. Although cut-through switching offers the least latency when transmitting frames, it is susceptible to transmitting fragments created via Ethernet collisions, runts (frames less than 64 bytes), or damaged frames.

1.2 Fragment-Free Mode

Switches operating in fragment-free mode receive and examine the first 64 bytes of frame. Fragment free is referred to as "fast forward" mode in some Cisco Catalyst documentation. Why examine 64 bytes? In a properly designed Ethernet network, collision fragments must be detected in the first 64 bytes.

1.3 Store-and-Forward Mode

Switches operating in store-and-forward mode receive and examine the entire frame, resulting in the most error-free type of switching.

As switches utilizing faster processor and application-specific integrated circuits (ASICs) were introduced, the need to support cut-through and fragment-free switching was no longer necessary. As a result, all new Cisco Catalyst switches utilize store-and-forward switching.

Figure2-1 compares each of the switching modes.

Figure2-1.Switching Modes

2. Switching Data

Regardless of how many bytes of each frame are examined by the switch, the frame must eventually be switched from the input or ingress port to one or more output or egress ports. A switch fabric is a general term for the communication channels used by the switch to transport frames, carry forwarding decision information, and relay management information throughout the switch. A comparison could be made between the switching fabric in a Catalyst switch and a transmission on an automobile. In an automobile, the transmission is responsible for relaying power from the engine to the wheels of the car. In a Catalyst switch, the switch fabric is responsible for relaying frames from an input or ingress port to one or more output or egress ports. Regardless of model, whenever a new switching platform is introduced, the documentation will generally refer to the "transmission" as the switching fabric.

Although a variety of techniques have been used to implement switching fabrics on Cisco Catalyst platforms, two major architectures of switch fabrics are common:

?Shared bus

?Crossbar

2.1 Shared Bus Switching

In a shared bus architecture, all line modules in the switch share one data path. A central arbiter determines how and when to grant requests for access to the bus from each line card. Various methods of achieving fairness can be used by the arbiter depending on the configuration of the switch. A shared bus architecture is much like multiple lines at an airport ticket counter, with only one ticketing agent processing customers at any given time.

Figure2-2illustrates a round-robin servicing of frames as they enter a switch. Round-robin is the simplest method of servicing frames in the order in which they are received. Current Catalyst switching platforms such as the Catalyst 6500 support a variety of quality of service (QoS) features to provide priority service to specified traffic flows.

Figure 2-2. Round-Robin Service Order

The following list and Figure 2-3 illustrate the basic concept of moving frames from the received port or ingress, to the transmit port(s) or egress using a shared bus architecture:

Frame received from Host1—The ingress port on the switch receives the entire frame from Host1 and stores it in a receive buffer. The port checks the frame's Frame Check Sequence (FCS) for errors. If the frame is defective (runt, fragment, invalid CRC, or Giant), the port discards the frame and increments the appropriate counter.

Requesting access to the data bus—A header containing information necessary to make a forwarding decision is added to the frame. The line card then requests access or permission to transmit the frame onto

the data bus.

Frame transmitted onto the data bus— After the central arbiter grants access, the frame is transmitted onto the data bus.

Frame is received by all ports— In a shared bus architecture, every frame transmitted is received by all ports simultaneously. In addition, the frame is received by the hardware necessary to make a forwarding decision.

Switch determines which port(s) should transmit the frame— The information added to the frame in step 2 is used to determine which ports should transmit the frame. In some cases, frames with either an unknown destination MAC address or a broadcast frame, the switch will transmit the frame out all ports except the one on which the frame was received.

Port(s) instructed to transmit, remaining ports discard the frame— Based on the decision in step 5, a certain port or ports is told to transmit the frame while the rest are told to discard or flush the frame.

Egress port transmits the frame to Host2—In this example, it is assumed that the location of Host2 is known to the switch and only the port connecting to Host2 transmits the frame.

One advantage of a shared bus architecture is every port except the ingress port receives a copy of the frame automatically, easily enabling multicast and broadcast traffic without the need to replicate the frames for each port. This example is greatly simplified and will be discussed in detail for Catalyst platforms that utilize a shared bus architecture in Chapter 3, "Catalyst Switching Architecture."

Figure 2-3. Frame Flow in a Shared Bus

2.2 Crossbar Switching

In the shared bus architecture example, the speed of the shared data bus determines much of the overall traffic handling capacity of the switch. Because the bus is shared, line cards must wait their turns to communicate, and this limits overall bandwidth.

A solution to the limitations imposed by the shared bus architecture is the implementation of a crossbar switch fabric, as shown in Figure 2-4. The term crossbar means different things on different switch platforms, but essentially indicates multiple data channels or paths between line cards that can be used simultaneously.

In the case of the Cisco Catalyst 5500 series, one of the first crossbar architectures advertised by Cisco, three individual 1.2-Gbps data buses are implemented. Newer Catalyst 5500 series line cards have the necessary connector pins to connect to all three buses simultaneously, taking advantage of 3.6 Gbps of aggregate bandwidth. Legacy line cards from the Catalyst 5000 are still compatible with the Catalyst 5500 series by connecting to only one of the three data buses. Access to all three buses is required by Gigabit Ethernet cards on the Catalyst 5500 platform.

A crossbar fabric on the Catalyst 6500 series is enabled with the Switch Fabric Module (SFM) and Switch Fabric Module 2 (SFM2). The SFM provides 128 Gbps of bandwidth (256 Gbps full duplex) to line cards via 16 individual 8-Gbps connections to the crossbar switch fabric. The SFM2 was introduced to support the Catalyst 6513 13-slot chassis and includes architecture optimizations over the SFM.

Figure 2-4. Crossbar Switch Fabric

3. Buffering Data

Frames must wait their turn for the central arbiter before being transmitted in shared bus architectures. Frames can also potentially be delayed when congestion occurs in a crossbar switch fabric. As a result, frames must be buffered until transmitted. Without an effective buffering scheme, frames are more likely to be dropped anytime traffic oversubscription or congestion occurs.

Buffers get used when more traffic is forwarded to a port than it can transmit. Reasons for this include the following:

?Speed mismatch between ingress and egress ports

?Multiple input ports feeding a single output port

?Half-duplex collisions on an output port

? A combination of all the above

To prevent frames from being dropped, two common types of memory management are used with Catalyst switches:

?Port buffered memory

?Shared memory

3.1 Port Buffered Memory

Switches utilizing port buffered memory, such as the Catalyst 5000, provide each Ethernet port with a certain amount of high-speed memory to buffer frames until transmitted. A disadvantage of port buffered memory is the dropping of frames when a port runs out of buffers. One method of maximizing the benefits of buffers is the use of flexible buffer sizes. Catalyst 5000 Ethernet line card port buffer memory is flexible and can create frame buffers for any frame size, making the most of the available buffer memory. Catalyst 5000 Ethernet cards that use the SAINT ASIC contain 192 KB of buffer memory per port, 24 kbps for receive or input buffers, and 168 KB for transmit or output buffers.

Using the 168 KB of transmit buffers, each port can create as many as 2500 64-byte buffers. With most of the buffers in use as an output queue, the Catalyst 5000 family has eliminated head-of-line blocking issues. (You learn more about head-of-line blocking later in this chapter in the section "Congestion and Head-of-Line Blocking.") In normal operations, the input queue is never used for more than one frame, because the switching bus runs at a high speed.

Figure 2-5illustrates port buffered memory.

Figure 2-5. Port Buffered Memory

3.2 Shared Memory

Some of the earliest Cisco switches use a shared memory design for port buffering. Switches using a shared memory architecture provide all ports access to that memory at the same time in the form of shared frame or packet buffers. All ingress frames are stored in a shared memory "pool" until the egress ports are ready to transmit. Switches dynamically allocate the shared memory in the form of buffers, accommodating ports with high amounts of ingress traffic, without allocating unnecessary buffers for idle ports.

The Catalyst 1200 series switch is an early example of a shared memory switch. The Catalyst 1200 supports both Ethernet and FDDI and has 4 MB of shared packet dynamic random-access memory (DRAM). Packets are handled first in, first out (FIFO).

More recent examples of switches using shared memory architectures are the Catalyst 4000 and 4500 series switches. The Catalyst 4000 with a Supervisor I utilizes 8 MB of Static RAM (SRAM) as dynamic frame buffers. All frames are switched using a central processor or ASIC and are stored in packet buffers until

switched. The Catalyst 4000 Supervisor I can create approximately 4000 shared packet buffers. The Catalyst 4500 Supervisor IV, for example, utilizes 16 MB of SRAM for packet buffers. Shared memory buffer sizes may vary depending on the platform, but are most often allocated in increments ranging from 64 to 256 bytes. Figure 2-6 illustrates how incoming frames are stored in 64-byte increments in shared memory until switched by the switching engine.

Figure 2-6. Shared Memory Architecture

4. Oversubscribing the Switch Fabric

Switch manufacturers use the term non-blocking to indicate that some or all the switched ports have connections to the switch fabric equal to their line speed. For example, an 8-port Gigabit Ethernet module would require 8 Gb of bandwidth into the switch fabric for the ports to be considered non-blocking. All but the highest end switching platforms and configurations have the potential of oversubscribing access to the switching fabric.

Depending on the application, oversubscribing ports may or may not be an issue. For example, a 10/100/1000 48-port Gigabit Ethernet module with all ports running at 1 Gbps would require 48 Gbps of bandwidth into the switch fabric. If many or all ports were connected to high-speed file servers capable of generating consistent streams of traffic, this one-line module could outstrip the bandwidth of the entire switching fabric. If the module is connected entirely to end-user workstations with lower bandwidth requirements, a card that oversubscribes the switch fabric may not significantly impact performance. Cisco offers both non-blocking and blocking configurations on various platforms, depending on bandwidth requirements. Check the specifications of each platform and the available line cards to determine the aggregate bandwidth of the connection into the switch fabric.

5. Congestion and Head-of-Line Blocking

Head-of-line blocking occurs whenever traffic waiting to be transmitted prevents or blocks traffic destined elsewhere from being transmitted. Head-of-line blocking occurs most often when multiple high-speed data sources are sending to the same destination. In the earlier shared bus example, the central arbiter used the round-robin service approach to moving traffic from one line card to another. Ports on each line card request access to transmit via a local arbiter. In turn, each line card's local arbiter waits its turn for the central arbiter to grant access to the switching bus. Once access is granted to the transmitting line card, the central arbiter has to wait for the receiving line card to fully receive the frames before servicing the next request in line. The situation is not much different than needing to make a simple deposit at a bank having one teller and many lines, while the person being helped is conducting a complex transaction.

In Figure 2-7, a congestion scenario is created using a traffic generator. Port 1 on the traffic generator is connected to Port 1 on the switch, generating traffic at a 50 percent rate, destined for both Ports 3 and 4. Port 2 on the traffic generator is connected to Port 2 on the switch, generating traffic at a 100 percent rate, destined for only Port 4. This situation creates congestion for traffic destined to be forwarded by Port 4 on the switch because traffic equal to 150 percent of the forwarding capabilities of that port is being sent. Without proper buffering and forwarding algorithms, traffic destined to be transmitted by Port 3 on the switch may have to wait until the congestion on Port 4 clears.

Figure 2-7. Head-of-Line Blocking

Head-of-line blocking can also be experienced with crossbar switch fabrics because many, if not all, line

cards have high-speed connections into the switch fabric. Multiple line cards may attempt to create a connection to a line card that is already busy and must wait for the receiving line card to become free before transmitting. In this case, data destined for a different line card that is not busy is blocked by the frames at the head of the line.

Catalyst switches use a number of techniques to prevent head-of-line blocking; one important example is the use of per port buffering. Each port maintains a small ingress buffer and a larger egress buffer. Larger output buffers (64 Kb to 512 k shared) allow frames to be queued for transmit during periods of congestion. During normal operations, only a small input queue is necessary because the switching bus is servicing frames at a very high speed. In addition to queuing during congestion, many models of Catalyst switches are capable of separating frames into different input and output queues, providing preferential treatment or priority queuing for sensitive traffic such as voice. Chapter 8 will discuss queuing in greater detail.

6. Forwarding Data

Regardless of the type of switch fabric, a decision on which ports should forward a frame and which should flush or discard the frame must occur. This decision can be made using only the information found at Layer 2 (source/destination MAC address), or on other factors such as Layer 3 (IP) and Layer 4 (Port). Each switching platform supports various types of ASICs responsible for making the intelligent switching decisions. Each Catalyst switch creates a header or label for each packet, and forwarding decisions are based on this header or label. Chapter 3 will include a more detailed discussion of how various platforms make forwarding decisions and ultimately forward data.

7. Summary

Although a wide variety of different approaches exist to optimize the switching of data, many of the core concepts are closely related. The Cisco Catalyst line of switches focuses on the use of shared bus, crossbar switching, and combinations of the two depending on the platform to achieve very high-speed switching solutions. High-speed switching ASICs use shared and per port buffers to reduce congestion and prevent head-of-line blocking.

翻译:

局域网交换机体系结构

本章将介绍所有交换机生产厂商都遵守的局域网交换技术的一些基本概念。本章首先介绍交换机如何接受数据。随后,本章介绍保证高效数据交换的一些机制。最后,本章介绍如何将数据转发给目标。这些概念并非Cisco交换机所特有的,而是在查看局域网交换机功能的时候,对所有交换机产品都适用的。

1. 数据接收----交换模式

在局域网交换中,根据交换机功能的不同,第一步就是从发送设备或主机接收帧或分组。对于仅在OSI模型的第2层进行转发决策的交换机,它们将数据看作帧。而对于在OSI 模型的第3层或者更高层进行转发决策的交换机,它们将数据看作分组。本章首先从第2层的角度来研究交换机。根据具体型号的不同,交换机在数据交换之前所存储和检查的桢数目也存在一定差异。

Catalyst交换机攴持下述三种交换模式:

?直通模式;

?碎片隔离模式;

?存储转发模式。

上述3种交换模式的区别在于交换机在制定转发决策之前所接收和检查的帧数目。下面将详细讨论每种交换模式。

1.1 直通模式

如果交换机工作在直通模式,那么它将只接收和检查帧的的前6个字节。这6个字节代表了帧的日标MAC地址,交换机利用这些信息足以做出转发决策。尽管直通交换能够在数据传送的时候提供最低的延迟,但却容易传送以太网碰撞所产生的碎片、残帧(runt)或受损帧。

1.2 碎片隔离模式

如呆交换机工作在碎片隔离模式,那么它将接收和检查全帧的前64个字节。在某些Cisco Catalyst交换机的文档中,碎片隔离又称为“快速转发”模式。为什么交换机检查帧的前64个字节呢?因为在设计良好的以太网网络中,碰撞碎片必须在前64字节中检测出来。

1.3 存储转发模式

如果交换机工作在存储转发模式,那么它将接收和检查整帧,因此它是错误率最低的交换模式。

由于采用速度更快的处理器和ASIC(Application-Specific Integrated Circuit,专用集成电路),交换机不必支持直通交换机和碎片隔离交换,因此,所有新型的Cisco Catalyst交换机都采用存储转发交换。

图2-1比较各种交换模式之间的区别。

图2-1 交换模式

2. 数据交换

无论交换机需要检查帧的多少字节,帧最终都将由输入或入站端口交换到单个或多个输出和出站端口。交换矩阵(switch fabric)是交换机通信信道的一个常用术语,它可以在交换机内部传送帧、承载转发决策信虑、和转送管理信息。Catalyst交换机中的交换矩阵可以看作汽车中的传动装置,在汽车中,传动装置负责将引擎的动力传递给汽车轮子;在Catalyst交换机中,交换矩阵负责将输入或入站端口的帧转送给单个或多个输出和出站端口。无论具体型号如何,也无论何时产生新的交换平台,所有文档都会将“传动装置”作为交换矩阵。

尽管Cisco Catalyst平台已经采用多种技术来实现交换矩阵,但以下两种体系结构的交换矩阵最为常见:

?共享总线;

?交叉矩阵。

2.1 共享总线交换

在共享总线的体系结构中,交换机的所有线路模块都共享1个数据通路。中央仲裁器决定何时授予各线路卡访问总线的请求。根据交换机配置的情况,仲裁器能够使用多种公平方法。共享总线体系结构非常类似于机场票务柜台前的多个队列,但任何时候仅有1个票务代理处理客户请求。

图2-2举例说明帧进入交换机时的循环服务过程。如果希望根据帧的接收顺序进行服务,那么循环是最简单的方法。为了能够给特定通信流量提供优先级服务,当前的Catalyst 交换平台(例如Catalyst 6500)能够支持各种各样的QoS(Quanlity Of Service,服务质量)特性。

图2-2 循环服务顺序

图2-3说明了共享总线体系结构中将接收端口或入口处的帧移动到发送端口或出口的基本原理,其中各步骤说明如下。

1.接收源自主机1的帧----交换机的入站端口接受源自主机1的整帧,并且将其存储到接受缓冲区中。端口根据帧的FCS(Frame Check Sequence,帧检验序列)进行错误检测。如果帧存在缺陷(例如残帧、碎片、无效CRC或者巨型帧),那么端口将丢弃该帧,并且将增加相关计数器的数值。

2.请求访问数据总线----包含转发决策所需要的信息报头将被添加到帧中,然后线路卡请求在数据总线上发送帧的访问权限或者许可权限。

图2-3 共享总线中的帧流

3.将帧发送到数据总线----在中央仲裁器授予访问权限之后, 帧将被发送到数据总线上。

4.所有端口接收到帧----在共享总线体系结构中,所有端口都将同时接收每个发送帧。此外,负责转发决策的硬件也将接收到帧。

5.交换机决定哪个端口应当发送帧----第2步骤中添加到帧中的信息可用于确定哪些端口应当发送帧。在某些情况下,对于具有未知目标MAC地址的帧或者广播帧,交换机将向除帧接收端口之外的所有端口发送帧。

6.端口发送帧,其余端口丢弃该帧----根据第5步骤中的决策,某个特定端口或者某些端口被告知发送帧,而其余端口则被告知丢弃或者清空帧。

7.出站端口将帧发送到主机2----在这个示例中,假定交换机知道主机2的位置,并且仅在连接到主机2的端口发送帧。

共享总线体系结构的优势之一在于每个端口(入站端口除外)都将自动接收帧的副本,也就易于实现组播和广播流量,而无需复制各个端口的帧。

2.2 交叉矩阵交换

在共享总线体系结构示例中,共享数据总线的速度决定了交换机的流量处理总容量。因为总线采用共享访问的方式,所以线路卡必须等待时机才能进行通信,这严重限制了总带宽。

为了克服共享数据总线体系结构所产生的限制,解决方案是采用交叉交换矩阵,如图2-4所示。对于不同的交换机平台,术语交叉矩阵意味着不同的内容,但基本都指线路卡之间能够同时使用多个数据信道或者通路。

图2-4 交叉交换矩阵

在Cisco Catalyst 5500系列(Cisco公司最早采用交叉矩阵体系结构的产品之一)交换机产品中,总共实现3条独立的1.2Gbit/s数据总线,新型的Catalyst 5500系列线路卡具有必要的连接器针脚,她们能够同时连接到这3条数据总线,进而能够充分利用3.6Gbit/s 的总带宽。通过仅连接到3条数据总线中的1条数据总线,老式的Cisco Catalyst 5500系列线路卡仍然能够兼容Cisco Catalyst 5500系列。在Cisco Catalyst 5500平台中,吉比特以太网线路卡要求访问所有3条数据总线。

在Cisco Catalyst 6500系列交换机中,SFM(Switch Fabric Module,交换矩阵模块)和SFM2(Switch Fabric Module2,交换矩阵模块2)能够支持交叉矩阵。通过到交叉交换矩阵的16个独立的8Gbit/s连接,SFM能够向线路卡提供128Gbit/s的带宽(256Gbit/s 全双工)。新型SFM2用于支持Catalyst 6513(13插槽的机箱),并且对SFM进行了体系结构方面的优化。

3. 数据缓冲

在共享数据体系结构传送帧之前,帧必须等待中央仲裁器的处理安排。此外,交叉交换矩阵发生拥塞,也可能会延迟帧的处理。基于上述原因,在传送帧之前,必须对其进行缓冲处理。如果没有有效的缓冲机制,那么当出现流景过量或发牛拥塞的时候,帧被丢弃的可能性就非常高。

如果发往端口的流量超过了它所能发送的流量,那么就需要使用缓冲。出现下述情况的时

候,就需要使用缓冲:

?入口和出站端口的速度不匹配;

?多个输入端口共同向单个输出端口提供流景;

?输出端口发生半双工碰撞;

?上述几种情况的组合。

为了防止丢弃帧,Catalyst交换机通常采用下述两种内存管理方式:

?端口缓冲内存;

?共享内存。

3.1 端口缓冲内存

通过采用端口缓冲内存,交换机(例如Catalyst 5500)能够为每个以太网端口提供一定数量的高速内存,这些内存可用于帧发送之前的帧缓冲。端口缓冲内存的不足之处,在于如果端口的缓冲已经用尽,那么就会发生丢弃帧的情况。为了最大限度利用缓冲的优势,方法之一是采用灵活的缓冲区尺寸。Catalyst 5500以太网线路卡端口的缓冲内存就是非常灵活的,并且能够创建各种尺寸的帧缓冲区,进而充分利用可用的缓冲区内存。对于采用SAINT ASIC的Catalyst 5000以太网卡,每个端口包含192KB的缓冲区内存,其中24KB用于接收或者输入缓冲区,而168KB用于发送或者输出缓冲区。

通过使用168KB的发送缓冲区,每个端口最多能够创建2500个64字节的缓冲区。因为大多数缓冲区都用语输出队列,所以Catalyst 5000家族交换机已经减轻线端阻塞的问题。

图2-5举例说明端口缓冲内存的情况。

3.2 共享内存

在最早的Cisco交换机产品中,某些产品使用共享内存设计进行端口缓冲。对于采用共享内存体系结构的交换机,所有端口能够同时以共享帧或者分组缓冲区的形式访问内存。所有的入口帧都被存储到共享内存“池”中,并且一直保存到出站端口准备发送帧为止。交换机以缓冲区的形式动态地分配共享内存,为接收大量入口流量的端口分配足够的缓冲区,并且不会为空闲端口分配不必要的缓冲区。

图2-5 端口缓冲内存

Catalyst 1200系列交换机是一款早期的共享内存交换机产品。Catalyst 1200能够支持以太网和FDDI,并且具有4MB的共享分组DRAM(Dynamic Random-Access Memory,动态随机访问内存)。分组采用FIFO(first in ,first out,先入先出)的处理方式。

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