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CAT5269WI-10TE13中文资料

DESCRIPTION

The CAT5419 is two Digitally Programmable Potentiometers (DPP?) integrated with control logic and 16 bytes of NVRAM memory.

A separate 6-bit control register (WCR) independently controls the wiper tap position for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I 2C-like). On power-up, the contents of the

CAT5419

Dual Digitally Programmable Potentiometers (DPP?) with 64 Taps and 2-wire Interface

FEATURES

s Two linear-taper digital potentiometers s 64 resistor taps per potentiometer

s End-to-end resistance 2.5k ?, 10k ?, 50k ? or 100k ?s Potentiometer control and memory access via

2-wire interface (I 2

C like)

s Low wiper resistance, typically 80?s Four non-volatile wiper settings for each

potentiometer

s Recall of wiper settings at power up

s 2.5 to 6.0 volt operation s Standby current less than 1μA

s 1,000,000 nonvolatile WRITE cycles

s 100 year nonvolatile memory data retention s 24-lead SOIC, 24-lead TSSOP and BGA s Write protection for data register

PIN CONFIGURATION

FUNCTIONAL DIAGRAM

? 2004 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Document No. 2115, Rev. F

first data register (DR0) for each of the two potentiometers is automatically loaded into its respective wiper control registers (WCR).

The Write Protection (WP ) pin protects against inadvertent programming of the data register.The CAT5419 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications.

BGA Top View - Bump Side Down

A L

G E N F R E E

L E

A D F R E E A B

C D E F

V CC R L0R H0R W0A 2WP SDA A 1R L1R H1R W1GND

NC NC NC NC A 0NC A 3SCL NC NC NC NC

SDA A 1R L1R H1R W1GND NC NC NC NC SCL A 3

WP A 2R W0R H0R L0V CC NC NC NC NC A 0NC

SOIC Package (J, W)TSSOP Package (U, Y)

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CAT5419

Document No. 2115, Rev. F

PIN DESCRIPTION

Pin Pin Pin

(TSSOP)

(SOIC)

(BGA)Name

Function

191C1VCC Supply Voltage

202B1R L0Low Reference Terminal for Potentiometer 0213C2R H0High Reference Terminal for Potentiometer 0

224A1R W0Wiper Terminal for Potentiometer 0235A2A2Device Address 246B2WP Write Protection 17B3SDA Serial Data Input/Output 28A3A1Device Address 39A4R L1Low Reference Terminal for Potentiometer 14

R H1High Reference Terminal for Potentiometer 1

511B4R W1Wiper Terminal for Potentiometer 1612C4GND Ground 713D4NC No Connect 814E4NC No Connect 915D3NC No Connect 1016F4NC No Connect 1117F3SCL Bus Serial Clock 1218E3A3Device Address 1319D1NC No Connect

1420F2A0Device Address, LSB 1521F1NC No Connect 1622D2NC No Connect 1723E1NC No Connect 18

No Connect

PIN DESCRIPTIONS

SCL:Serial Clock

The CAT5419 serial clock input pin is used to clock all data transfers into or out of the device.SDA:Serial Data

The CAT5419 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-OR'd with the other open drain or open collector outputs.

A0, A1, A2, A3:Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus.A match in the slave address must be made with the address input in order to initiate communication with the CAT5419.

R H , R L :Resistor End Points

The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer.R W :Wiper

The R W pins are equivalent to the wiper terminal of a mechanical potentiometer.

WP :Write Protect Input

The WP pin when tied low prevents non-volatile writes to the data registers (change of wiper control register is allowed) and when tied high or left

floating normal read/write operations are allowed.See page 7, Write Protection for more details.

DEVICE OPERATION

The CAT5419 is two resistor arrays integrated with 2-wire serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers.Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and R L ). R H and R L are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (R W ) by a

CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.

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CAT5419

Document No. 2115, Rev. F

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ..................-55°C to +125°C Storage Temperature........................-65°C to +150°C Voltage on any Pin with

Respect to V SS (1)(2)................-2.0V to +V CC +2.0V V CC with Respect to Ground ................-2.0V to +7.0V Package Power Dissipation

Capability (T A = 25°C)...................................1.0W Lead Soldering Temperature (10 secs)............300°C Wiper Current.................................................. +12mA

Note:

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.(3)Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.(4)LSB = R TOT / 63 or (R H - R L ) / 63, single pot (5)n = 0, 1, 2, ..., 63

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.

Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to V CC +2.0V for periods of less than 20 ns.(2)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings ”may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Recommended Operating Conditions:V CC = +2.5V to +6.0V Temperature Min Max Industrial

-40°C

85°C

POTENTIOMETER CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

Test Conditions Min Typ Max Units R POT Potentiometer Resistance (-00)100k ?R POT Potentiometer Resistance (-50)50k ?R POT Potentiometer Resistance (-10)10k ?R POT

Potentiometer Resistance (-2.5) 2.5

k ?

Potentiometer Resistance

+20%

Tolerance R POT Matching 1

%Power Rating

25°C, each pot 50mW I W Wiper Current +6mA R W Wiper Resistance I W = +3mA @ V CC =3V 300

?R W Wiper Resistance I W = +3mA @ V CC = 5V

150?V TERM Voltage on any R H or R L Pin

V SS = 0V

GND

V CC

V V N

Noise (1)

TBD nV/ Hz Resolution 1.6

Absolute Linearity (2)R w(n)(actual)-R (n)(expected)(5)

+1LSB (4)Relative Linearity (3)

R w(n+1)-[R w(n)+LSB ](5)

+0.2

LSB (4)Temperature Coefficient of

+300

ppm/°C TC RPOT R POT (1)TC RATIO Ratiometric Temp. Coefficient (1)20

ppm/°C C H /C L /C W

Potentiometer Capacitances

(1)

10/10/25pF fc

Frequency Response

R POT = 50k ?(1)

0.4

MHz

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CAT5419

Document No. 2115, Rev. F

Symbol Parameter Min Typ Max Units f SCL Clock Frequency

400kHz T I (1)Noise Suppression Time Constant at SCL, SDA Inputs 50ns t AA SLC Low to SDA Data Out and ACK Out

0.9

μs t BUF (1)Time the bus must be free before a new transmission can start 1.2μs t HD:STA Start Condition Hold Time 0.6μs t LOW Clock Low Period 1.2μs t HIGH Clock High Period

0.6μs t SU:STA Start Condition SetupTime (for a Repeated Start Condition)0.6μs t HD:DAT Data in Hold Time 0ns t SU:DAT Data in Setup Time 100

t R (1)SDA and SCL Rise Time 0.3μs t F (1)SDA and SCL Fall Time 300

ns t SU:STO Stop Condition Setup Time 0.6μs t DH

Data Out Hold Time

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

CAPACITANCE

T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol Test Conditions Min

Typ

Max Units C I/O (1)Input/Output Capacitance (SDA)

V I/O = 0V 8pF C IN (1)

Input Capacitance (A0, A1, A2, A3, SCL, WP )

V IN = 0V

POWER UP TIMING (1)

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

Min Typ Max Units t PUR Power-up to Read Operation 1ms t PUW

Power-up to Write Operation

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

Test Conditions Min Typ Max Units I CC Power Supply Current f SCL = 400kHz

1mA I SB Standby Current (V CC = 5.0V)V IN = GND or V CC; SDA Open

1μA I LI Input Leakage Current V IN = GND to V CC 10μA I LO Output Leakage Current V OUT = GND to V CC

μA V IL Input Low Voltage -1V CC x 0.3V V IH Input High Voltage

V CC x 0.7

V CC + 1.0V V OL1

Output Low Voltage (V CC = 3.0V)

I OL = 3 mA

0.4

A.C. CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

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CAT5419

Document No. 2115, Rev. F

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Min Typ Max Units t WR

Write Cycle Time

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

SCL

SDA IN

SDA OUT

Figure 1. Bus Timing

STOP

CONDITION

START

CONDITION

ADDRESS

SCL

SDA

Figure 2. Write Cycle Timing

START BIT

SDA

STOP BIT

SCL

Figure 3. Start/Stop Timing

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Reference Test Method Min Typ Max Units N END (1)Endurance MIL-STD-883, Test Method 10331,000,000Cycles/Byte T DR (1)Data Retention MIL-STD-883, Test Method 1008100Years V ZAP (1)ESD Susceptibility MIL-STD-883, Test Method 3015

2000Volts I LTH (1)(2)

Latch-Up

JEDEC Standard 17

100

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.

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CAT5419

Document No. 2115, Rev. F

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CAT5419

Document No. 2115, Rev. F

WRITE OPERATIONS

In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5419. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register.The CAT5419 acknowledges once more and the Master generates the STOP condition, at which time if a non-volatile data register is being selected, the device begins an internal programming cycle to non-volatile memory.While this internal cycle is in progress, the device will not respond to any request from the Master device.Acknowledge Polling

The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host's write operation,the CAT5419 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5419 is still busy with the write operation, no ACK will be returned. If the CAT5419 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect against inadvertent programming of the non-volatile data registers. If the WP pin is tied to LOW, the data registers are protected and become read only. Similarly,WP pin going LOW after Start will interrupt non-volatile write to data registers, while WP pin going LOW after internal write cycle has started will have no effect on any write operation.The CAT5419 will accept both slave addresses and instructions, but the data registers are protected from programming by the device ’s failure to send an acknowledge after data is received.

Figure 6. Write Timing

Figure 5. Slave Address Bits

0101A3A2A1A0

CAT5419

*A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

**A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

C K

BUS ACTIVITY:

MASTER

SDA LINE

S T C K

SLAVE/DPP INSTRUCTION

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CAT5419

Document No. 2115, Rev. F

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

SLAVE ADDRESS BYTE

The first byte sent to the CAT5419 from the master/processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5419 are fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5419 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to V CC or V SS .INSTRUCTION BYTE

The next byte sent to the CAT5419 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The R1and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of two Wiper Control Registers. The format is shown in Table 2.

Table 1. Identification Byte Format

ID3ID2ID1ID0A3A2A1A001

(MSB)

(LSB)

Device Type Identifier

Slave Address

Table 2. Instruction Byte Format

I3I2I1I0R1R0 0P0(MSB)

(LSB)

Instruction Data Register WCR/Pot Selection

Opcode

Selection

Data Register Selected

R1R0DR000DR101DR210DR3

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CAT5419

Document No. 2115, Rev. F

Table 3. Instruction Set

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5419 contains two 6-bit Wiper Control Registers,one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details).Finally, it is loaded with the content of its data register zero (DR0) upon power-up.

The Wiper Control Register is a volatile register that loses its contents when the CAT5419 is powered-down.Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down.Data Registers (DR)

Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms.

If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data.

INSTRUCTIONS

Four of the nine instructions are three bytes in length.These instructions are:

—Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR —Write Wiper Control Register - change current

wiper position in the WCR of the selected potentiometer —Read Data Register - read the contents of the selected Data Register —Write Data Register - write a new value to the selected Data Register The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions

Note:

1/0 = data is one or zero

Instruction

Instruction Set

Operation

Read Wiper Control Register

10010001/0Read the contents of the Wiper Control Register pointed to by P0

Write Wiper Control Register

10100001/0Write new value to the Wiper Control Register pointed to by P0

Read Data Register 10111/01/001/0Read the contents of the Data Register pointed to by P0 and R1-R0

Write Data Register 11001/01/001/0Write new value to the Data Register pointed to by P0 and R1-R0

XFR Data Register to Wiper Control Register

1/0

Transfer the contents of the Data Register pointed to by P0 and R1-R0 to its associated Wiper Control Register

XFR Wiper Control Register to Data Register

11101/01/001/0

Transfer the contents of the Wiper Control Register pointed to by P0 to the Data Register pointed to by R1-R0

Gang XFR Data Registers to Wiper Control Registers 00011/01/000

Transfer the contents of the Data Registers pointed to by R1-R0 of both pots to their respective Wiper Control Register

Gang XFR Wiper Control Registers to Data Register 10001/01/000

Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of both pots

Increment/Decrement Wiper Control Register

00100001/0

Enable Increment/decrement of the Control Latch pointed to by P0

WCR0/P0

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CAT5419

Document No. 2115, Rev. F

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CAT5419

Document No. 2115, Rev. F

Figure 10. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)Write Wiper Control Register (WCR)Read Data Register (DR)Write Data Register (DR)SCL

SDA

R W

INC/DEC Command

Issued

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CAT5419

Document No. 2115, Rev. F

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CAT5419

Document No. 2115, Rev. F

Prefix Device #Suffix

Notes:

ORDERING INFORMATION

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CAT5419

Document No. 2115, Rev. F

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CAT5419

Document No. 2115, Rev. F

PACKAGING INFORMATION CON'T 24 Lead TSSOP (U)

0.25

0o - 8

DETAIL A

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CAT5419

Document No. 2115, Rev. F

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CAT5419

Document No. 2115, Rev. F

REVISION HISTORY

Date

Rev.Reason

10/8/2003E Updated Features Updated Description

04/01/04

Eliminated data sheet desingation

Update Description Update Pin Description Update Device Operation

Update Absolute Maximum Ratings

Update Recommended Operating Conditions Update Potentiometer Characteristics Update Write Protection Update Instructions

Update Ordering Information

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Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

https://www.wendangku.net/doc/b75385998.html, Publication #:2115 Revison:F

Issue date:04/02/04

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ?AE2 ?

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

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