PC104总线规范
PC/104 Specification
Version 2.5
November 2003
Please Note
This specification is subject to change without notice. While every effort has been made to ensure the accuracy of the material contained within this document, the PC/104 Embedded Consortium shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this specification. If errors are found, please notify the PC/104 Embedded Consortium.
PC/104is a trademark of the PC/104 Embedded Consortium. All other marks are the property of their respective companies.
Copyright 1992-2003, PC/104 Embedded Consortium
REVISION HISTORY
Version 1.0, March 1992 - Initial release.
Version 2.1, July 1994- Revised specification incorporating changes to conform with IEEE
P996.1 draft version D1.00:
a. Changed bus options. Eliminated the "option 2" configurations having right-angle P1 and P2
connectors. Created new "option 2" configurations similar to "option 1,” but without the
stackthrough pins. Added a statement indicating that a P2 connector may be included on 8- bit modules, if desired.
b. Added two additional mounting holes to 8-bit bus versions, making the mounting hole
patterns of both 8- and 16-bit modules identical.
c. Added an I/O connector region along the bus edge of the module.
d. Increased widths of I/O mating-connector regions from 0.4" to 0.5".
e. Changed lengths of I/O mating-connector regions so that their edges align with the outer
edges of the annular rings of adjacent mounting holes.
f. Reduced the bus drive requirement on the signals that had been specified at 6 mA to 4 mA.
g. Added specification of module power requirements.
h. In Appendix C, Section 3, changed minimum value of pullup resistance on shared interrupt
line from 10K to 15K ohms.
i. Added a section defining levels of PC/104 conformance.
Version 2.2, September 1994
a. Added correction sheet showing revised schematic for Appendix C.
Version 2.3, June 1996
a. Incorporated correction to Appendix C schematic.
b. Changed P2 connector Pin 1 designation in 16-bit module dimension drawings.
c. Added metric dimensions, including metric versions of module dimension drawings.
d. Minor formatting changes.
Version 2.4, August 2001
a. Added Appendix D Connector Specifications.
b. Removed all specific company references.
c. Corrected Consortium address and phone numbers
d. Added new reference for ISA specification
e. Cleaned up mechanical drawings
Version 2.5, November 2003
a. Reformatted and updated
1. New Chapter 2 “ISA Signal Definition” has been added
2. Chapter 3 “Electrical Specification” is now Chapter 4.
3. Chapter 4 “Levels of Conformance” is now Chapter 5.
4. Appendix D “Connector Specifications has been combined with Appendix A
b.Signal names have been updated to reflect the names referenced in Edward Solari’s book “ISA &
EISA Theory & Operation”
1. IOCHCHK* relabeled to IOCHK*
2. RESETDRV relabeled to RESET
3. ENDXFR* relabeled to SRDY*
4. SYSCLK relabeled to BCLK
5. MASTER* relabeled to MASTER16*
c. Mechanical drawings have been redone in AutoCAD showing both English and Metric units.
d.Contact finish female interface has been changed from 20 micoinches minimum to 15 microinches in
Figure 5
e.Mechanical performance withdrawal force has been change from 1 ounce minimum average to 1
ounce per pin minimum in Figure 5
TABLE OF CONTENTS
1. INTRODUCTION... (1)
1.1 References ... (1)
1.2 Contact Information ... (2)
2. MECHANICAL SPECIFICATIONS... .. (3)
2.1 Module Dimensions ... (3)
2.2 Module Stack Options... (3)
2.3 Key Locations ... (3)
3. ISA SIGNAL DEFINITION ... (5)
3.1 Address and Data ... . (5)
3.2 Cycle Control ... . (5)
3.3 Bus Control ... .. (6)
3.4 Interrupt... .. (6)
3.5 DMA ... (6)
4. ELECTRICAL SPECIFICATIONS ... (7)
4.1 Signal Assignments... .. (7)
4.2 Added Grounds ... . (7)
4.3 AC Signal Timing ... (7)
4.4 DC Signal Levels ... . (7)
4.5 Bus Drive Current ... (7)
4.6 Interrupt-Sharing Option ... . (8)
4.7 Bus Termination Option ... .. (8)
4.8 Module Power Requirements... . (8)
5. LEVELS OF CONFORMANCE ... .. (9)
5.1 PC/104 "Compliant" ... .. (9)
5.2 PC/104 "Bus-compatible" ... .. (9)
APPENDICIES
A. MECHANICAL DIMENSIONS... .......................................................................................... .. A-1
B. BUS SIGNAL ASSIGNMENTS... .......................................................................................... .. B-1
C. INTERRUPT-SHARING OPTION ... ................................................................................... ... C-1 C.1 Introduction ... ....................................................................................................................... .. C-2 C.2 Recommended Circuit ... ..................................................................................................... ... C-2 C.3 Restrictions ... ........................................................................................................................ .. C-3 C.4 "ISA Compatibility" Option Jumper ... ............................................................................... ... C-3
TABLE OF FIGURES
Figure 1: A Possible Module Stack Configuration ... ............................................................................. . 4 Figure 2: PC/104 8-bit Module Dimensions ...................................................................................... . A-2 Figure 3: PC/104 16-bit Module Dimensions ... ............................................................................... .. A-3 Figure 4: 8-bit and 16-bit ISA Bus Connector Dimensions ... ......................................................... .. A-4 Figure 5: 8-bit and 16-bit ISA Bus Connector Specifications ... ....................................................... . A-5 Figure 6: Typical Interrupt-Sharing Circuit ... ................................................................................... .. C-2
TABLE OF TABLES
Table 1: Module Power Requirements ... ............................................................................................ . 8 Table 2: 8-bit and 16-bit ISA Bus Signal Assignments ... ............................................................. .. B-2
PC/104 SPECIFICATION
Version 2.5 - March 2003
1. INTRODUCTION
While the PC and PC/AT architectures have become extremely popular in both general purpose (desktop) and dedicated (non-desktop) applications, its use in embedded microcomputer applications has been limited due to the large size of standard PC and PC/AT motherboards and expansion cards.
This document supplies the mechanical and electrical specifications for a compact version of the ISA (PC and PC/AT) bus, optimized for the unique requirements of embedded systems applications. The specification is herein referred to as "PC/104," based on the 104 signal
contacts on the two bus connectors (64 pins on P1, plus 40 pins on P2).
Briefly, the needs of embedded applications have been satisfied by PC/104, through the following key differences from standard ISA bus:
■ Reducing the form-factor, to 3.550 by 3.775 inches (90 by 96 mm).
■ Eliminating the need for backplanes or card cages, through its self-stacking bus.
■ Minimizing component count and power consumption (to typically 1-2 Watts per module), by reducing required bus drive on most signals to 4 mA.
PC/104 specifies two module versions —8-bit and 16-bit —which correspond to the PC and PC/AT bus implementations, respectively.
1.1 References
The remainder of this specification covers the differences from the ISA bus as detailed in
Edward Solari’s book ISA and EISA Theory and Operation published by Annabooks.
Designers of modules and systems based on PC/104 should be familiar with the ISA specification. It is available from:
Annabooks
12860 Danielson Court
Poway, CA USA 92064
Tel 800.462.1042 or 858.435.2000
Fax 858.391.5616
On the web at https://www.wendangku.net/doc/b75883921.html,
1.2 Contact Information
If errors are found in this document, please send a written copy of the suggested corrections to:
PC/104 Embedded Consortium
P.O. Box 78008
San Francisco, CA 94107-8008
Tel 415.243.2104
Fax 415.836.9094
E-mail info@https://www.wendangku.net/doc/b75883921.html,
Website https://www.wendangku.net/doc/b75883921.html,
2. MECHANICAL SPECIFICATIONS
2.1 Module Dimensions
PC/104 modules can be of two bus types, 8-bit and 16-bit. These correspond to the PC and
PC/AT buses, respectively. The detailed mechanical dimensions of these two PC/104 bus types are provided in Appendix A.
2.2 Module Stack Options
As shown in the figures in Appendix A, each of the two bus types (8-bit and 16-bit) offers two bus options, according to whether or not the P1 and P2 bus connectors extend through the module as "stackthrough" connectors. These options are provided to help meet the tight space requirements of embedded applications.
Figure 1 illustrates a typical module stack including both 8- and 16-bit modules, and shows the use of both the "stackthrough" and "non-stackthrough" bus options. As shown in Figure 1, when 8- and 16-bit modules are combined in a stack, the 16-bit modules must be stacked below (i.e., on the "secondary side" of) the 8-bit modules. A "passive" P2 bus connector may optionally be included in the design of 8-bit modules, to allow the use of these modules anywhere in a stack.
2.3 Key Locations
Key locations - consisting of omitted pins on P1 and P2, and plugged holes on J1 and J2 - have been designated on each bus connector, to help assure proper connector mating. See Appendix
B.
Figure 1: A Possible Module Stack Configuration
8-BIT (ISA)
PC/104
MODULE
16-BIT (ISA)
PC/104
MODULE
16-BIT (ISA)
PC/104
MODULE
A
3. ISA SIGNAL DEFINITION
For full details on the electrical requirements for the ISA bus and a complete description of ISA bus signal definitions, reference Edward Solari’s book ISA and EISA Theory and Operation
3.1 Address and Data
BALE Bus Address Latch Enable line is driven by the platform CPU to indicate when
SA<19:0>, LA<23:17>, AENx, and SBHE# are valid. It is also driven to a logical one
when an ISA add-on card or DMA controller owns the bus.
SA<19:0> Address lines are driven by the ISA bus master to define the lower 20 address
signal lines needed for the lower 1 MB of the memory address space.
LA<23:17> Latched Address lines are driven by the ISA bus master or DMA controler to
provide the additional address lines required for the 16 MB memory address space.
SBHE# System Byte High Enable line is driven by the ISA bus master to indicate that
valid data resides on the SD<15:8> lines.
AENx Address Enable line is driven by the platform circuity as an indication to ISA
resources not to respond to the ADDRESS and I/O COMMAND lines. This line is the
method by which I/O resources are informed that a DMA transfer cycle is occurring and
that only the I/O resource with an active DACKx# signal line can respond to the I/O
signal lines.
SD<15:0> Data lines 0 - 7 or 8 - 15 are driven for an 8 data bit cycle, and 0 - 15 are driven
for a 16 data bit cycle.
3.2 Cycle Control
MEMR# Memory Read line is driven by the ISA bus master or DMA controller to request a memory resource to drive data onto the bus during the cycle.
SMEMR# System Memory Read line is to request a memory resource to drive data onto the
bus during the cycle. This line is active when MEMR# is active and the
LA<23:20> signal lines indicate the first 1 MB of address space.
MEMW# Memory Write line is to request a memory resource to accept data from the data
lines.
SMEMW# System Memory Write line is to request a memory resource to drive data onto the bus during the cycle. This line is active when MEMW# is active and the
LA<23:20> signal lines indicate the first 1 MB of address space.
IOR# I/O Read line is driven by the ISA bus master or DMA controller to request an I/O resource to drive data onto the data bus during the cycle.
IOW# I/O Write requests an I/O resource to accept data from the data bus.
MEMCS16# Memory Chip Select 16 line is driven by the memory resource to indicate that it is an ISA resource that supports a 16 data bit access cycle. It also allows the ISA bus
master to execute shorter cycles.
IOCS16# I/O Chip Select 16 line is driven by an I/O resource to indicate that it is an ISA
resource that supports a 16 data bit access cycle. It also allows the ISA bus master to
execute shorter default cycles
IOCHRDY I/O Channel Ready line allows resources to indicate to the ISA bus master that
additional cycle time is required.
SRDY# Synchronous Ready (or NOWS# No-Wait-State) line is driven active by the
accessed resource to indicate that an access cycle shorter than the standard access
cycle can be executed.
3.3 Bus Control
REFRESH# Memory Refresh is driven by the refresh controller to indicate a refresh cycle
MASTER16# MASTER16# line is only driven active by an ISA add-on bus owner card that has been granted bus ownership by the DMA controller.
IOCHK# I/O Channel Check line is driven by any resource. It is active for a general error condition that has no specific interpretation.
RESET Reset line is driven active by the platform circuitry. Any bus resource that senses an active RESET signal line must immediately tri-state all output drivers and enter the
appropriate reset condition.
BCLK System Bus Clock line is a clock driven by the platform circuitry. It has a 50% ± approximately 5% (57 to 69 nanoseconds for 8 MHz) duty cycle, at a frequency of 6
to 8 MHz (± 500 ppm).
OSC Oscillator line is a clock driven by the platform circuitry. It has a 45 - 55 % duty cycle, at a frequency of 14.31818 MHz (± 500 ppm). It is not synchronized to any
other bus signal line.
3.4 Interrupt
IRQx Interrupt Request lines allow add-on cards to request interrupt service by the
platform CPU.
3.5 DMA
DRQx DMA Request lines are driven active by I/O resources to request service by the
platform DMA controller.
DACKx# DMA Acknowledge lines are driven active by the platform DMA controller to
select the I/O resource that requested a DMA transfer cycle.
TC Terminal Count line is driven by the platform DMA controller to indicate that all the data has been transferred.
4. ELECTRICAL SPECIFICATIONS
4.1 Signal Assignments
Signals are assigned in the same order as on the edgecard connectors of ISA, but transformed to the corresponding header connector pins. Signal assignments for the J1/P1 and J2/P2 connectors are given in Appendix B.
4.2 Added Grounds
Several ground pins have been added, to maximize bus integrity. See Appendix B.
4.3 AC Signal Timing
All PC/104 bus signals are identical in signal timing to their ISA counterparts.
4.4 DC Signal Levels
All PC/104 bus signal DC logic high and logic low voltage levels are identical to their ISA counterparts.
4.5 Bus Drive Current
To reduce component count and minimize power consumption and heat dissipation most bus signals have a reduced bus drive requirement of 4 mA. The exception is open collector driven signals which must drive 330 ohm pullup resistors defined by the ISA specification. This allows direct driving of the bus by many ASIC devices, and by HCT family logic.
Specifically, the following signals must be driven with devices capable of providing 20 mA sink current (as indicated in ISA):
MEMCS16*
IOCS16*
MASTER16*
SRDY*
All other signals may be driven with devices capable of providing 4 mA sink current.
4.6 Interrupt-Sharing Option
There is an optional means to share a single bus interrupt line among multiple interrupting devices. Appendix C provides a design guideline which can help ensure compatibility of interrupt-sharing among PC/104 modules.
4.7 Bus Termination Option
Termination of the 8-bit and 16-bit ISA bus signals may be desired in some systems to increase data integrity and system reliability. When termination is included, AC termination networks must be used to provide termination close to the characteristic impedance of the signal lines without exceeding the DC output current capabilities of the drivers.
As in the ISA standard, the recommended network consists of a resistor-capacitor network of 40- 60 ohms in series with 30-70 pF, connected between each bus signal and ground.
Whether termination is needed, and where it should be located, is dependent on the specific system configuration and must be determined by the system designer.
4.8 Module Power Requirements
The operating voltage range and maximum power requirements of each module are given in
Table 1. Each module shall not draw more than the operating current indicated. The total power requirement of a PC/104 module stack is the sum of that required by each of the modules in the stack. Operating voltages, which refer to the voltage measured at the appropriate bus connector pins of any given module, are specified to ±5 percent. Only those voltages required by modules in a system need be supplied to the bus.
Table 1: Module Power Requirements
5. LEVELS OF CONFORMANCE
This section provides terminology intended to assist manufacturers and users of PC/104 bus- compatible products in defining and specifying conformance with the PC/104 Specification. 5.1 PC/104 "Compliant"
This refers to "PC/104 form-factor" devices that conform to all non-optional aspects of the PC/104 Specification, including both mechanical and electrical specifications.
5.2 PC/104 "Bus-compatible"
This refers to devices which are not "PC/104 form-factor" (i.e., do not comply with the module dimensions of the PC/104 Specification), but provide a male or female PC/104 bus connector that meets both the mechanical and electrical specifications provided for the PC/104 bus connector.
APPENDIX A MECHANICAL DIMENSIONS
Figure 2: PC/104 8-bit Module Dimensions Dimensions are in inches / (millimeters)
Figure 3: PC/104 16-bit Module Dimensions Dimensions are in inches / (millimeters)
Figure 4: 8-bit and 16-bit ISA Bus Connector Dimensions Dimensions are in inches/(millimeters)
Figure 5: 8-bit and 16-bit ISA Bus Connector Specifications MATERIALS
Housing:
Contact:
Solder:
Solder Clip:
CONTACT FINISH
Female Interface:
Male Interface:
Solder Tail:
Underplate:
MECHANICAL PERFORMANCE Insertion Force:
Withdrawal Force:
Normal Force:
Durability:
Operating Temp:
ELECTRICAL PERFORMANCE Contact Resistance:
Current Capacity:
Dielectric Strength:
Insulation Resistance: High Temp Thermoplastic, UL Rated 94-V0 Phosphor Bronze
Tin-Lead (63-37), If Applicable Aluminum Alloy, If Applicable
15 Microinches Minimum Hard Gold Gold Flash Minimum
100 Microinches Minimum Solder
50 Microinches Minimum Nickel
3.5 Ounce Per Pin Maximum
1 Ounce Per Pin Minimum
50 Grams Minimum (Per Beam)
50 Cycles Minimum
-55° C To +85° C
<30 Milliohms Maximum
1 Amp Continuous Per Pin
1000 Vac
5,000 Megohms Minimum