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HSMP-382x

HSMP-382x, 482x

Surface Mount RF PIN Switch and Limiter Diodes

Data Sheet

Features

? Diodes Optimized for:Low Current Switching Low Distortion Attenuating ? Power Limiting/Circuit Protection

? Surface Mount SOT-23 and SOT-323 Packages Single and Dual Versions

Tape and Reel Options Available ? Low Failure in Time (FIT) Rate [1]? Lead-free

Note:

1. For more information see the Surface Mount PIN Reliability Data Sheet.

Package Lead Code Identifi cation, SOT-323 (Top View)

Description/Applications

The HSMP-382x series is o ptimized for switch i ng ap-plications where ultra-low resistance is required. The HSMP-482x diode is ideal for limiting and low induc-tance switching applications up to 1.5 GHz.

A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime.

Package Lead Code Identifi cation, SOT-23 (Top View)

SERIES

Absolute Maximum Ratings [1] T C = +25°C

Symbol Parameter

Unit

SOT-23

SOT-323

I f

Forward Current (1 μs Pulse) Amp 1 1P IV Peak

Inverse Voltage V 50

50T j Junction Temperature °C 150 150T stg

Storage Temperature

°C

-65 to 150

θjc Thermal

Resistance [2] °C/W 500 150Notes:

1. Operation in excess of any one of these conditions may result in permanent damage to the device.

2. T C = +25°C, where T C is defi ned to be the temperature at the package pins where contact is

made to the circuit board.

Minimum Maximum Typical Maximum Typical

Part Package Breakdown Series Total Total Total Number Marking Lead Voltage Resistance Capacitance Capacitance Inductance HSMP- Code Code Confi guration V BR (V) R S (Ω) C T (pF) C T (pF) L T (nH) 4820 FA A Dual Anode 50

0.6

0.75 1.2 1.0 482B

A Dual Anode Test Conditions V R = V BR

I F = 10 mA f = 1 MHz

f = 1 MHz f = 500 MHz –

Measure V R = 20 V

V R = 0 V

3 GHz

I R ≤ 10 μA

High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes

Electrical Specifi cations T C = 25°C

Package Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Confi guration Voltage V BR (V) R S (Ω) C T (pF) 3820 F0

0 Single 50

0.6

0.8

3822 F2 2 Series 3823 F3 3 Common Anode 3824 F4

4 Common Cathode

T est Conditions

V R = V BR f = 100 MHz

f = 1 MHz

Measure I F = 10 mA V R = 20 V

I R ≤ 10 μA

Typical Parameters at T C = 25°C

Part Number

Series Resistance

Carrier Lifetime

Reverse Recovery Time

Total Capacitance

HSMP- R S (Ω)

τ (ns)

T rr (ns)

C T (pF)

382x

1.5 70 7 0.60 @ 20 V

T est Conditions f = 100 MHz I F = 10 mA

V R = 10 V

I F = 10 mA

I F = 20 mA

90% Recovery

Typical Parameters at T C = 25°C (unless otherwise noted), Single Diode

Typical Applications for Multiple Diode Products

RF 2

Figure 7. Simple SPDT Switch, Using Only Positive Current.Figure 8. High Isolation SPDT Switch, Dual Bias.

RF COMMON

RF 1

Typical Applications for Multiple Diode Products, continued

BIAS

Figure 9. Switch Using Both Positive and Negative Bias Current.Figure 10. Very High Isolation SPDT Switch, Dual Bias.

Figure 11. High Isolation SPST Switch (Repeat Cells as Required.

Figure 12. Power Limiter Using HSMP-3822 Diode Pair. See Application Note 1050 for details.

RF 2

Typical Applications for HSMP-482x Low Inductance Series

Microstrip Series Connection for HSMP-482x Series

In order to take full advantage of the low inductance of the HSMP-482x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 14.

Figure 16. Equivalent Circuit.

Co-Planar Waveguide Shunt Connection for HSMP-482x Series

Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 17. Since it eliminates the need for via holes to ground, it off ers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. See

AN1050 for details.

GROUND BY TWO

VIA HOLES

Figure 13. Internal Connections.

Figure 14. Circuit Layout.

Microstrip Shunt Connections for HSMP-482x Series

In Figure 15, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-482x diode are placed across the resulting gap. This forces the 0.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass fi lter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nH of shunt inductance external to the diode

is created by the via holes, and is a good estimate for 0.032" thick material.

Figure 15. Circuit Layout, HSMP-482x Limiter.

Figure 17. Circuit Layout.Figure 18. Equivalent Circuit.

Center Conductor

Assembly Information

SOT-323 PCB Footprint

A recommended PC

B pad layout for the miniature SOT-323 (SC-70) package is shown in Figure 19 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance.

0.079

Dimensions in inches

0.031Dimensions in

inches mm

Figure 19. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products.

SOT-23 PCB Footprint

Figure 20. Recommended PCB Pad Layout for Avago’s SOT-23 Products.

SMT Assembly

Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase refl ow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-323/-23 package, will reach solder refl ow temperatures faster than those with a greater mass. Avago’s diodes have been qualifi ed to the time-temperature profi le shown in Figure 21. This profi le is representative of an IR refl ow type of surface mount assembly process.

After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones.

The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The refl ow zone briefl y elevates the temperature suffi ciently to produce a refl ow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause d eformation o f t he b oard o r d amage t o c omponents due to thermal shock. The maximum temperature in the refl ow zone (T MAX ) should not exceed 260°C. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refl ow of solder.

Figure 21. Surface Mount Assembly Profi le.

T e m p e r a t u r e

T Lead-Free Refl ow Profi le Recommendation (IPC/JEDEC J-STD-020C)

Refl ow Parameter

Lead-Free Assembly

Average ramp-up rate (Liquidus Temperature (T S(max) to Peak)3°C/ second max Preheat

Temperature Min (T S(min))150°C Temperature Max (T S(max))200°C

Time (min to max) (t S )

60-180 seconds Ts(max) to TL Ramp-up Rate 3°C/second max Time maintained above:

Temperature (T L )217°C

Time (t L )

60-150 seconds Peak Temperature (T P ) 260

+0/-5°C Time within 5 °C of actual Peak temperature (t P )20-40 seconds Ramp-down Rate

6°C/second max Time 25 °C to Peak Temperature

8 minutes max

Note 1: All temperatures refer to topside of the package, measured on the package body surface

Package Characteristics

Lead Material .......................................................Copper (SOT-323); Alloy 42 (SOT-23)Lead Finish ............................................................................Tin 100% (Lead-free option)Maximum Soldering Temperature ...............................................260°C for 5 seconds Minimum Lead Strength ..............................................................................2 pounds pull Typical Package Inductance ..........................................................................................2 nH Typical Package Capacitance .................................................0.08 pF (opposite leads)

Ordering Information

Specify part number followed by option. For example: HSMP - 382x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code

Surface Mount PIN

Option Descriptions

-BLKG = Bulk, 100 pcs. per antistatic bag

-TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel

Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.”

Package Dimensions

Outline 23 (SOT-23)

Outline SOT-323 (SC-70)

Notes:

XXX-package marking Drawings are not to scale

DIMENSIONS (mm)MIN.0.790.0000.300.082.731.150.891.780.452.100.45

MAX.1.200.1000.540.203.131.501.022.040.602.700.69

SYMBOL

A A1

D E1e e1e2E

Notes:

XXX-package marking Drawings are not to scale

DIMENSIONS (mm)MIN.0.800.000.150.081.801.101.800.26MAX.1.000.100.400.252.251.402.400.46

SYMBOL A A1B C D E1e e1E L

1.30 typical 0.65 typical

Tape Dimensions and Product Orientation For Outline SOT-23

Device Orientation

For Outlines SOT-23/323

DESCRIPTION

SYMBOL SIZE (mm)SIZE (INCHES)LENGTH WIDTH DEPTH PITCH

BOTTOM HOLE DIAMETER A 0B 0K 0P D 1 3.15 ± 0.102.77 ± 0.101.22 ± 0.104.00 ± 0.101.00 + 0.050.124 ± 0.0040.109 ± 0.0040.048 ± 0.0040.157 ± 0.0040.039 ± 0.002CAVITY

DIAMETER PITCH POSITION D P 0E 1.50 + 0.104.00 ± 0.101.75 ± 0.100.059 + 0.0040.157 ± 0.0040.069 ± 0.004PERFORATION

WIDTH THICKNESS

W t18.00 +0.30 –0.100.229 ± 0.0130.315 +0.012 –0.0040.009 ± 0.0005CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION)CAVITY TO PERFORATION (LENGTH DIRECTION)

F P 2

3.50 ± 0.052.00 ± 0.05

0.138 ± 0.0020.079 ± 0.002

DISTANCE BETWEEN CENTERLINE

Tape Dimensions and Product Orientation For Outline SOT-323

For product information and a complete list of distributors, please go to our web site: https://www.wendangku.net/doc/be7509025.html, Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright ? 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-4026EN AV02-1395EN - April 24, 2012

(CARRIER TAPE THICKNESS)

DESCRIPTION

SYMBOL SIZE (mm)SIZE (INCHES)LENGTH WIDTH DEPTH PITCH

BOTTOM HOLE DIAMETER A 0B 0K 0P D 1 2.40 ± 0.102.40 ± 0.101.20 ± 0.104.00 ± 0.101.00 + 0.250.094 ± 0.0040.094 ± 0.0040.047 ± 0.0040.157 ± 0.0040.039 + 0.010CAVITY

DIAMETER PITCH POSITION D P 0E 1.55 ± 0.054.00 ± 0.101.75 ± 0.100.061 ± 0.0020.157 ± 0.0040.069 ± 0.004PERFORATION

WIDTH THICKNESS W t 18.00 ± 0.300.254 ± 0.020.315 ± 0.0120.0100 ± 0.0008CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION)CAVITY TO PERFORATION (LENGTH DIRECTION)

F P 2 3.50 ± 0.052.00 ± 0.050.138 ± 0.0020.079 ± 0.002

DISTANCE

FOR SOT-323 (SC70-3 LEAD)An

8C MAX FOR SOT-363 (SC70-6 LEAD)

10C MAX

ANGLE

WIDTH

TAPE THICKNESS C T t 5.4 ± 0.100.062 ± 0.0010.205 ± 0.0040.0025 ± 0.00004COVER TAPE