开关电源PCB布局指南英文版

SIMPLE SWITCHER ?PCB Layout Guidelines

INTRODUCTION

One problem with writing an Application Note on PCB layout is that the people who read it are usually not the ones who are going to use it.Even if the designer has struggled through electromagnetic fields,EMC,EMI,board parasitics,transmission line effects,grounding,etc.,he will in all prob-ability then go on with his primary design task,leaving the layout to the CAD/layout person.Unfortunately,especially when it comes to switching regulators,it is not enough to be concerned with just basic routing/connectivity and mechani-cal issues.Both the designer and the CAD person need to be aware that the design of a switching power con-verter is only as good as its layout.Which probably ex-plains why a great many of customer calls received,con-cerning switcher applications,are ultimately traced to poor layout practices.Sadly,these could and should have been avoided on the very first prototype board,saving time and money on all sides.

The overall subject of PCB design is an extremely wide one,embracing several test/mechanical/production issues and also in some cases compliance/regulatory issues.There is also a certain amount of physics/electromagnetics involved,if a clearer understanding is sought.But the purpose of this Application Note is to reach the audience most likely to use it.Though there is enough design information for the more

experienced designer/CAD person,the Application Note in-cludes a quick-set of clear and concise basic rules that should be scrupulously followed to avoid a majority of prob-lems.In particular,we have provided recommended start-ing points for layout when using the popular LM267x,LM259x and LM257x families (Figure 2)The focus is on the step-down (Buck)Simple Switcher ICs from National,but the same principles hold for any topology and switching power application.

Most of the issues discussed in this Note revolve around simply assuring the desired performance in terms of basic electrical functionality.Though luckily,as the beleaguered switcher designer will be happy to know,in general all the electrical aspects involved are related and point in the same general ‘direction’.So for example,an ‘ideal’layout,i.e.one which helps the IC function properly,also leads to reduced electromagnetic emissions,and vice-versa.For example,reducing the area of loops with switching currents will help in terms of EMI and performance.However the designer is cautioned that there are some exceptions to this general ’trend’.One which is brought out in some detail here is the practice of ’copper-filling’,which may help reduce parasitic inductances and reduce noise-induced IC problems,but can also increase EMI.

Quick-Set of Rules for SIMPLE SWITCHER PCB Layout (Buck)

a)Place the catch diode and input capacitor as shown in Figure 2.

b)For high-speed devices (e.g.LM267x)do not omit placing input decoupling/bypass ceramic capacitor (0.1μF–0.47μF)as in Figure 2.

c)Connect vias to a Ground plane if available (optional,marked ‘X’in Figure 2)

d)If vias fall under tab of SMT power device,these are considered ‘thermal vias’.Use correct dimensions as discussed to avoid production issues.Or place the vias close to but not directly under the tab.

e)Route feedback trace correctly as discussed,away from noise sources such as the inductor and the diode.f)Do not increase width of copper on switching node injudiciously.

g)If very large heatsink area is required for catch diode (having estimated the heatsink requirement correctly)use isolation as discussed.

h)

For higher power SMT applications,use 2oz board for better thermal management with less copper area.

SIMPLE SWITCHER is a Registered Trademark of National Semiconductor.

National Semiconductor Application Note 1229Sanjaya Maniktala July 2002

SIMPLE SWITCHER PCB Layout Guidelines

AN-1229

?2002National Semiconductor Corporation https://www.wendangku.net/doc/b57875859.html,

INTRODUCTION

(Continued)

THE AC AND DC CURRENT PATHS

Referring to Figure 1a ,the bold lines represents the main (power)current flow in the converter during the time the switch is ON.As the switch turns ON,the edge of the of the current waveform is provided largely by CBYPASS,the re-mainder coming mainly from CIN.Some slower current com-ponents come from the input DC power supply (not shown)and also refresh these input caps.Figure 1b represents the situation when the switch is OFF.We can therefore see that in certain trace sections,current has to start flowing sud-denly during the instant of switch turn-off and in some sec-tions it needs to stop flowing equally suddenly.Figure 1c

represents the ‘difference’,i.e.traces shown bold in this Figure are those where the current flow changes suddenly .During the turn-on transition the picture reverses,but the ’difference’trace sections are the same.Therefore during either switch transition,’step changes’of current take place in these difference sections.These traces encounter the harmonic-rich rising or trailing edges of the current pedestal waveform.The difference traces are considered ’critical’and deserve utmost attention during PCB layout.It is often stated colloquially,that ‘AC current’flows in these trace sections,and ’DC current’in the others.The reason is that the basic switching PWM frequency forms only a fraction of the total harmonic (Fourier)content of the current waveform in the ’AC’traces.In comparison,where ‘DC current’flows,the

20042601

FIGURE 1.

A N -1229

https://www.wendangku.net/doc/b57875859.html,

2

THE AC AND DC CURRENT PATHS (Continued)

current does not change in a stepped fashion and so the harmonic content is lower.It is also no surprise that the DC sections are those in series with the main inductor,because it is known that inductors have the property of preventing sudden changes in current(this is analogous to a capacitor which‘resists’sudden changes in voltage).

Summing up:In switching regulator layout,it is the AC paths that are considered critical,whereas the DC paths are not.That is the only basic rule to be kept in mind, and from which all the others follow.This is also true for any topology.Perform an analysis of the current flow for any topology in the same manner as we did for the Buck,to find the’difference traces’:and these traces are by defintion the’critical’ones for layout.

What is the problem with step current changes anyway?In a resistor for example,this causes no unexpected/ unidentifiable problem.The voltage is given by V=IR,and so for a given change of current,the voltage will change pro-portionally.For example,a0.5cm wide Cu trace of thick-ness1.4mil has a resistance of1milliohm per cm length (at20degC).So it seems that a1inch long trace with a current changeover of1A,would produce a change in volt-age of only2.5millivolts across the trace,which is insignifi-cant enough to cause the control sections of most ICs to misbehave.But in fact the induced voltage is much larger. The important thing to realize is that traces of copper on a PCB,though barely resistive,are also inductive.Now,the oft-repeated thumb-rule is that‘every inch of trace length has an inductance of about20nH’.Like the trace resis-tance,that too doesn’t seem much at first sight.But it is this rather minute inductance which is in fact responsible for a great many customer calls in SIMPLE SWITCHER applica-tions!

The equation for voltage across an inductance is V=L*dl/dt, and so the voltage does not depend on the current but on the rate of change of the current.This fact makes all the differ-ence when the1A change we spoke about occurs within a very short time.The induced voltage can be very high,even for small inductances and currents,if the dl/dt is high.A high dl/dt event occurs during transition from Figure1a to Figure 1b(and back)in all the AC trace sections(shown bold in Figure1c).The induced voltage spike appears across each affected trace,lasting for the duration of the crossover.

To get a better feel for the numbers here:the change in current in the AC sections of a typical buck converter is about 1.2times the load current during the switch turn-off transition and is about0.8times the load current during the switch turn-on transition(for an’optimally’designed Buck inductor,as per inductor design guidelines in the relevant Datasheets/Selection Software).The transition time is about30ns for high speed Fet switchers like the LM267x,and is about75ns for the slower bipolar switchers like the LM259x series.This also incidentally means that the voltage spikes in the high-speed families can be more than twice that in the slower families,for a comparable layout and load.Therefore layout becomes all the more critical in high-speed switchers.

So,one inch of trace switching say1A of instantaneous current in a transition time of30ns gives0.7V,as compared to 2.5mV(that we estimated on the basis of resistance alone).For3A,and two inches of trace,the induced voltage ’tries’to be4V!In Figure1c,the small triangles along the sections indicate the direction of the momentary induced

voltage,as the converter changes from the situation in Fig-

ure1a to that in Figure1b(switch turn-off).We can see that

assuming that the ground pin of the IC is the reference point,

the switching node(marked‘SW’)tries to go negative(all its

series trace sections adding up).Similarly the input pin

(marked‘VIN’goes high through series contributions in all its

related sections.Figure1c represents the picture during the

turn-off transition.During the turn-on transition all the in-

duced voltage polarities shown are simply reversed.In that

case,the VIN pin is dragged low,and the switching node pin

is dragged high momentarily.

The astute designer will recognize that this was to be ex-

pected since any inductance,even if it is parasitic,demands

to be‘reset’,which means that the volt-seconds during the

on-time must equal and be opposite in sign to the

volt-seconds during the off-time.The designer will also real-

ize that till these parasitic trace inductances reset,they do

not’allow’the crossover to occur.So for example,traces

which were carrying current prior to switch turn-off will’insist’

on carrying current till the voltage spikes force them to do

otherwise.Similarly,the traces which need to start carrying

current will’refuse’to do so till the spikes across them force

them to do likewise.Since switching losses are proportional

to crossover time,even if these voltage spikes do not cause

anomalous behavior,they can degrade efficiency.For ex-

ample,in transformer-based flyback regulators,when the the

primary number of turns is much larger than the secondary

turns,designers may be surprised to learn how much the

secondary side trace inductances alone can degrade effi-

ciency.This is because any secondary side uncoupled

(trace/transformer leakage)inductances reflect into the

primary side as an equivalent parasitic inductance in

series with the switch.This adds an additional term to

the effective leakage as seen by the switch that equals

the secondary inductance multiplied by square of the

turns ratio(turns ratio being Np/Ns).Therefore the dissipa-

tion in the flyback clamp(zener/RCD)can increase dramati-

cally,lowering efficiency.One lesson here is that though

’leakage inductance’(from traces or the transformer)is con-

sidered’uncoupled’,in reality it can make its presence se-

verely felt from one side of the transformer to the other.So it

is not totally’uncoupled’at all!In fact this happens to be the

main reason why flybacks with low output voltages(high

turns ratio)show poorer efficiency as compared to higher

output flybacks.Therefore,reducing critical trace induc-

tances is important for several reasons:efficiency,EMI,be-

sides basic functionality.

The momentary voltage spikes which last for the duration of

the transition can be very hard to capture on an oscilloscope.

But they may be presumed to be present if the IC is seen to

be misbehaving for no’obvious reason’.These spikes,if

present with sufficiently high amplitude,can propagate into

the control sections of the IC causing what we call here a

controller’upset’.This leads to the observed performance

anomalies,and in rare cases this can even cause device

failure.Since none of these spike-related problems can be

easily corrected,or band-aided,once the layout is initially

bad,the important thing is to get the layout‘right’to start

with.

The designer may well ask,why is it that these step current

changes are a problem with the parasitic trace inductances,

and not with the main inductor of the Buck converter?That is

because all inductors try to resist any sudden current

change.But since the main inductor has a much larger

inductance(and energy storage)as compared to the para-

sitic trace inductances,it therefore ends up‘dominating’.

AN-1229

https://www.wendangku.net/doc/b57875859.html,

3

THE AC AND DC CURRENT PATHS

(Continued)

From V *dt=L *dl we can also see that if L is large,a much higher voltseconds (V *dt)is required to cause a given change in current.The trace inductances therefore simply ’give in’first before the main inductor does.But they certainly don’t go down without a fight...and the voltage spikes bear testimony to this!

Notice that the currents in the signal traces in the schematic are not shown.For example those connected to the com-pensation node (marked ‘COMP’)or bootstrap (marked ‘BOOST’)carry relatively minute currents and therefore are not likely to cause upsets.They are therefore not critical and can be routed relatively ‘carelessly’.The feedback trace is an exception,and will be discussed later.The Ground pin of the IC is another potential entry point of noise pickup.Inex-perienced designers often grossly under estimate the needs of this pin,particulary for Buck converters.They assume that since the main power flow in a Buck converter does not pass through the ground pin,the ‘current through the ground pin is very low’,and therefore the trace length leading up to this pin is not critical.In fact,though the average current through this pin is very low,the peak current or its dl/dt is not.Consider the switch driver as shown schematically in Figure 1.Clearly it needs to supply current to drive the switch.In any Fet operated as a switch,large peak to peak instantaneous current spikes are needed to charge and discharge the gate capacitance.This is essential so as to cause the Fet to switch fast,and this reduces the switching/crossover losses inside the switch and improves the overall efficiency of the converter.(Actually,in a practical IC,the ‘spike’of current comes from the bootstrap capacitor,and then the bootstrap capacitor is quickly refreshed by the internal circuitry of the IC ----it is the refresh current that passes through the ground pin).Further,as in any high-speed digital IC,parts of the internal circuitry,clocks,gates,comparators etc.,can turn on and off suddenly,leading to small but abrupt changes in the current through the ground pin.This can cause ’ground bounce’which in turn can lead to controller upsets.There-fore the length of the trace to the Ground pin also needs to be kept as small as possible.This also implies that the input capacitors,especially the bypass capacitor ‘CBYPASS’should be placed very close to the IC ,even for a Buck IC.

PLACING COMPONENTS ‘acap’(as close as possible)

One has heard this before:“component X needs to be ‘acap’”.Soon we are told the “component Y too needs to be ‘acap’”.Then “Z too”.And so on.Which would be physically impossible because matter cannot occupy the same place at the same time!So which one comes first?This is the million-dollar predicament always facing switcher layout.

The troubling trace lengths are those indicated Figure 1c .To keep them small,clearly two components need to be acap.These are the input bypass capacitor and also the catch diode.Consider the input capacitor section first.

In the schematic there are in two input capacitors shown.These are marked ‘CIN’and ‘CBYPASS’respectively.The purpose of the total input capacitance is to reduce the volt-age variations at the input pin.The variations are mainly due to the pulsed input current waveshape,as demanded by a Buck topology.Note that for this particular topology,the output capacitor current is smooth (because the inductor is in series with it).In a Boost topology the situation is re-versed:i.e.the input capacitor current is smooth and the current into the output capacitor is pulsed.This makes the demand for input decoupling less stringent than in a Buck (or Buck-Boost).In a Buck-Boost or ’flyback’,both the input and the output capacitor currents are pulsed,and input decou-pling is required not only for the control-section/drivers of the IC but for the input current step waveform of the power stage.Designers familiar with a Cuk topology know that in this case both input and output currents are smooth.The Cuk converter is therefore often called the ’ideal DC to DC’converter,and expectedly its parasitic inductances can be largely ignored ----because there are no AC trace sections in the sense we described.

Now if the input power to a Buck converter was coming through long leads from a distant voltage source,the induc-tance of the incoming leads would seriously inhibit their ability to provide the fast changing pulsed current shape.So an on-board source of power is required right next to the converter,and this is provided by the input capacitor.It provides the pulsed current,and then is itself refreshed at a slower rate (DC current)from the distant voltage source.However,since the input capacitor is fairly large in size,it may not be physically possible to place it as close as de-sired.Especially for very high speed switchers such as the LM267x series (note that a ‘high speed’switcher as de-fined here,is one with a very small crossover/transition time,and it does not necessarily have to be one with a high switching frequency ).In addition,the Equivalent Se-ries Resistance (‘esr’)and Equivalent Series Inductance (‘esl’)of the main input capacitor may be too high,and this can cause high frequency input voltage ripple on the VIN pin.For the Buck converter schematic as shown in Figure 1,the input pin connects not only to the Drain of the Fet switch,but also provides a low internally regulated supply rail to the control sections of the IC.But no real series pass regulator can ’hold off’very fast changes in the applied input voltage.Some noise will feed through into the control section and then much will depend on the internal sensitivity of the IC to noise (related to its design,internal layout,process/logic family).It is therefore best to try to keep voltage on the VIN pin fairly clean --—from a high frequency point of view.Note that it is not being suggested here that one responds to this statement by increasing the input capacitance indiscrimi-nately,because we are not talking about the natural input voltage ripple which occurs at the rate of the switching frequency (e.g.100kHz–260kHz).Our concern here is the noise occurring at the moment of the transitions,and this noise spectrum peaks at around 10MHz–30MHz,as deter-mined by the transition/crossover time of the switch.The crossover time has nothing to do with the basic PWM switch-ing frequency,but does ofcourse depend on the type of switch used i.e.bipolar or Fet.

Therefore a high frequency ‘bypass’or ‘decoupling’capacitor with small or no leads,shown as ‘CBYPASS’in Figure 1,is to be placed very close to the VIN and GND pins of the IC.This is usually a 0.1μF–0.47μF (monolithic)multilayer ceramic (typically X7R type,size 1206or the more recent ’inverted’termination version of this popular size,the ’0612’----also note that smaller sized ceramic caps generally have higher esr/esl,but check before use).Since now this com-ponent provides the main pulsed current waveshape,the bulk capacitor shown as ‘CIN’,may be moved slightly further up (about an inch)without any deleterious effect.For lighter loads,and if it is possible to place the input bulk capacitor very close to the IC,the high frequency bypass capacitor may sometimes be omitted.But for high-speed switchers

A N -1229

https://www.wendangku.net/doc/b57875859.html,

4

PLACING COMPONENTS‘acap’(as close as possible)(Continued)

like the LM267x,the input ceramic bypass capacitor is considered almost mandatory for any application.

The position of the catch diode is also critical.It too needs to be acap.Now,every topology has a node called the’switch-ing node’.This is the’hot’or’swinging’end of the switch.For integrated switchers,this node can also be an easy entry point for noise feed-through into the control sections.Note that the problem is not caused by the simple fact that the voltage at this node swings,for it is designed for exactly that situation in mind.The problem is with the additional noise spikes riding on top of the basic square voltage waveform, arising from the trace inductances as explained earlier. Therefore,it is essential to place the catch diode very close to the IC and connect it directly to the SW pin and GND pins of the IC,with traces that are very short and fairly wide.In some erroneous layouts,where the catch diode was not appropriately placed to start with,the con-verter could be‘bandaided’by a small series RC snubber. This consists typically of a resistor(low inductive type preferred)of value10?–100?and a capacitor,which should be ceramic of value470pF–https://www.wendangku.net/doc/b57875859.html,rger capaci-tance than this would lead to unacceptably higher dissipation (=1/2*C*V2*f),chiefly in the resistor,and would serve no additional purpose.However,note that this RC snubber needs to be placed very close to and across the Switch-ing pin and Gnd pin of the IC,with short leads/traces. Sometimes designers think that this is’across the diode’,

because on the schematic there is no way to tell the differ-

ence.However,particularly when the diode is a Schottky,the

primary purpose of such a snubber is to absorb the voltage

spikes of the trace inductances.Therefore its position must

be such that it provides bypassing of the critical or AC trace

sections of the output side as shown in Figure1c(right hand

side of the switcher)----which means it must be close to the

IC.Of course,as mentioned previously,it is best to get the

layout right to start with,rather than adding such extra

components.

Remaining component placements can be taken up only

after the input bypass capacitor and the catch diode are

firmly in place and are both acap.The traces to either of

these two components should be short,fairy wide,and

should not go pass through any vias on the way to the IC.

For SMT boards this implies that the input capacitor and

catch diode are on the same layer as the IC.In Figure2

suggested PCB starting points are provided for several

switchers.All of them focus on placing these two critical

components correctly.These layouts are strongly recom-

mended for most applications.The’X’marks suggest the

recommended location where vias can be used to con-

nect to a Ground Plane(if present).The remaining compo-

nents can be placed relatively carelessly(though in doing so,

there may be slight impact,for example on the accuracy of

the output voltage rail and its ripple,but nothing compared to

what can happen if the input decoupling cap and catch diode

are incorrectly placed).Trace routing is now discussed in

more detail.

AN-1229

https://www.wendangku.net/doc/b57875859.html,

5

PLACING COMPONENTS ‘acap’(as close as possible)

(Continued)

ROUTING THE TRACES

As mentioned above,it is not advisable to route any of the critical traces through ‘vias’.Vias are considered useful from a purely CAD perspective for ‘layer jumping’,but are often used indiscriminately as they seem an easy solution to con-nectivity problems.But they also add impedance,and that is exactly what we are trying to avoid.The inductance of a via is given by

where ‘h’is the height of the via in mm (equal to the thick-ness of the board,commonly 1.6mm),and ‘d’is the diam-eter in mm.Therefore a single via of diameter 0.4mm on a standard 1.6mm board gives an inductance of 1.2nH.It may not sound much,but it is almost twice that of a wire of the same length and diameter.It has been seen empirically that for the high speed LM267x series,if the bypass capacitor is connected through vias to the IC,occa-sional field problems do arise.So if vias have to be used

for some reason,several vias in parallel will yield better results than a single via.And larger via diameters would help further (unless they are being used as ’thermal vias’---discussed later).

It is also said that “the traces also need to be ‘wide’and ‘short’”.The necessity of short traces is clearly understood,usually intuitively,by most engineers.In fact the thumbrule of ‘20nH per inch’also implies that trace inductance is almost proportional to length.However,a common ‘intuitive’mis-take is to assume that inductance is inversely propor-tional to the width of the trace .So some engineers mis-takenly ‘add copper’lavishly to critical traces (though there are some other reasons why this may be being done,and these will be discussed later).A first approximation for the inductance of a conductor having length ‘l’and diameter ‘d’is

where l and d are in centimeters.Note that the equation for a PCB trace is not much different from that of a wire.

20042602

FIGURE 2.Recommended Layout Starting Points

A N -1229

https://www.wendangku.net/doc/b57875859.html, 6

ROUTING THE TRACES

(Continued)

where ‘w’is the width of the trace.For PCB traces,L hardly depends on the thickness of the copper (1oz or 2oz board).Both the above equations are plotted in Figure 3.It will be seen that for a given length,a PCB trace of width ‘x’has higher inductance than a wire of diameter ‘x’.In fact the width of a PCB trace has to be about 1.78times the diameter of a wire for the same inductance .

A wire of AWG 20has a diameter of 32mils (or 0.081cm).So for a length of one inch (1000mils or 2.54cm)L equals 21nH (which is the usual thumbrule).We can see that L is almost proportional to length.But if we double the diameter to 0.16cm,L equals 17nH,which is not much different from 21nH.This indicates a non-linear relationship.Referring to Figure 3,where the above function is plotted out (dotted lines are for a PC

B trace),we can see that the diameter/width of a wire/trace has to typically increase by a factor of 10for the inductance to halve .The rela-tionship of L to d is therefore logarithmic in nature.The reason for this is the effects of mutual inductance between parallel sections/strips of the conductor.

‘Beefing up’traces to reduce the effects of parasitic induc-tances should be a last resort.Decreasing the length of the trace should be the first step.Increasing the width of certain traces can in fact become counterproductive.In particular,the trace from the switch node to the diode is ‘hot’from an EMI point of view.This is not only because of the AC (high frequency)current it carries,but because of its voltage,which is a switched waveform.Any conductor with a varying voltage,irrespective of the current,becomes an antenna if its dimensions are large enough.Radiated emissions from this antenna can cause undesirable common-mode interfer-ence in its vicinity.Therefore this calls for the area of the copper around the switching node to be reduced,not https://www.wendangku.net/doc/b57875859.html,rge planes of switched voltage also cause ca-pacitive noise coupling into nearby traces.On a typical SMT board,if the opposite side happens to be a ’ground plane’,noise from the switching node can couple through the FR4dielectric of the PCB into the Ground plane.No Ground plane is ’perfect’,and therefore this injected high frequency

noise can also cause the ground plane to not only radiate,but to pass noise onto the IC through ’ground bounce’.Some people suggest that a copper island,exactly the same size/shape as the switching-node island be created on the oppo-site side of the PCB,connected through several vias.This is supposed to prevent ’capacitive cross-talk’to other traces and to enhance thermal dissipation.But this obviously also leads to the breaking-up/partioning of the Ground plane.This defeats the very purpose of Ground plane as it can cause strange effects arising due to the odd current flow patterns in the now divided Ground plane.In general,the Ground plane should be kept continuous/unbroken as far as possible,or it could behave like a slot antenna.For the switching node therefore,the best option is to keep the amount of copper around it to the actual minimum re-quirement.

Some basic physics to be reminded of here:electric fields are caused by electric charge,and magnetic fields by cur-rents.But if an electric field varies with time,it produces a corresponding magnetic field.However magnetic fields are associated with currents.Therefore AC voltages (varying electric fields)on opposite planes of copper on a PCB cause a ’displacement current’(capacitive coupling current)through the FR4dielectric.Similarly,a varying magnetic field causes an electric field.So for example in a transformer,when we pass AC current (varying magnetic field)in a wind-ing,we get Faraday induced voltages (electric field).When-ever voltage or current is switched,an electromagnetic field is generated,which produces EMI.And this EMI is inadvert-ently ’helped’by antenna structures.Therefore,on a PCB layout,the area enclosed by all current loops carrying ’AC (switched)current’must be kept small.Similarly the area of copper planes with ’AC (switched)voltage’must be kept small.Both can behave as antennae.In addition,traces carrying switching currents/voltages must also be kept away from ’quieter’traces to avoid cross-coupling.Further,since ’sharp edges’are known to cause an increase in field strengths,two 45degree bends in a trace are preferred to a single 90degree bend.

COPPER FILLING:WHEN TO STOP

Adding copper lavishly to traces serves some purpose oc-casionally,sometimes none at all,and sometimes it even works against the design in an unintended manner.There may be no simple hard and fast rules here.Judiciousness needs to be applied.But first it is instructive to consider some of the ‘reasons’why copper is lavished,and to the degree it is really required.Most often the requirements are actually much less than predictions based on ’gut instinct’:We will take each of these separately:

a)Current Handling Capability:

If we multiply the width of a trace with its thickness we get the ‘cross sectional area’of the conductor.This determines the resistance (per unit length)of the conductor and the consequent self-heating.This leads to an estimable tem-perature rise.It is important to note that the ‘current handling capability’is therefore not a ‘stake in the ground’as some people think,but is related to a permissible temperature rise.

20042606

FIGURE 3.Inductance of Wire of Length ‘1’AN-1229

https://www.wendangku.net/doc/b57875859.html,

7

COPPER FILLING:WHEN TO STOP

(Continued)

Mil Standards call for maximum 20?C rise,but 30?C–40?C are also common.Figure 4is a chart which helps in the correct estimation.

Commercial PCB’s are often referred to as ‘1oz’or ‘2oz’for example.This refers to the weight of copper in ounces per square foot deposited on the copper clad laminate.1oz is actually equivalent to 1.4mils copper thickness (or 35μm).Similarly 2oz is twice that .We are only considering outer layers (not internal layers)in this Application Note,and therefore at most double-sided (2layer)boards.

Using the thickness of the copper trace we can find the trace width required.For example for 1oz copper board (1.4mils copper thickness),and allowing 20?C rise in temperature,for 4A of current we need 75/1.4=54mils (1.4mm)wide trace.For a 2oz board we need exactly half of that i.e.0.7mm width.

However note that a 1oz double sided board will pass through an electroless copper plating process stage (before solder mask is applied)to create the vias (/PTH:Plated Through Hole),and so it may end up effectively as being considered closer to a 1.4oz copper board.Therefore it is a good idea to check this out with the PCB manufacturer before even starting the layout.Also note that even a single-sided board passes through a hot air solder level finishing stage (after solder mask),where a thin Tin-Lead layer is deposited on the ’unmasked’(no solder mask)copper areas.This does increase the effective thickness of these traces,but doesn’t help as much as copper plating,since Tin-Lead has 10times higher resistivity than copper.

When estimating resistive heating,it is important to know the average current in the traces.For a Buck con-verter,in the AC traces of the input sections (the left hand side of the IC in Figure 1c )the average current is lo *D,where lo is the load current and D the duty cycle.For the AC traces of the output section (the right-hand side),the aver-age current is lo *(1-D).So if the load current is 3A,and the duty cycle (≈Vo/Vin)is say 0.4,then the average current on

the input side is 1.2A only.On the output side it is 1.8A.In neither case is this equal to the load current of 3A!So the trace should be sized correctly and according to such a calculation.

Note that the expected temperature rise stated above is based on ‘self-heating’.But a trace can become very hot simply due to heat from a nearby component.In that case,even a 30?C (additional)rise due to self-heating may be unacceptable.And the ’acceptable’rise also depends on worst-case ambient temperature,and also the rated tem-perature of the board laminate (keep below 120?C for FR4).A quick thumb rule that closely follows the above discussion is:

For moderate temperature rise (less than 30?C)and currents less than 5A

?Use at least 12mils width of copper per amp for 1oz board

?Use at least 7mils width of copper per amp for 2oz board b)Trace Inductance:

We have seen that the preferred method to reduce trace inductance is to reduce length,not increase width.Beyond a certain point,widening of traces does not reduce inductance significantly.Nor does it depend much on whether we use 1oz or 2oz boards.Neither does it depend on whether the trace is unmasked or not (to allow solder/copper to deposit and thereby increase effective conductor thickness).But if for some reason the length cannot be reduced,another way to reduce inductance is by paralleling of forward and return current traces.

Inductances exist because they can store magnetic energy.Therefore conversely,if the magnetic field is somehow cancelled,the inductance too vanishes .By paralleling two current traces,each carrying current of the same mag-nitude but in opposite direction on a PCB,the magnetic field is greatly reduced.These two traces should be parallel and very close.They can be run side-by-side on the same side for a single-sided board.If a double-sided PCB is being used,the most effective solution is to run the traces parallel and on opposite sides of the PCB.The traces can and should be fairly wide in this case to improve their mutual coupling and create the required field cancellation.Note that if a ground plane is used on one side,the return auto-matically ‘images’the forward current trace and pro-duces field cancellation and reduction in inductance .The designer may well ask:what happens to the inductance equation for trace length we presented earlier?---that didn’t seem to indicate that paralleling should help.The problem with the simple trace inductance equation is that it is an approximation.There is simply no such thing as an inde-pendent straight piece of wire carrying current in a given direction ---current must return and so there are only current loops .This follows from basic Physics ---charge cannot accumulate and must return:in this case to the opposite terminal of the emf source responsible for the flow of current.So whenever we talk about the inductance of just a single wire,basically we are talking about a very large loop.Since inductance of a current carrying loop is propor-tional to the area enclosed by the loop,if the loop area is made very small,inductance too is reduced.

Current Density Curve for Outer Layer PCB Copper

Etch

20042607

FIGURE https://www.wendangku.net/doc/b57875859.html,-STD-275E Curves for Current Density

vs.Temperature Rise A N -1229

https://www.wendangku.net/doc/b57875859.html, 8

COPPER FILLING:WHEN TO STOP (Continued)

c)Thermal Management:

Natural convection depends on the amount of surface area that is in contact with the air.If a conductive plate serving as a’heatsink’is thick enough to ensure perfect thermal con-duction into the far recesses of the plate,the temperature rise would have been simply inversely proportional to the total exposed area.PCB copper planes too are in that sense an aid to convection,the difference being that they are not thick enough to ensure perfect conduction.Therefore at some point,we will reach a point of diminshing returns:very large increases in the copper area will produce smaller and smaller improvement in the thermal resistance.This occurs roughly for a square of side1inch on a1oz copper board. Some improvement continues till about3inches,especially for2oz boards and better,but beyond that,external heat-sinks are required.Ultimately,a reasonable practical value attainable for the thermal resistance(from the case of the power device to the ambient)is about30?C/W.

That is not to say that heat is lost only from the copper side. The usual laminate(board material)used for SMT applica-tions is epoxy-glass‘FR4’(also known as GF or G10)which is a fairly good conductor of heat.More commercial and cost-effective applications use cheaper board materials like CEM1,CEM2,CEM3etc.,which are fortunately not much worse as thermal conductors than FR4.So some of the heat from the device side does get to the other side where it contacts the air.Therefore putting a copper plane on the other side(this need not even be electrically the same node,it could be the ground plane)also helps,but only by about10%–20%as compared to a copper plane on only one side.A much greater reduction of thermal resistance by about50%–70%can be produced if‘ther-mal vias’are used to conduct heat to the other side.This thermally‘shunts’or bypasses the board material to get the heat to the other side where there is more exposure to air movement.

The tab of the power packages of the Simple Switcher devices is fortunately at Ground potential,so having large copper planes around the tab will not produce EMI.The tab can be left floating,but if it is used,it must be physically connected directly to the GND pin of the IC as indicated in Figure2.If a double-sided board is used,several small vias can be sunk right next to the IC Ground in positions marked ’X’on to a‘Ground plane’on the other side of the PCB. These vias therefore not only help in the correct electrical implementation of grounding,but also can serve as thermal shunts.They are therefore appropriately called‘thermal vias’.It is recommended that they be small(0.3mm–0.33 mm barrel diameter)so that the hole is essentially filled up during the plating process,thus aiding conduction to the other side.Too large a hole can cause‘solder wick-ing’problems during the reflow soldering process.The pitch(distance between the centers)of several such thermal vias in an area is typically1mm–1.2mm and a grid of thermal vias can be created right under the tab. Since the thermal vias also’steal’heat away from the area during the reflow cycle,occasionally leading to poor solder joints,some recommend that vias(thermal or otherwise) should be close to,but never directly under the tab/legs/pins of any component.

From the point of view of the internal construction of a typical switcher IC,there is no reason to make the trace around the switching node wide since very little heat can come out this

way.As mentioned earlier,this node can act as an antenna

and cause radiation problems.However,there are situations

where a large amount of copper on the switching node may

just be unavoidable.The tab of most power diodes is the

cathode.To sink heat from the diode,a large heatsink or

copper plane must be connected to the tab.Unfortunately for

a conventional positive to positive Buck topology(unlike the

positive to positive Boost or the negative to positive

Buck-Boost)the cathode/tab of the diode corresponds to the

switching node,which is not‘quiet’.Therefore we have a

conflict of interest here between thermal requirements and

EMI.For EMI-sensitive applications,a rather non-typical

diode with the anode internally connected to the tab can be

sought.Or,if an external heatsink is being used,it is recom-

mended that there be electrical(not thermal!)isolation be-

tween the power device and the(grounded)heatsink.Mica

or’Sil-pads’are possible choices here.If the diode must be

SMT,an isolated SMT package may be a good choice.

Overestimating the amount of the copper plane for device

cooling is a common mistake,and can lead to excessive

EMI.The heating in a Buck converter diode is based on

the average current through the diode,not the load

current.Note that a typical Schottky diode has a forward

voltage drop of0.5V.If the load current is5A and the duty

cycle is0.4,the dissipation is only5*0.5*(1–0.4)=1.5W.If

the temperature of the board(the copper area around the

tab)is to be say a maximum of100?C,and the maximum

ambient is55?C,the allowed temperature rise here is

100–55=45?C.For1.5W of estimated dissipation,the re-

quired board(or case)to ambient thermal resistance is

45/1.5=30?C/W.This as we have seen is achievable on a

PCB.To calculate the required area,we can use as a good

approximation an equation derived from empirical equa-

tions for a plate of area‘A’:

A=985x Rth?1.43x P?0.28sq.inches

Here P is in Watts and Rth is the required thermal resistance

in?C/W.Solving for our example

A=985x30?1.43x1.5?0.28sq.inches

A=6.79sq.inches

If this area is square in shape,the length of each side needs

to be6.790.5=2.6inches.If the area called for exceeds1

sq inch,a2oz board should be used.Clearly a2oz board

should be used in the example,as it reduces the thermal

‘constriction’around the power device and allows the large

copper area to be more effectively used for convection.Note

that we are considering only a copper plane exposed to air

on one side of the PCB.Breaking up the Ground plane to

create islands on the other side to connect to was not

considered a good option as it leads to odd return current

patterns.

THE GROUND PLANE

With double-sided boards,it is a common practice to almost

completely fill one side with ground.There are people who

usually rightly so consider this a panacea or‘silver bullet’for

most problems.As we have seen,every signal has a return,

and as its harmonics get higher,the return‘wants’to be

directly under the signal path,thus leading to field cancella-

tion,and reduction of inductance.It also helps thermal man-

agement as it couples some of the heat produced by power

devices on one side of the board to the other side.The

Ground plane also capacitively links to noisy traces above it,

causing some’softening’of transients and thereby some

reduction in noise/EMI---unless the cross-coupling is so

severe as to start causing the Ground plane itself to

AN-1229

https://www.wendangku.net/doc/b57875859.html,

9

THE GROUND PLANE

(Continued)

radiate.Vias can be sunk under the ground terminal of all power components in to the Ground plane,and this reduces DC resistance offset errors on the output voltage too for example.As mentioned,in Figure 2,‘X’marks have been placed to indicate that if there is a double sided board in use,and a Ground plane is present,then vias can be added at these points.They are optional,and so if a low cost single-sided board is preferred,they can be omitted.But if these vias are also doubling over as ‘thermal vias’for the switcher IC,as when they are under the tab of an SMT power device,they should be sized appropriately as previ-ously discussed.

However,a Ground plane should be an ‘add-on’to the recommendations in Figure 2.It does not substitute the correct placement of the two critical components .Much effort should go into not breaking or partitioning this plane.Further,in general,if too much switching power flow occurs through such a plane,it can create ’ground bounce’and cause controller upsets.Therefore in higher power applica-tions,with the added luxury of multi-layer PCBs,separate signal and power ground planes are used.But for the lower power SIMPLE SWITCHER family,a single Ground plane is all that may be required.And if the layout is carried out conscientiously ,keeping all the recommendations in mind,even a single-sided board should suffice.

SIGNAL TRACES:FEEDBACK

The only critical signal trace is the feedback trace.First consider only the Adjustable versions of the Simple Switch-ers.One end of the trace connects to a low impedance node,which is the output rail or a resistive divider at the output.The other end connects to the feedback pin,which is the high impedance input of the error amplifier.If this trace picks up noise (capacitively or inductively)as it passes between these two nodes,it can lead to erroneous output voltages,and in extreme cases even instability or device failure.There seem to be just two options for this

1.Keep the feedback trace short if possible so as to mini-mize pickup AND/OR

2.

Keep it away from noise sources (e.g.switching diode,inductor)

Keeping the trace short may not be feasible.In fact the feedback trace may be deliberately kept slightly longer so as to route it away from potential noise sources.It should not pass under the inductor or diode in particu-lar.If a double-sided SMT board is being used,a good strategy is as follows:

?use a via at the output resistive divider to bring the trace to the other side

?run the trace to cut through the surrounding ground plane areas,taking care not to pass it under the inductor/diode and not parallel to any power trace on either side of the board (though it can cross them perpendicularly)

?and then very close to the IC,use another via to bring out the trace to the component side where it connects to the feedback pin of the IC Refer to Figure 5a which shows the situation for the Adjust-able part.The trace which picks up noise is bold.However,if we consider a fixed voltage part,we learn an important thing.This is Figure 5b .Note that the feedback trace here is not marked bold.The reason is that a trace can pick up noise only if at least one end of it is a high impedance node .In Figure 5b ,the feedback pin goes to a resistive divider rather than directly to the input of the error amplifier.So it is relatively immune to noise pickup.The only section where noise can be picked up is inside the IC (shown bold),and this is a very short path.Applying the same principle to an Adjustable part provides another interesting way to route the feedback trace.One way is shown in Figure 5c .Here the length of the ‘feedback trace’is very short,so it is relatively noise-free.The feedback resistors are physically close to the IC and the trace from the output to the upper resistor has low impedances on either side,and so does not pick up noise.However,the connection of the lower resistor to ground is not ideal as the resistive drop across the section marked ‘lo *R’will affect the output voltage load regulation slightly.Another way is in Figure 5d,and this resolves both issues.This is therefore recommended.If a ground plane is used however,both Figure 5c and Figure 5d are actually the same if vias are correctly placed to couple into this plane.For Figure 5d ,if possible,it is a good idea to run the top and bottom traces to the resistive divider parallel and close to each other,so as to minimize any further chance of noise pickup.

A N -1229

https://www.wendangku.net/doc/b57875859.html, 10

AN-1229 SIGNAL TRACES:FEEDBACK(Continued)

20042608

FIGURE5.Feedback Traces(bold lines susceptible to noise)

https://www.wendangku.net/doc/b57875859.html,

11

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.

2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.

National Semiconductor Corporation Americas

Email:support@https://www.wendangku.net/doc/b57875859.html,

National Semiconductor Europe

Fax:+49(0)180-5308586Email:europe.support@https://www.wendangku.net/doc/b57875859.html,

Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Fran?ais Tel:+33(0)141918790

National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466

Email:ap.support@https://www.wendangku.net/doc/b57875859.html,

National Semiconductor Japan Ltd.

Tel:81-3-5639-7560Fax:81-3-5639-7507

https://www.wendangku.net/doc/b57875859.html,

A N -1229

S I M P L E S W I T C H E R P C B L a y o u t G u i d e l i n e s

National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

开关电源PCB设计流程及布线技巧

开关电源PCB设计流程及布线技巧在任何开关电源设计中，PCB板的物理设计都是最后一个环节，如果设计方法不当，PCB可能会辐射过多的电磁干扰，造成电源工作不稳定，以下针对各个步骤中所需注意的事项进行分析： 一、从原理图到PCB的设计流程 建立元件参数－》输入原理网表-》设计参数设置-》手工布局-》手工布线-》验证设计－》复查-》cam输出。 二、参数设置 相邻导线间距必须能满足电气安全要求，而且为了便于操作和生产，间距也应尽量宽些。最小间距至少要能适合承受的电压，在布线密度较低时，信号线的间距可适当地加大，对高、低电平悬殊的信号线应尽可能地短且加大间距，一般情况下将走线间距设为8mil。焊盘内孔边缘到印制板边的距离要大于1mm，这样可以避免加工时导致焊盘缺损。当与焊盘连接的走线较细时，要将焊盘与走线之间的连接设计成水滴状，这样的好处是焊盘不容易起皮，而是走线与焊盘不易断开。 如图：

三、元器件布局 实践证明，即使电路原理图设计正确，印制电路板设计不当，也会对电子设备的可靠性产生不利影响。例如，如果印制板两条细平行线靠得很近，则会形成信号波形的延迟，在传输线的终端形成反射噪声；由于电源、地线的考虑不周到而引起的干扰，会使产品的性能下降，因此，在设计印制电路板的时候，应注意采用正确的方法。每一个开关电源都有四个电流回路： （1）电源开关交流回路 （2）输出整流交流回路 （3）输入信号源电流回路 （4）输出负载电流回路输入回路 通过一个近似直流的电流对输入电容充电，滤波电容主要起到一个宽带储能作用；类似地，输出滤波电容也用来储存来自输出整流器的高频能量，同时消除输出负载回路的直流能量。所以，输入和输出滤波电容的接线端十分重要，输入及输出电流回路应分别只从滤波电容的接线端连接到电源；如果在输入/输出回

上海工业产业导向及布局指南.

上海工业产业导向及布局指南 根据国家发展计划委员会、国家经济贸易委员会、国家对外经济贸易合作部近年来发布的《"十五"工业结构调整规划》、《高新技术产业化目录》、《高新技术出口目录》、《淘汰落后生产能力、工艺和产品的目录》、《当前工商领域禁止投资目录》、《外商投资产业指导目录》等指导性文件，结合《上海工业"十五"发展计划》，在广泛听取各方面意见的基础上，会同有关部门、工业集团、行业协会，并组织有关专家进行了深入研究，编制本《上海工业产业导向及布局指南》（以下简称"指南"），以进一步明确上海工业发展与调整的重点领域、行业和产品门类，为全社会企业在上海从事工业投资发展和重点地区实施工业布局调整提供导向性意见。在产业发展方面，"十五"期间，上海将初步建立起以高科技工业为主导、基础原材料工业为依托、现代装备工业为骨干、都市型工业为配套的工业结构新体系，重点鼓励发展电子信息、汽车、电站设备及大型机电产品、石油化工与精细化工、精品钢材、生物医药等六大支柱工业，同时确定限期淘汰、总量控制、市场淘汰、安全防范等四类重点行业、产品，加快调整步伐。在产业布局方面，以"盘活存量，用好增量，优化布局，增强辐射"为原则，加快建设信息产业、汽车城、化学工业区、精品钢材等四大产业基地，进一步完善"三环分布"的工业总体格局：即以市中心为轴心，内环线、外环线为布局界线，内环线以内以都市型工业为主，内外环线之间以都市型工业、高科技工业及配套产业为主，外环线以外以装备类工业和基础原材料工业为主。加强产业布局导向，鼓励新增和搬迁改造工业项目按照产业类别和技术层次向"1+3+9"市级工业区集中，鼓励同类产业及相关配套产业集聚发展，结合各区县"一业特强，多业发展"和"一城九镇" 建设的产业导向，形成各具特色的工业区发展新格局。 本指南由鼓励发展类、禁止类、限止类和工业布局四大部分内容组成，编制的基本原则是：（1）符合国家产业政策的要求；（2）符合上海城市总体功能定位的要求；（3）符合建设上海工业新高地的要求；（4）有利于提高上海工业综合竞争力，加快产业升级要求。 本指南是市经委转变政府职能，加强产业宏观导向的尝试，在首次编制中难免会有不少疏漏和不确切、不合理之处，也热忱欢迎社会各界对此多提宝贵意见和建议，以帮助我们进一步做好修改完善。 电子信息产品制造业 通信及网络设备 1．光通信有源器件及模块、无源器件及模块 2．宽带数字同步系列光纤通信系统设备 3．光纤、光纤预制棒 4．数字交叉连接设备 5. GSM、CDMA基站、终端、交换设备及第三代数字移动通信产品 6．WAP（无线网络）产品 7．数字集群通信系统设备 8．高速无线寻呼系统设备 9．移动智能网络设备 10．VSAT卫星通信系统、卫星移动通信系统及地面站设备 11．宽带数字同步系列微波通信系统设备 12．高速宽带数字程控交换机

反激式开关电源PCB设计要点

反激式开关电源PCB设计要点 反激电源整体原理图如图1所示。 图1开关电源从市电火线L和零线N进来后，有一个电流较大的保险管，如图1所示。这是因为板子上有其他市电交流负载，如交流电机等，当负载电流过大时，保护电路。该保险管电流参数需要根据实际负载功率计算选择。保险管后有一个压敏电阻（如图2所示），用于抑制浪涌和瞬时尖峰电压，当其两端电压高于其阈值时，压敏电阻值迅速下降，从而流过大电流，保护后级电路。在压敏电阻后又有一个电流较小的保险管（如图2所示），这才是真正针对板子开关电源的过流保护，防止电源电流过大，保护电路。保险管后的NTC电阻（如图2所示），用于抑制开机时的浪涌电流，因为刚开机时，NTC温度较低，电阻值很大，抑制电流过大；当在电流作用下，NTC电阻温度升高，电阻值下降到很小，不影响正常工作电流。安规X电容(如图2所示）用于滤除市电的差模干扰，其后的3个电阻主要用于给X电容放电，以符合安规要求，防止在切断市电输入时，人手触摸到金属

端子有触电感。使用多个电阻的原因是分散承受电压和功率。共模电感（如图2所示）用于滤除共模干扰电流。 图2输入电容EC1在行业上有个3uF/W的通用原则，但需要注意的是该功率是输入功率而非输出功率，假设输出功率12W，效率为80%，则输入功率为15W，则输入电容至少为45uF，如图8所示。由于反激电源演变自Buck-Boost，其输入回路和输出回路均是电流不连续路径，因此均要控制回路面积越小越好。输入电容EC1要靠近电源芯片，如图3所示。同理，输出整流二极管和输出电容也应该靠近变压器。

图3RCD钳位电路用于吸收开关管关断时的Vds高压，防止损坏MOS 管（电源芯片）。Layout时需将电容靠近变压器，电阻次之，如图4所示。

车架设计指南

奇瑞汽车有限公司底盘部设计指南 编制： 审核： 批准：

1、架的主要功能： 车架是整个汽车的基体，汽车上绝大多数部件和总成都是通过车架来固定其位置的。如：发动机、传动系统、悬架、转向、驾驶室、货箱和有关操纵机构。车架的功用是支撑连接汽车的各零部件，并承受来自车内外的各种载荷。 2、车架的类型： 主要类型 目前，汽车车架的结构形式基本上有三种：边梁式车架、中梁式车架（或称脊骨式车架）和综合式车架。其中以边梁式车架应用最广。 边梁式车架由两根位于两边的纵梁和若干根横梁组成，用铆接法或焊接法将纵梁与横梁连接成坚固的刚性构架。通常用低合金钢板冲压而成，断面形状一般为槽形，也有的做成Z字形或箱形断面。其结构特点是便于安装驾驶室、车厢及一些特种装备和布置其它总成，有利于改装变型车和发展多品种汽车。被广泛采用在载货汽车和大多数的特种汽车上。近代轿车为了保证良好的整车性能，尽量降低中心和有利于前后悬架的布置，把结构需要放在第一位，兼顾车架加工工艺性，所以车架形状设计的比较复杂而实用。 中梁式车架只有一根位于中央贯穿前后的纵梁，因此亦称为脊骨式车架，中梁的断面可以做成管型或箱型。这种结构的车架有较大的扭转刚度。使车轮有较大的运动空间，便于布置等优点因此被采用在某些轿车和货车上。 综合式车架比较复杂，应用比较广，一般轿车上使用。 车架的几种结构 车架主要有以下结构形式： 1．箱横梁和发动机支撑梁 横梁总成支撑发动机、水箱、保证车身的扭转刚度 发动机支撑梁和水箱横梁均有钢板冲压焊接而成，发动机支撑梁为封闭断面。 发动机支撑梁与车身连接处通常装有橡胶缓冲块。

材料：支撑梁上下体材料常采用为SAPH440其它BH340 表面处理为电泳。 2．车架 副车架带控制臂总成承受前轴载荷、支撑车身、动力总成、转向机、前悬挂、制动器等 副车架、控制臂均为钢板冲压焊接而成为封闭断面。 控制臂与副车架连接处采用橡胶衬套，起到改善行驶性能和舒适性。 材料：副车架上下体材料为常采用SAPH370（370为抗拉强度）其它为SPHE、SPHC，表面处理为电泳 3、纵梁 发动机纵梁总成支撑动力总成 1、动机纵梁总成均由钢板冲压焊接而成，为封闭断面。

开关电源课程设计

太原理工大学课程设计任务书 指导教师签名：日期：

前言 随着电力电子技术的发展，开关电源的应用越来越广泛。反激式开关电源以其设计简单，体积小巧等优势，广泛应用于小功率场合。开关电源以其小型、轻量和高效率的特点，被广泛地应用于各种电气设备和系统中，其性能的优劣直接关系到整个系统功能的实现。开关稳压电源有多种类型，其中单端反激式开关电源由于具有线路简单，所需要的元器件少，能够提供多路隔离输出等优点而广泛应用于小功率电源领域。 本论文根据输入电压经EMI滤波设计整流桥，再与直流变压器开关管构成反激电路。通过输出反馈经UC3842控制占空比，从而使输出电压稳定。反激电路中开关管开通原边线圈储存能量，副边不导通。原边关断时，线圈储存的能量通过互感向负载提供能量。输出电压反馈由TL431和光耦构成，当输出稳定时，有一个稳定的电流；当输出电压增大时，TL431分流增加，发光二极管亮度改变，使三级管电流改变，致使开关管控制导通占空比改变，从而使输出电压减小。另外，芯片UC3842引脚接一电流反馈，通过控制分压值实现截流保护，防止输出过电流。 设计中，直流变压器的设计是重点，需要计算其原边电感，原副边匝数，铁芯的选择，根据这些参数构造电路图，计算各电容电阻值及二极管承受的反压，选择合适的型号。 论文先介绍了开关电源及反激式开关电源，然后介绍器件选型，再分部分介绍主电路、控制电路和保护电路，最后附表为选择时参数参考表和总电路图。

目录 前言 第一章开关电源概述 (1) 1.1开关电源综述 (1) 1.2反激式开关电源介绍 (2) 第二章总体方案的确定 (2) 2.1总体设计思路及框图 (2) 2.2仿真原理图 (3) 第三章具体电路设计 (5) 3.1EMI滤波电路 (5) 3.2整流滤波电路设计 (6) 3.3高频变压器的设计 (7) 3.4控制反馈电路的设计 (15) 3.5保护电路的设计 (17) 3.6输出侧滤波电路设计 (18) 第四章电路仿真与结果 (19) 4.1 EMI滤波电路 (19) 4.2整流电路 (21) 4.3反激型电路 (22) 4.4反馈电路 (23) 4.5总电路 (24) 心得体会 (25) 参考文献 (26)

汽车总布置设计说明书

目录 目录 ................................................................ I 摘要 .............................................................. I II 第1章、汽车形式的选择 . (1) 1.1汽车质量参数的确定 (1) 1.1.1汽车载客量和装载质量 ................................... 1 1.1.2质量系数ηmo ............................................ 1 1.1.3整车整备质量m o ......................................... 1 1.1.4汽车总质量m a ........................................... 1 1.2汽车轮胎的选择 ............................................... 2 1.3驱动形式的选择 ............................................... 2 1.4轴数的选择 ................................................... 3 1.5货车布置形式 ................................................. 3 第2章.汽车发动机的选择 (4) 2.1发动机最大功率 max e P (4) 2.2选择发动机 ................................................... 4 第3章、汽车主要参数选择 .. (7) 3.1汽车主要尺寸的确定 (7) 3.1.1外廓尺寸 ............................................... 7 3.1.2轴距L .................................................. 7 3.1.3前轮距B 1和后轮距B 2 ..................................... 7 3.1.4前悬L F 和后悬L R ......................................... 8 3.1.5货车车头长度 ........................................... 8 3.1.6货车车箱尺寸 ........................................... 8 3.2轴荷分配及质心位置的计算 ..................................... 8 第4章.传动比的计算和选 .. (13) 4.1驱动桥主减速器传动比0i 的选择 (13) 4.2变速器传动比 g i 的选择 (14) 4.2.1变速器头档传动比 1 g i 的选择 (14) 4.2.2变速器的选择 .......................................... 14 第5章.动力性能计算 (15) 5.1驱动平衡计算 (15) 5.1.1驱动力计算 ............................................ 15 5.1.2行驶阻力计算 .......................................... 15 5.1.3力的平衡方程 .......................................... 17 5.2动力特性计算 (17) 5.2.1动力因数D 的计算 (17)

开关电源的PCB布局走线

首先从开关电源的设计及生产工艺开始描述吧，先说说印制板的设计。开关电源工作在高频率,高脉冲状态，属于模拟电路中的一个比较特殊种类。布板时须遵循高频电路布线原则。 1、布局:脉冲电压连线尽可能短,其中输入开关管到变压器连线，输出变压器到整流管连接线。脉冲电流环路尽可能小如输入滤波电容正到变压器到开关管返回电容负。输出部分变压器出端到整流管到输出电感到输出电容返回变 压器电路中X电容要尽量接近开关电源输入端,输入线应避 免与其他电路平行，应避开。 Y电容应放置在机壳接地端子或FG连接端。共摸电感应与变压器保持一定距离，以避免 磁偶合。如不好处理可在共摸电感与变压器间加一屏蔽，以上几项对开关电源的EMC性能影响较大。 输出电容一般可采用两只一只靠近整流管另一只应 靠近输出端子,可影响电源输出纹波指标，两只小容量电容 并联效果应优于用一只大容量电容。发热器件要和电解电容保持一定距离，以延长整机寿命，电解电容是开关电源寿命的瓶劲,如变压器、功率管、大功率电阻要和电解保持距离，电解之间也须留出散热空间,条件允许可将其放置在进风口控制部分要注意:高阻抗弱信号电路连线要尽量短 如取样反馈环路，在处理时要尽量避免其受干扰、电流取样

信号电路，特别是电流控制型电路，处理不好易出现一些想不到的意外，其中有一些技巧 现以3８43电路举例见图（1）图一效果要好于图二，图二在满载时用示波器观测电流波形上明显叠加尖刺，由于干扰限流点比设计值偏低，图一则没有这种现象、还有开关管驱动信号电路，开关管驱动电阻要靠近开关管,可提高开关管工作可靠性，这和功率 MＯＳFET高直流阻抗电压驱动特性有关。 下面谈一谈印制板布线的一些原则。 线间距：随着印制线路板制造工艺的不断完善和提高,一般加工厂制造出线间距等于甚至小于0．１mｍ已经不存在什么问题,完全能够满足大多数应用场合。考虑到开关电源所采用的元器件及生产工艺，一般双面板最小线间距设

QFN封装的组装和PCB布局指南

QFN封装的组装和PCB布局指南 前言 双排或多排QFN封装是近似于芯片级塑封的封装，其基板上有铜引线框架。底部上面裸露的芯片粘附焊盘会有效地将热量传递给PCB，并且通过下面的键合提供稳定的接地或通过导电芯片粘附材料形成电气连接。双排或多排QFN封装的设计实现了柔性，并提高了在极高速操作频率下的电气性能。 双排或多排QFN封装采用有间隙的引线设计，这种设计可形成交错排列的引线布局。内排交错0.5mm，就会使最大尺寸芯片实现紧凑致密的设计，同时，不会超过通常的0.5mm间距的SMT工艺的表面组装技术（SMT）的能力。 Actel公司提供的QFN封装有三种结构：QN180、QN132和QN108。这些封装的印脚和外形是按照JEDEC MO-247标准：塑料四方无引线交叉排列的多排封装（增热任选）和按照JEDEC Design Guide 4.19：四方形无引线交叉排列的多排封装而实施的。 QFN封装概述 图1和图2所示是通过同一平面上的芯片和线焊焊盘使这种封装的高度达到最小化。图3说明了这种焊盘的结构。在组装时，引线直接与板子连接，而不像塑料四方（PQ）或薄形四方（TQ）那样，在引线封装内留有一定间隙的高度以便分离。此外，由于芯片焊盘直接与PCB连接，使得QFN封装具有极好的散热性。由于QFN封装的有效和致密的设计，还会降低电子寄生效应。 表1所列是典型的可靠性数据。 表1 可靠性

为了达到峰值性能，母板的设计必须合适，且对于封装的组装必须给予特别的构思。就提高的温度、电气和板级性能而言，必须使用与板上热焊盘相对应的焊盘将封装上裸露的焊盘焊接到板上。为了使板子能够实现有效的导热，PCB的热焊盘区域必须设置有导热通孔。对内部一排引线和热焊盘之间的容差是有要求的，以便通过导通孔来布设内排信号的线路。对容差量的要求取决于具体应用。在设计PCB印脚时必须考虑到这一点，由于封装、PCB和板组装诸多方面的关联性，必须考虑到尺寸容差。 明显影响QFN封装在板上的组装和焊点质量的一些因素列在下面： ?覆盖于热焊盘区域的焊膏量； ?热焊盘周边和热焊盘区域的模板设计； ?导通孔的类型； ?板厚度； ?封装上的引线涂层； ?板上的表面涂层； ?焊膏类型； ?再流曲线。 这种应用提示：为开发适当的板设计和表面组装工艺提供了通用指南。为了满足一些特别用户的表面组装实践和应用要求而优化工艺，需要进一步地进行潜心研发。 PCB焊盘设计指南 这部分主要论述对于推荐的焊盘图形的逻辑依据在封装级和板级布局中的局限性。

整车布置设计规范(修改稿)

整车总布置设计规范 1.范围 本标准规定了整车总布置设计的原则、规定及应满足的有关法规等。 本标准适用于公司新产品开发时的整车总布置设计。 2.引用文件 下列文件中的条款通过本标准的引用而成为本标准的条款。凡是注日期的引用文件，其随后所有的修改单（不包括勘误的内容）或修订版均不适用本标准，然而，鼓励根据本标准达成协议的各方研究是否可使用这些文件的最新版本。凡是不注日期的引用文件，其最新版本适用于本标准。 QC/T490-2000：主图板 QC/T576-1999：轿车尺寸标注编码 GB/T17867-1999：轿车手操纵件、指示器及信号装置的位置 GB14167-1993：安全带固定点 GB11556－1994 ：A、区 GB11565-1989：B区 GB11562-1994：前方视野 GB/T13053-1991：脚踏板 SAEJ 1100：头部空间、上下左方便性 3术语和定义 下列术语和定义适用于本标准。 3.1整车总布置 明示所有总成的硬点、关键的参数的布置图 3.2设计硬点 轮距、轴距、总长、总宽、造型风格、油泥模型表面或造型面、人体模型尺寸、人机工程校核的控制要求、底盘等与车身相关零部件对车身的控制点线面及控制结构，都称为设计硬点。 4.整车总布置图上应确定的参数 4.1整车的外廓尺寸； 4.2轴距和前、后轮距； 4.3前悬和后悬长度；

4.4发动机、前轮的布置关系； 4.5轮胎型号、静力半径和滚动半径、负载能力； 4.6车箱内长及外廓尺寸； 4.7前轮接地点至前簧座的距离； 4.8前簧中心距； 4.9后簧中心距； 4.10车架前部和后部外宽； 4.11车架纵梁外形尺寸及横梁位置； 4.12前簧作用长度； 4.13后簧作用长度； 5.参数确定原则及设计的一般程序 5.1参数确定原则 以设计任务书和标杆样车为基准，按设计任务书上规定的或标杆样车上测定的参数进行总布置，如确实不能满足的，需提出经上级领导批准后方能更改。 5.2设计的一般程序 1）总布置设计人员在接到新车型的开发任务后，首先要进行整车构思，并参与市场调研和样车分析，在此基础上制定出总的设计原则和明确设计目标； 2）各专业所建立标杆样车的3D数模，并提供给整车布置人员； 3）总布置设计人员将各专业所提供的数模装配好； 4）对各总成的匹配和布置关系等进行分析，明确它们的优点和不足； 5）各专业所建立拟采用的总成的数模，不提供总布置人员； 6）总布置人员对新的数模进行分析，并提出可行性的建议； 7）对方案进行评审； 8）评审后对各总成进行修改或开发； 6.主要尺寸参数的确定

开关电源的PCB布线要求

开关电源的PCB布线设计 开关电源PCB排版是开发电源产品中的一个重要过程。许多情况下，一个在纸上设计得非常完美的电源可能在初次调试时无法正常工作，原因是该电源的PCB排版存在着许多问题． 0、引言 为了适应电子产品飞快的更新换代节奏，产品设计工程师更倾向于选择在市场上很容易采购到的AC／DC适配器，并把多组直流电源直接安装在系统的线路板上。由于开关电源产生的电磁干扰会影响到其电子产品的正常工作，正确的电源PCB排版就变得非常重要。开关电源PCB排版与数字电路PCB排版完全不一样。在数字电路排版中，许多数字芯片可以通过PCB软件来自动排列，且芯片之间的连接线可以通过PCB软件来自动连接。用自动排版方式排出的开关电源肯定无法正常工作。所以，没计人员需要对开关电源PCB排版基本规则和开关电源工作原理有一定的了解。 1、开关电源PCB排版基本要点 1.1 电容高频滤波特性 图1是电容器基本结构和高频等效模型。 电容的基本公式是 式(1)显示，减小电容器极板之间的距离(d)和增加极板的截面积(A)将增加电容器的电容量。 电容通常存在等效串联电阻(ESR)和等效串联电感(ESL)二个寄生参数。图2是电容器在不同工作频率下的阻抗(Zc)。

一个电容器的谐振频率(fo)可以从它自身电容量(C)和等效串联电感量(LESL)得到，即 当一个电容器工作频率在fo以下时，其阻抗随频率的上升而减小，即 当电容器工作频率在fo以上时，其阻抗会随频率的上升而增加，即 当电容器工作频率接近fo时，电容阻抗就等于它的等效串联电阻(RESR)。 电解电容器一般都有很大的电容量和很大的等效串联电感。由于它的谐振频率很低，所以只能使用在低频滤波上。钽电容器一般都有较大电容量和较小等效串联电感，因而它的谐振频率会高于电解电容器，并能使用在中高频滤波上。瓷片电容器电容量和等效串联电感一般都很小，因而它的谐振频率远高于电解电容器和钽电容器，所以能使用在高频滤波和旁路电路上。由于小电容量瓷片电容器的谐振频率会比大电容量瓷片电容器的谐振频率要高，因此，在选择旁路电容时不能光选用电容值过高的瓷片电容器。为了改善电容的高频特性，多个不同特性的电容器可以并联起来使用。图3是多个不同特性的电容器并联后阻抗改善的效果。

教室设计与布局指南

现代化教室设计与布局指南 在学习方面，许多老师都关心自己的教学方法，父母的支持和差异化教学。但是，教室设计是支撑教师效能的基础。班级布置方式可能会影响学生的学习水平。 教室布置不仅是重新布置椅子的问题，而且是有目的地重新布置教室以达到预期效果的问题。老师如何重新布置教室应该取决于他们的个人理念，他们希望实现的目标以及研究中发现的一些最佳实践。但是，重要的是要基本了解哪些因素会影响教室的布局。 教室布置的基础 《教师杂志》一文指出，教室的布局方式对学业成绩有影响。研究似乎表明，班级安排对学生学习的影响占16％。布置教室时，教师需要考虑许多环境因素，包括照明，温度甚至空气质量以及教室使用的颜色。对于许多教师而言，仅考虑这些因素中的每一个都是不切实际的。但是，要吸取的教训是，教室的设计对于最大程度地提高学生的学业成绩至关重要。 另一项研究表明，根据班级的设计，教室的布局可能对学习产生积极或消极的25％的影响。通过适当的教室布局，可以提高注意力，改善行为，并且老师可以更有效地支持学习成果。与以前的研究非常相似，研究人员指出了可能影响学术成果的几个因素。教室的布置可

能会影响音响效果，因此，严重偏爱讲座形式的老师可能想布置课桌，以使所有学生都能清楚地听到老师的声音。 个性化是课堂设计的一个有趣因素。指设计一个教室，使学生和老师感到自己拥有周围的空间。这可以通过使用可以重新配置的器具来实现，即使只是在有限的程度上，也可以使学生重新布置他们的工作环境。如果教师经常重新布置教室以在讲座和小组作业之间切换，这也将很有帮助。 他们为教室选择的装饰的性质通常超出了教师的控制能力，但学校管理人员可能要考虑的一个因素。学生在学习时所经历的舒适程度可能使他们更容易学习。柔软，色彩柔和，质地舒适的桌凳实际上可以改善学生的心情。因此，在为学校购买用具时，应注意教室使用的用具种类。 当然，老师确实可以控制班级中的家具摆设。尽管他们可能无法为学生购买三十把新椅子，但他们可以挂上不同的装饰，其中包括柔和的色彩以帮助改善学习环境。这只是他们如何使用独特的装饰来改善环境的自定义环境的一个示例。 课堂布局背后的哲学 乔厄普（Jo Earp）指出，教室的布局应反映教师自己的教育理念。如果他们非常注重群体学习，则应按照便于群体学习的方式布置课程。课桌的布置应使学生能够轻松地相互交流并合作完成小组任务。讲课

车架设计指南

上汽集团奇瑞汽车有限公司 奇瑞汽车有限公司 底盘部设计指南 编制： 审核： 批准：

上汽集团奇瑞汽车有限公司 1、架的主要功能： 车架是整个汽车的基体，汽车上绝大多数部件和总成都是通过车架来固定其位置的。如：发动机、传动系统、悬架、转向、驾驶室、货箱和有关操纵机构。车架的功用是支撑连接汽车的各零部件，并承受来自车内外的各种载荷。 2、车架的类型： 2.1 主要类型 目前，汽车车架的结构形式基本上有三种：边梁式车架、中梁式车架（或称脊骨式车架）和综合式车架。其中以边梁式车架应用最广。 边梁式车架由两根位于两边的纵梁和若干根横梁组成，用铆接法或焊接法将纵梁与横梁连接成坚固的刚性构架。通常用低合金钢板冲压而成，断面形状一般为槽形，也有的做成Z字形或箱形断面。其结构特点是便于安装驾驶室、车厢及一些特种装备和布置其它总成，有利于改装变型车和发展多品种汽车。被广泛采用在载货汽车和大多数的特种汽车上。近代轿车为了保证良好的整车性能，尽量降低中心和有利于前后悬架的布置，把结构需要放在第一位，兼顾车架加工工艺性，所以车架形状设计的比较复杂而实用。 中梁式车架只有一根位于中央贯穿前后的纵梁，因此亦称为脊骨式车架，中梁的断面可以做成管型或箱型。这种结构的车架有较大的扭转刚度。使车轮有较大的运动空间，便于布置等优点因此被采用在某些轿车和货车上。 综合式车架比较复杂，应用比较广，一般轿车上使用。 2.2车架的几种结构 车架主要有以下结构形式： 1．箱横梁和发动机支撑梁 横梁总成支撑发动机、水箱、保证车身的扭转刚度 发动机支撑梁和水箱横梁均有钢板冲压焊接而成，发动机支撑梁为封闭断面。 发动机支撑梁与车身连接处通常装有橡胶缓冲块。 材料：支撑梁上下体材料常采用为SAPH440其它BH340 表面处理为电泳。

开关电源EMI设计-电源PCB设计要点

开关电源EMI设计-电源PCB设计要点 摘要：由于开关电源的开关特性，容易使得开关电源产生极大的电磁兼容方面的干扰，作为一个电磁兼容工程师，或则一个PCB layout 工程师必须了解电磁兼容问题的原因已经解决措施，特别是layout 工程师，需要了解如何避免脏点的扩大，本文主要介绍了电源PCB 设计的要点。 1，几个基本原理：任何导线都是有阻抗的；电流总是自动选择阻抗最小的路径；辐射强度和电流、频率、回路面积有关；共模干扰和大dv/dt 信号对地互容有关；降低EMI 和增强抗干扰能力的原理是相似的。 2，布局要按电源、模拟、高速数字及各功能块进行分区。 3，尽量减小大di/dt 回路面积，减小大dv/dt 信号线长度（或面积，宽度也不宜太宽，走线面积增大使分布电容增大，一般的做法是：走线的宽度尽量大，但要去掉多余的部分），并尽量走直线，降低其隐含包围区域，以减小辐射。 4，感性串扰主要由大di/dt 环路（环形天线），感应强度和互感成正比，所以减小和这些信号的互感（主要途径是减小环路面积、增大距离）比较关键；容性串扰主要由大dv/dt 信号产生，感应强度和互容成正比，所有减小和这些信号的互容（主要途径是减小耦合有效面积、增大距离，互容随距离的增大降低较快）比较关键。 5，尽量利用环路对消的原则来布线，进一步降低大di/dt 回路的面积，如图1 所示（类似双绞线利用环路对消原理提高抗干扰能力，增大传输距离）：

图1 ，环路对消（boost 电路的续流环） 6，降低环路面积不仅降低了辐射，同时还降低了环路电感，使电路性能更佳。 7，降低环路面积要求我们精确设计各走线的回流路径。 8，当多个PCB 通过接插件进行连接时，也需要考虑使环路面积达到最小，尤其是大di/dt 信号、高频信号或敏感信号。最好一个信号线对应一条地线，两条线尽量靠近，必要时可以用双绞线进行连接（双绞线每一圈的长度对应于噪声半波长的整数倍）。如果大家打开电脑机箱，就可以看到主板到前面板USB 接口就是用双绞线进行连接，可见双绞线连接对于抗干扰和降低辐射的重要性。 9，对于数据排线，尽量在排线中多安排一些地线，并使这些地线均匀分布在排线中，这样可以有效降低环路面积。 10，有些板间连接线虽然是低频信号，但由于这些低频信号中含有大量的高频噪声（通过传导和辐射），如果没有处理好，也很容易将这些噪声辐射出去。 11，布线时首先考虑大电流走线和容易产生辐射的走线。 12，开关电源通常有4 个电流环：输入、输出、开关、续流，（如图2 ）。其中输入、输出两个电流环几乎为直流，几乎不产生emi ，但容易受干扰；开关、续流两个电流环有较大的di/dt ，需要注意。如果输入、输出两个电容用多

开关电源PCB布局指南AN-1229中文版

SIMPLE Array SWITCHER ? PCB ? AN-1229? 2002 National Semiconductor Corporation AN200426 https://www.wendangku.net/doc/b57875859.html,

https://www.wendangku.net/doc/b57875859.html, 2 A N -1229 ? ? 20042601 1. 1a ? ? ? ? ? ? ? ? CBYPASS ? ? CIN ? ? ?? ? 1b ? ? ? ? ? ? ? ? ? ? 1c ? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ?? PCB ? ? ? ? ? ? ? ? ? ? ? ? PWM ? ? ? ?? ?? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? , ? ? ? ? ???

AN-1229 https://www.wendangku.net/doc/b57875859.html, 3 ? ? ǖ ? ? ? ? ? ? ? ? ? ? ? ? ? ?ǖ ? ? ?? ? ǜ ? ? V ǚIR ? ? ? ?? ? ? ? 1.4 0.5 1 ? 20 ?? 1 ? 1A ? 2.5 ? ? ?? IC ? ? ? ? PCB ? ? ? ? ? 20 ?? ? ? ? SIMPLE SWITCHER ? V ǚL*dI/dt ? ?? ? ? ? 1A ? ? ? ? ? dI/dt ? ? 1a 1b ? ? ? ? 1c ? dI/dt ? ? ? ǖ ? ? ? ? 1.2?? 0.8?? ? ? ? ?? FET , LM267x 30ns ? , LM259x 75ns ? ? ? ? ? ? ? ? ?? ? ? ? 30ns ? 1 ? 1A 0.7V ? ? 2.5mV ? ?? 2 ? 3A 4V ? 1c ? ? 1a 1b ? ??? ? , IC ? ?? ?SW ?? ? ? ? ?? , ?? ?VIN ?? ? ? ?? 1c ? ? ? ?VIN ? ? ? ? , ? ? ?? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Np/Ns ?? ? RCD ? ? ? ? ? ?? ?? ? ? ? ? ? ?? ? ?? ? ? ? ? , ǖ EMI ? ? ? ? ? ? IC ? ? ? ? ? IC ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ǜ ?? ? ? ?? ? ? ? V*dt ǚL*dI ? , L ? ?V*dt ? ? ? , ? ??? ? ? ? ? ?? ? ? ? ? ? ?? ?COMP ?? ?? ? ?? ? ? ? ? ?? ?? ?? ? ?IC ? ? ? ? , ? ??

整车部设计手册总布置图

第一章整车集成 1.1总布置图绘制 1.1.1意义 根据新产品规划和概念设计确定车身总布置方案，然后再绘制总布置草图，然后开始进一步的 造型设计。其中整车总布置草图的绘制对后期的开发设计起到依据和指导作用。 1.1.2总布置草图的绘制 1.1. 2.1第一版总布置图-概念草图 1.1. 2.1.1相关输入及流程 为了给造型提供工程依据和下一步设计提供指导，绘制出总布置概念草图。总布置草图的绘制 开始于项目预研阶段，根据新产品的规划，对竞品车进行扫描分析，根据发动机舱初步布置数据得 出初步的整车限制尺寸和人机工程目标；依照相应的法律法规要求，并根据现有产品尽可能的考虑 通用化的前提下确定车身总布置方案。 总布置概念草图的绘制时间及相关流程见图1-1所示。 图1-1总布置草图绘制时间及流程 1.1. 2.1.2总布置草图内容 草图阶段的总布置图，主要是对造型的输入，体现总布置的基本硬点参数，其中最重要的是H 点的位置，Ｈ点是整车的设计参考点，必须在早期准确地确定，一旦更改将对整个前期的布置设计 及项目进度产生重大的影响。

在草图阶段的总布置图中，主要体现如下内容： 1、Ｈ点坐标，人机内部空间等相关参数； 2、整车外廓尺寸，包括长、宽、高、轮距、轴距、前悬、后悬； 3、法规要求及设计目标； 4、COP零件的状态； 5.三种载荷状态的地面线； 6、各种限制面； 7、其他，如车门形式、玻璃曲率等。 1.1. 2.1.3绘制概念草图步骤 在绘制概念草图之前，是在已经了解项目定位、对项目有了初步策划方案，并且对竞品车或对 标车进行了大量分析的前提下开始绘制。 通常，概念草图的绘制需要如下步骤： （1）首先建立车身坐标系，“国标”定义的“整车坐标系”。通过空载或设计载荷时车轮中心（左、右前轮和左、右后轮）及地板门槛纵平面来确定整车坐标系。然后摆放车姿，如图1-2所示。 图1-2 （2）确定踏板和踵点位置，如图1-3所示。 踏板组 后踵点 前踵点 图1-3

开关电源PCB设计实例

开关电源PCB设计实例 标签：开关电源PCB 印制电路板的制作 所有开关电源设计的最后一步就是印制电路板(PCB)的线路设计。如果这部分设计不当，PCB也会使电源工作不稳定，发射出过量的电磁干扰(EMI)。设计者的作用就是在理解电路工作过程的基础上，保证PCB设计合理。 开关电源中，有些信号包含丰富的高频分量，因而任何一条PCB引线都可能成为天线。引线的长和宽影响它的电阻和电感量，进而关系到它们的频率响应。即使是传送直流信号的引线，也会从邻近的引线上引入RF(射频)信号，使电路发生故障，或者把这干扰信号再次辐射出去。所有传送交流信号的引线要尽可能短且宽。这意味着任何与多条功率线相连的功率器件要尽可能紧挨在一起，以减短连线长度。引线的长度直接与它的电感量和电阻量成比例，它的宽度则与电感量和电阻量成反比。引线长度就决定了其响应信号的波长，引线越长，它能接收和传送的干扰信号频率就越低，它所接收到的RF(射频)能量也越大。 主要电流环路 每一个开关电源内部都有四个电流环路，每个环路要与其他环路分开。由于它们对PCB布局的重要性，下面把它们列出来： 1．功率开关管交流电流环路。 2．输出整流器交流电流环路。 3．输入电源电流环路。 4．输出负载电流环路。

图59a、b、c画出了三种主要开关电源拓扑的环路。 通常输入电源和负载电流环路并没有什么问题。这两个环路上主要是在直流电流上叠加了一些小的交流电流分量。它们一般有专门的滤波器来阻止交流噪声进入周围的电路。输入和输出电流环路连接的位置只能是相应的输入输出电容的接线端。输入环路通过近似直流的电流对输入电容充电，但它无法提供开关电源所需的脉冲电流。输入电容主要是起到高频能量存储器的作用。类似地，输出滤波电容存储来自输出整流器的高频能量，使输出负载环能以直流方式汲取能量。因此，输入和输出滤波电容接线端的放置很重要。如果输入或输出环与功率开关或整流环的连接没有直接接到电容的两端，交流能量就会从输入或输出滤波电容上流进流出，并通过输入和输出电流环“逃逸”到外面环境中。 功率开关和整流器的交流电流环路包含非常高的PWM开关电源典型的梯形电流波形。这些波形含有延展到远高于基本开关频率的谐波。这些交流电流的峰值有可能是连续输入或输出直流电流的2～5倍。典型的转换时间大约是50ns，因而这两个环路最有可能产生电磁干扰(EMI)。 在电源PCB制作中，这些交流电流环路的布线要在其他引线之前布好。每个环路由三个主要器件组成：滤波电容、功率开关管或整流器、电感或变压器。它们的放置要尽可能靠近。这些器件的方向也要确定好，以使它们之间的电流通路尽可能短。图60就

HT32系列单片机晶振ADC设计的注意事项及PCB布局指引

HT32系列单片机晶振&ADC设计的注意事项及PCB布局指南HT32系列单片机晶振&ADC设计的注意事项及PCB布局指南文件编码：A N0301S 简介 该应用范例介绍盛群32-bit HT32系列单片机关于晶体振荡器和ADC（模数转换器）的硬件 设计。晶体振荡器的架构是基于Pierce振荡器，ADC的设计是采用SAR结构。同时该应用 范例还提供了PCB布局指南。 晶体振荡器 HT32系列单片机支持四种类型的振荡器 --- 内部高速RC振荡器(HSI)，外部高速晶振 (HSE)，内部低速RC振荡器(LSI)和外部低速晶振(LSE)。本章节介绍HSE和LSE晶体振荡 器。 晶振等效电路 图1显示了一个接近主要振动模式下的晶振频率的常规等效电路。L qz, C s, R qz是晶体振荡 的动态参数。参数C p表示电极间的分布电容产生的分流电容。 图1 晶振等效电路

表1举例说明了标准8MHz频率下的元件参数值。 等效元件参数值 L qz 24.38mH C s 0.016pF R qz 50 C p 5pF 表1 标准8MHz频率下的元件参数值 HT32系列单片机中的Pierce振荡器 图2显示了Pierce振荡器的架构。基于Pierce振荡器低功耗，低成本及稳定的优势，HT32系列单片机的内部振荡电路设计采用了Pierce振荡器。 图2 Pierce振荡器架构

HT32系列单片机晶振的应用电路 图3显示了HT32系列单片机中Pierce 振荡电路。以下公式便于用户选择外部负载电容。 图3 HT32系列单片机中的晶振电路 图3中的参数描述-- X: 石英晶体或陶瓷谐振器 R f : 外部反馈电阻 R ext : 用来限制反相输出电流的外部电阻 C L1和C L2: 两个外部负载电容 C stray : 印刷电路板和接头上的分布电容，它是寄生电容。 ? R f 代表在高增益区反相器偏置的反馈电阻。R f 不能太小，否则反馈回路可能不能振荡。在HT32系列单片机中，8MHz HSE 采用的R f 为1M Ω；32768Hz LSE 采用的R f 为10M Ω。 ? R ext 代表阻尼电阻，有助于省电，提高稳定性，抑制高频区域内的增益。插入R ext 是为了减少负电阻。所以，R ext 不能太大，否则反馈回路可能不能振荡。有时用户可能会在高频振荡应用中省去R ext 来降低生产成本。 ? 根据晶体或陶瓷谐振器负载电容C L 规范来决定外部电容C L1和C L2，便于晶振制造商调整到指定的频率。晶体或陶瓷谐振器制造商必须提供C L 的值。为使振荡器稳定振荡，负载电容C L 可根据以下公式得到： stray L2L1L2L1 L C C C C C C ++?= 事实上，芯片输入/输出口，焊盘，封装引脚，印刷电路板有助于寄生电容C stray 形成负载电 容C L 。所以，晶体或陶瓷谐振器所需的外部负载电容C L1和C L2将有所限制。 C L1和C L2计算范例 如果晶振中C L = 10pF ，假设Cstray = 5pF ，所以， 5pF 5pF -pF 10 C C C C C -C L2 L1L2L1stray L ==+?=

汽车总布置设计毕业设计(含外文翻译)

摘要 随着汽车行业的蓬勃发展，以及人机工程学、空气动力学在汽车上的应用，车身总布置也在飞速的变革与发展。车身总布置设计是经验和原理方法的结合，是在考虑整车形式、车身与底盘的关系、以及总布置和造型传递给车身内部布置的一些约束条件下，进行车室内部布置，是基于功能和约束的方案寻求最优的过程。一个与众不同的驾驶空间：开阔的视野，舒适的座椅布置，布置紧凑的仪表以及伸手可及的操作元件，能给人充分的心理满足和安全感。人机工程学、空气动力学和现代化制造方法的发展促使汽车车身总布置的不断更新和完善，传统与创新艺术风格的有机结合也影响着车身总布置的美学实践。然而，每一款新车型的问世都离不开车身总布置和它的设计工具，汽车车身总布置是汽车概念设计阶段的一项相当重要的方案设计工作。 本次设计主要内容是根据人机工程学的理论和在汽车上实际应用的分析，进行总布置设计。本文介绍汽车总布置设计工具人体模型，眼椭圆。提出了综合考虑驾驶员舒适性、视野性、腿部操纵空间、方向盘、顶盖等因素的H 点区域法。利用CATIA进行总布置设计,CATIA对于提高车身总布置的质量，以及缩短产品开发周期具有非常大的现实意义 关键词：车身总布置设计；人机工程学；人体模型；眼椭圆。

Abstract With the vigorous development of auto industry, and ergonomics, air dynamics in automotive applications, general arrangement in the rapid development and reform. Body: the layout design experience and the principle of method is combined, is considering vehicle body and forms, the chassis layout, and transfer to body shape and some internal layout constraints on car interior ministry decorate, it is based on the function and constraints for the solution of the optimal process. A special driving space: open vision, comfortable seats arrangement of instrumentation and arrangement, compact and operating components, can give a person to fully satisfy the psychology and security. the modern automobile body is always arranging also in the rapid transformation and the development.The man-machine engineering, the aerodynamics and the modernized manufacture method development urges the unceasing renewal and the consummation which the automobile body always arranges, traditional and the innovation artistic style organic synthesis is also affecting esthetics practice which the automobile body always arranges.However, each section new vehicle being published cannot leave the automobile body always to arrange and its design tool, the automobile body total arrangement is an automobile conceptual design stage quite important project design work. T he main content of the theory is based on ergonomics in cars and practical application analysis, the layout design. Introduces the layout design tool car body model, elliptic. Puts forward comprehensive consideration of the pilot, leg vision comfortableness, manipulation of space, the steering wheel, the above factors zone method H. To improve the CATIA layout of quality, body and shorten the development cycle has very great practical significance Keywords: body layout design, Ergonomics, Human model, Eye ellipse.