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4050 CMOS 六同相缓冲器-转换器

October 1987

Revised January 1999

CD4049UBC

? CD4050BC Hex Inverting Buffer ? Hex Non-Inverting Buffer ? 1999 Fairchild Semiconductor Corporation DS005971.prf https://www.wendangku.net/doc/b58794609.html, CD4049UBC ? CD4050BC

Hex Inverting Buffer ?

Hex Non-Inverting Buffer

General Description

The CD4049UBC and CD4050BC hex buffers are mono-

lithic complementary MOS (CMOS) integrated circuits con-

structed with N- and P-channel enhancement mode

transistors. These devices feature logic level conversion

using only one supply voltage (V DD). The input signal high

level (V IH) can exceed the V DD supply voltage when these

devices are used for logic level conversions. These

devices are intended for use as hex buffers, CMOS to DTL/

TTL converters, or as CMOS current drivers, and at V DD=

5.0V, they can drive directly two DTL/TTL loads over the

full operating temperature range.

Features

s Wide supply voltage range: 3.0V to 15V

s Direct drive to 2 TTL loads at 5.0V over full temperature

range

s High source and sink current capability

s Special input protection permits input voltages greater

than V DD

Applications

?CMOS hex inverter/buffer

?CMOS to DTL/TTL hex converter

?CMOS current “sink” or “source” driver

?CMOS HIGH-to-LOW logic level converter

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP

CD4049UBC

Top View

CD4050BC

Top View

Order Number Package Number Package Description

CD4049UBCM M16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

CD4049UBCN N16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

CD4050BCM M16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

CD4050BCN N16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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C D 4049U B C ? C D 4050B C

Schematic Diagrams

CD4049UBC 1 of 6 Identical Units

CD4050BC

1 of 6 Identical Units

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CD4049UBC ? CD4050BC

Absolute Maximum Ratings (Note 1)

(Note 2)

Recommended Operating Conditions (Note 2)

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of “Recom-mended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation.Note 2: V SS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

Note 3: V SS = 0V unless otherwise specified.

Supply Voltage (V DD )?0.5V to +18V Input Voltage (V IN )

?0.5V to +18V Voltage at Any Output Pin (V OUT )?0.5V to V DD + 0.5V Storage Temperature Range (T S )?65°C to +150°C

Power Dissipation (P D )Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (T L )(Soldering, 10 seconds)

260°C Supply Voltage (V DD )3V to 15V Input Voltage (V IN )

0V to 15V Voltage at Any Output Pin (V OUT )0 to V DD

Operating T emperature Range (T A )CD4049UBC, CD4050BC

?40°C to +85°C

Symbol Parameter

Conditions

?40°C +25°C +85°C Units Min

Max Min

Typ Max Min

Max I DD

Quiescent Device Current

V DD = 5V 40.03 4.030μA V DD = 10V 80.058.060μA V DD = 15V

0.07

16.0

120

μA

V OL

LOW Level Output Voltage

V IH = V DD , V IL = 0V ,|I O | < 1 μA V DD = 5V 0.0500.050.05V V DD = 10V 0.0500.050.05V V DD = 15V

0.05

V OH

HIGH Level Output Voltage

V IH = V DD , V IL = 0V ,|I O | < 1 μA V DD = 5V 4.95 4.955 4.95V V DD = 10V 9.959.95109.95V V DD = 15V

14.95

1514.95

V V IL

LOW Level Input Voltage |I O | < 1 μA

(CD4050BC Only)

V DD = 5V, V O = 0.5V 1.5 2.25 1.5 1.5V V DD = 10V , V O = 1V 3.0 4.5 3.0 3.0V V DD = 15V , V O = 1.5V

4.0 6.75 4.0 4.0V V IL

LOW Level Input Voltage |I O | < 1 μA

(CD4049UBC Only)

V DD = 5V, V O = 4.5V 1.0 1.5 1.0 1.0V V DD = 10V , V O = 9V 2.0 2.5 2.0 2.0V V DD = 15V , V O = 13.5V

3.0

3.5

3.0

V V IH

HIGH Level Input Voltage |I O | < 1 μA

(CD4050BC Only)

V DD = 5V, V O = 4.5V 3.5 3.5 2.75 3.5V V DD = 10V , V O = 9V 7.07.0 5.57.0V V DD = 15V , V O = 13.5V

11.011.08.2511.0V V IH

HIGH Level Input Voltage |I O | < 1 μA

(CD4049UBC Only)

V DD = 5V, V O = 0.5V 4.0 4.0 3.5 4.0V V DD = 10V , V O = 1V 8.08.07.58.0V V DD = 15V , V O = 1.5V

12.012.011.512.0V I OL

LOW Level Output Current V IH = V DD , V IL = 0V (Note 4)

V DD = 5V, V O = 0.4V 4.6 4.05 3.2mA V DD = 10V , V O = 0.5V 9.88.512 6.8mA V DD = 15V , V O = 1.5V

29254020mA I OH

HIGH Level Output Current V IH = V DD , V IL = 0V (Note 4)

V DD = 5V, V O = 4.6V ?1.0?0.9?1.6?0.72mA V DD = 10V , V O = 9.5V ?2.1?1.9?3.6?1.5mA V DD = 15V , V O = 13.5V

?7.1?6.2?12?5

mA I IN

Input Current

V DD = 15V , V IN = 0V ?0.3?0.3?10?5?1.0μA V DD = 15V , V IN = 15V

0.3

10?5

1.0

μA

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C D 4049U B C ? C D 4050B C

DC Electrical Characteristics (Continued)

Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be allowed to exceed this value for extended periods of time. I OL and I OH are tested one output at a time.

AC Electrical Characteristics (Note 5)

CD4049UBC

T A = 25°C, C L = 50 pF , R L = 200k, t r = t f = 20 ns, unless otherwise specified

Note 5: AC Parameters are guaranteed by DC correlated testing.

AC Electrical Characteristics (Note 6)

CD4050BC

T A = 25°C, C L = 50 pF , R L = 200k, t r = t f = 20 ns, unless otherwise specified

Note 6: AC Parameters are guaranteed by DC correlated testing.

Symbol Parameter

Conditions Min Typ Max Units t PHL

Propagation Delay Time V DD = 5V 3065ns HIGH-to-LOW Level

V DD = 10V 2040ns V DD = 15V 1530ns t PLH

Propagation Delay Time V DD = 5V 4585ns LOW-to-HIGH Level

V DD = 10V 2545ns V DD = 15V 2035ns t THL

T ransition Time V DD = 5V 3060ns HIGH-to-LOW Level

V DD = 10V 2040ns V DD = 15V 1530ns t TLH

T ransition Time V DD = 5V 60120ns LOW-to-HIGH Level

V DD = 10V 3055ns V DD = 15V 2545ns C IN

Input Capacitance

Any Input

22.5

Symbol Parameter

Conditions Min Typ Max Units t PHL

Propagation Delay Time V DD = 5V 60110ns HIGH-to-LOW Level

V DD = 10V 2555ns V DD = 15V 2030ns t PLH

Propagation Delay Time V DD = 5V 60120ns LOW-to-HIGH Level

V DD = 10V 3055ns V DD = 15V 2545ns t THL

T ransition Time V DD = 5V 3060ns HIGH-to-LOW Level

V DD = 10V 2040ns V DD = 15V 1530ns t TLH

T ransition Time V DD = 5V 60120ns LOW-to-HIGH Level

V DD = 10V 3055ns V DD = 15V 2545ns C IN

Input Capacitance

Any Input

7.5

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CD4049UBC ? CD4050BC

Switching Time Waveforms

Typical Applications

CMOS to TLL or CMOS at a Lower V DD

V DD1 ≥ V DD2

In the case of the CD4049UBC the output drive capability increases with increasing input voltage. E.g., If V DD1 = 10V the CD4049UBC could drive 4 TTL loads.

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C D 4049U B C ? C D 4050B C

Physical Dimensions

inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

CD4049UBC

? CD4050BC Hex Inverting Buffer ? Hex Non-Inverting Buffer LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1.Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support

device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

F a irch ild d o e s n o t a ssu m e a n y re sp o n sib ility fo r u se o f a n y circu itry d e scrib e d, no circu it p a te n t licen se s a re im p lie d an d F a irch ild re se rv e s th e rig h t a t an y tim e w itho u t n o tice to ch a n g e sa id circu itry a n d sp e cificatio n s.