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CY7C68001_05中文资料

EZ-USB SX2? High-Speed USB Interface Device

CY7C68001

1.0 EZ-USB SX2? Features

?USB 2.0-certified compliant

—On the USB-IF Integrators List: Test ID Number 40000713

?Operates at high (480 Mbps) or full (12 Mbps) speed ?Supports Control Endpoint 0:

—Used for handling USB device requests ?Supports four configurable endpoints that share a 4-KB FIFO space

—Endpoints 2, 4, 6, 8 for application-specific control and data

?Standard 8- or 16-bit external master interface

—Glueless interface to most standard microproces-sors DSPs, ASICs, and FPGAs

—Synchronous or Asynchronous interface ?Integrated phase-locked loop (PLL)

?3.3V operation, 5V tolerant I/Os

?56-pin SSOP and QFN package

?Complies with most device class specifications 2.0 Applications

?DSL modems

?ATA interface

?Memory card readers

?Legacy conversion devices

?Cameras

?Scanners

?Home PNA

?Wireless LAN

?MP3 players

?Networking

?Printers

The “Reference Designs” section of the Cypress web site provides additional tools for typical USB applications. Each reference design comes complete with firmware source code and object code, schematics, and documentation. Please see the Cypress web site at https://www.wendangku.net/doc/b58939530.html,.

2.1Block Diagram

2.2

Introduction

The EZ-USB SX2? USB interface device is designed to work with any external master, such as standard microprocessors,DSPs, ASICs, and FPGAs to enable USB 2.0 support for any peripheral design. SX2 has a built-in USB transceiver and Serial Interface Engine (SIE), along with a command decoder for sending and receiving USB data. The controller has four endpoints that share a 4-KB FIFO space for maximum flexi-bility and throughput, as well as Control Endpoint 0. SX2 has three address pins and a selectable 8- or 16- bit data bus for command and data input or output.

2.3System Diagram

3.0

Functional Overview

3.1

USB Signaling Speed

SX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:?Full-speed, with a signaling bit rate of 12 Mbits/s ?High-speed, with a signaling bit rate of 480 Mbits/s.SX2 does not support the low-speed signaling rate of 1.5Mbits/s.

3.2Buses

SX2 features:

?A selectable 8- or 16-bit bidirectional data bus

?An address bus for selecting the FIFO or Command Inter-face.

3.3

Boot Methods

During the power-up sequence, internal logic of the SX2checks for the presence of an I 2C EEPROM.[1,2] If it finds an EEPROM, it will boot off the EEPROM. When the presence of an EEPROM is detected, the SX2 checks the value of first byte. If the first byte is found to be a 0xC4, the SX2 loads the next two bytes into the IFCONFIG and POLAR registers,respectively. If the fourth byte is also 0xC4, the SX2enumerates using the descriptor in the EEPROM, then signals to the external master when enumeration is complete via an ENUMOK interrupt (Section 3.4). If no EEPROM is detected,the SX2 relies on the external master for the descriptors. Once this descriptor information is received from the external master, the SX2 will connect to the USB and enumerate.3.3.1

EEPROM Organization

The valid sequence of bytes in the EEPROM are displayed below

Notes:

1.Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0

to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-byte EEPROMs (24LC64, etc.) should be strapped to address 001.

2.The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull-up values are 2.2K–10K

Ohms.

Figure 2-2. Example USB System Diagram

Table 3-1. Descriptor Length Set to 0x06:

Default Enumeration Byte Index

Description

00xC41IFCONFIG 2POLAR 30xC4

4Descriptor Length (LSB):0x065

Descriptor Length (MSB): 0x006VID (LSB)7VID (MSB)8PID (LSB)9PID (MSB)10DID (LSB)11

DID (MSB)

Table 3-2. Descriptor Length Not Set to 0x06Byte Index

Description

00xC41IFCONFIG 2POLAR 30xC4

4Descriptor Length (LSB)5Descriptor Length (MSB 6Descriptor[0]7Descriptor[1]8

Descriptor[2]

?0xC4: This initial byte tells the SX2 that this is a valid EE-PROM with configuration information.

?IFCONFIG: The IFCONFIG byte contains the settings for the IFCONFIG register. The IFCONFIG register bits are de-fined in Section 7.1. If the external master requires an in-terface configuration different from the default, that interface can be specified by this byte.

?POLAR: The Polar byte contains the polarity of the FIFO flag pin signals. The POLAR register bits are defined in Section 7.3. If the external master requires signal polarity different from the default, the polarity can be specified by this byte.

?Descriptor: The Descriptor byte determines if the SX2

loads the descriptor from the EEPROM. If this byte = 0xC4, the SX2 will load the descriptor starting with the next byte.

If this byte does not equal 0xC4, the SX2 will wait for de-scriptor information from the external master.?Descriptor Length: The Descriptor length is within the next two bytes and indicate the length of the descriptor contained within the EEPROM. The length is loaded least significant byte (LSB) first, then most significant byte (MSB).

?Byte Index 6 Starts Descriptor Information: The descrip-tor can be a maximum of 500 bytes.

3.3.2Default Enumeration

An optional default descriptor can be used to simplify enumer-ation. Only the Vendor ID (VID), Product ID (PID), and Device ID (DID) need to be loaded by the SX2 for it to enumerate with this default set-up. This information is either loaded from an EEPROM in the case when the presence of an EEPROM (Table3-1) is detected, or the external master may simply load a VID, PID, and DID when no EEPROM is present. In this default enumeration, the SX2 uses the in-built default descriptor (refer to Section 12.0).

If the descriptor length loaded from the EEPROM is 6, SX2 will load a VID, PID, and DID from the EEPROM and enumerate. The VID, PID, and DID are loaded LSB, then MSB. For example, if the VID, PID, and DID are 0x0547, 0x1002, and 0x0001, respectively, then the bytes should be stored as:

?0x47, 0x05, 0x02, 0x10, 0x01, 0x00.

If there is no EEPROM, SX2 will wait for the external master to provide the descriptor information. To use the default descriptor, the external master must write to the appropriate register (0x30) with descriptor length equal to 6 followed by the VID, PID, and DID. Refer to Section 4.2 for further information on how the external master may load the values.

The default descriptor enumerates four endpoints as listed in the following page:

?Endpoint 2: Bulk out, 512 bytes in high-speed mode, 64 bytes in full-speed mode

?Endpoint 4: Bulk out, 512 bytes in high-speed mode, 64 bytes in full-speed mode

?Endpoint 6: Bulk in, 512 bytes in high-speed mode, 64 bytes in full-speed mode

?Endpoint 8: Bulk in, 512 bytes in high-speed mode, 64 bytes in full-speed mode.

The entire default descriptor is listed in Section 12.0 of this data sheet.3.4Interrupt System

3.4.1Architecture

The SX2 provides an output signal that indicates to the external master that the SX2 has an interrupt condition, or that the data from a register read request is available. The SX2 has six interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK, BUSACTIVITY, and READY. Each interrupt can be enabled or disabled by setting or clearing the corresponding bit in the INTENABLE register.

When an interrupt occurs, the INT# pin will be asserted, and the corresponding bit will be set in the Interrupt Status Byte. The external master reads the Interrupt Status Byte by strobing SLRD/SLOE. This presents the Interrupt Status Byte on the lower portion of the data bus (FD[7:0]). Reading the Interrupt Status Byte automatically clears the interrupt. Only one interrupt request will occur at a time; the SX2 buffers multiple pending interrupts.

If the external master has initiated a register read request, the SX2 will buffer interrupts until the external master has read the data. This insures that after a read sequence has begun, the next interrupt that is received from the SX2 will indicate that the corresponding data is available. Following is a description of this INTENABLE register.

3.4.2INTENABLE Register Bit Definition

Bit 7: SETUP

If this interrupt is enabled, and the SX2 receives a set-up packet from the USB host, the SX2 asserts the INT# pin and sets bit 7 in the Interrupt Status Byte. This interrupt only occurs if the set-up request is not one that the SX2 automatically handles. For complete details on how to handle the SETUP interrupt, refer to Section 5.0 of this data sheet.

Bit 6: EP0BUF

If this interrupt is enabled, and the Endpoint 0 buffer becomes available to the external master for read or write operations, the SX2 asserts the INT# pin and sets bit 6 in the Interrupt Status Byte. This interrupt is used for handling the data phase of a set-up request. For complete details on how to handle the EP0BUF interrupt, refer to Section 5.0 of this data sheet.

Bit 5: FLAGS

If this interrupt is enabled, and any OUT endpoint FIFO’s state changes from empty to not-empty and from not-empty to empty, the SX2 asserts the INT# pin and sets bit 5 in the Interrupt Status Byte. This is an alternate way to monitor the status of OUT endpoint FIFOs instead of using the FLAGA-FLAGD pins, and can be used to indicate when an OUT packet has been received from the host.

Bit 2: ENUMOK

If this interrupt is enabled and the SX2 receives a SET_CONFIGURATION request from the USB host, the SX2 asserts the INT# pin and sets bit 2 in the Interrupt Status Byte. This event signals the completion of the SX2 enumeration process.

Bit 1: BUSACTIVITY

If this interrupt is enabled, and the SX2 detects either an absence or resumption of activity on the USB bus, the SX2 asserts the INT# pin and sets bit 1 in the Interrupt Status Byte. This usually indicates that the USB host is either suspending

or resuming or that a self-powered device has been plugged in or unplugged. If the SX2 is bus-powered, the external master must put the SX2 into a low-power mode after detecting a USB suspend condition to be USB-compliant.

Bit 0: READY

If this interrupt is enabled, bit 0 in the Interrupt Status Byte is set when the SX2 has powered up and performed a self-test. The external master should always wait for this interrupt before trying to read or write to the SX2, unless an external EEPROM with a valid descriptor is present. If an external EEPROM with a valid descriptor is present, the ENUMOK interrupt will occur instead of the READY interrupt after power up. A READY interrupt will also occur if the SX2 is awakened from a low-power mode via the WAKEUP pin. This READY interrupt indicates that the SX2 is ready for commands or data.

3.4.3Qualify with READY Pin on Register Reads Although it is true that all interrupts will be buffered once a command read request has been initiated, in very rare condi-tions, there might be a situation when there is a pending interrupt already, when a read request is initiated by the external master. In this case it is the interrupt status byte that will be output when the external master asserts the SLRD. So, a condition exists where the Interrupt Status Data Byte can be mistaken for the result of a command register read request. In order to get around this possible race condition, the first thing that the external master must do on getting an interrupt from the SX2 is check the status of the READY pin. If the READY is low at the time the INT# was asserted, the data that will be output when the external master strobes the SLRD is the interrupt status byte (not the actual data requested). If the READY pin is high at the time when the interrupt is asserted, the data output on strobing the SLRD is the actual data byte requested by the external master. So it is important that the state of the READY pin be checked at the time the INT# is asserted to ascertain the cause of the interrupt.

3.5Resets and Wakeup

3.5.1Reset

An input pin (RESET#) resets the chip. The internal PLL stabi-lizes after V CC has reached 3.3V. Typically, an external RC network (R = 100 KOhms, C = 0.1 μF) is used to provide the RESET# signal. The Clock must be in a stable state for at least 200 μs before the RESET is released.

3.5.2USB Reset

When the SX2 detects a USB Reset condition on the USB bus, SX2 handles it like any other enumeration sequence. This means that SX2 will enumerate again and assert the ENUMOK interrupt to let the external master know that it has enumerated. The external master will then be responsible for configuring the SX2 for the application. The external master should also check whether SX2 enumerated at High or Full speed in order to adjust the EPxPKTLENH/L register values accordingly. The last initialization task is for the external master to flush all of the SX2 FIFOs.

3.5.3Wakeup

The SX2 exits its low-power state when one of the following events occur:

?USB bus signals a resume. The SX2 will assert a BUSAC-TIVITY interrupt.

?The external master asserts the WAKEUP pin. The SX2 will assert a READY interrupt[3].

3.6Endpoint RAM

3.6.1Size

?Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).?FIFO Endpoints: 4096 Bytes: 8 × 512 bytes (Endpoint 2, 4, 6, 8).

3.6.2Organization

?EP0–Bidirectional Endpoint 0, 64-byte buffer.

?EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or iso-chronous. EP2 and EP6 can be either double-, triple-, or quad-buffered. EP4 and EP8 can only be double-buffered.

For high-speed endpoint configuration options, see

Figure3-1.

Note:

3.If the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic will perform RESUME

signalling after a WAKEUP interrupt.

3.6.3Endpoint Configurations (High-speed Mode)

Endpoint 0 is the same for every configuration as it serves as the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to Figure3-1. Endpoints 2, 4, 6, and 8 may be configured by choosing either:

?One configuration from Group A and one from Group B ?One configuration from Group C.

Some example endpoint configurations are as follows.

?EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-buffered.

?EP2: 512 bytes double-buffered, EP4: 512 bytes double-buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes double buffered.

?EP2: 1024 bytes quad-buffered.

3.6.4Default Endpoint Memory Configuration

At power-on-reset, the endpoint memories are configured as follows:

?EP2: Bulk OUT, 512 bytes/packet, 2x buffered.

?EP4: Bulk OUT, 512 bytes/packet, 2x buffered.

?EP6: Bulk IN, 512 bytes/packet, 2x buffered.

?EP8: Bulk IN, 512 bytes/packet, 2x buffered.

3.7External Interface

The SX2 presents two interfaces to the external master.

1.A FIFO interface through which EP2, 4, 6, and 8 data flows.

2.A command interface, which is used to set up the SX2, read

status, load descriptors, and access Endpoint 0.

3.7.1Architecture

The SX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals (IFCLK, CS#, SLRD, SLWR, SLOE, PKTEND, and FIFOADR[2:0]).

The SX2 command interface is used to set up the SX2, read status, load descriptors, and access Endpoint 0. The command interface has its own READY signal for gating writes, and an INT# signal to indicate that the SX2 has data to be read, or that an interrupt event has occurred. The command interface uses the same control signals (IFCLK, CS#, SLRD, SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface, except for PKTEND.

3.7.2Control Signals

3.7.2.1FIFOADDR Lines

The SX2 has three address pins that are used to select either the FIFOs or the command interface. The addresses corre-spond to the following table.

The SX2 accepts either an internally derived clock (30 or 48 MHz) or externally supplied clock (IFCLK, 5–50 MHz), and SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals from an external master. The interface can be selected for 8-

Figure 3-1. Endpoint Configuration

Table 3-3. FIFO Address Lines Setting

Address/Selection FIFOADR2FIFOADR1FIFOADR0

FIFO2000

FIFO4001

FIFO6010

FIFO8011

COMMAND100

RESERVED101

RESERVED110

RESERVED111

or 16- bit operation by an internal configuration bit, and an Output Enable signal SLOE enables the data bus driver of the selected width. The external master must ensure that the output enable signal is inactive when writing data to the SX2. The interface can operate either asynchronously where the SLRD and SLWR signals act directly as strobes, or synchro-nously where the SLRD and SLWR act as clock qualifiers. The optional CS# signal will tristate the data bus and ignore SLRD, SLWR, PKTEND.

The external master reads from OUT endpoints and writes to IN endpoints, and reads from or writes to the command interface.

3.7.2.2Read: SLOE and SLRD

In synchronous mode, the FIFO pointer is incremented on each rising edge of IFCLK while SLRD is asserted. In asynchronous mode, the FIFO pointer is incremented on each asserted-to-deasserted transition of SLRD.

SLOE is a data bus driver enable. When SLOE is asserted, the data bus is driven by the SX2.

3.7.2.3Write: SLWR

In synchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of IFCLK while SLWR is asserted. In asynchronous mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each asserted-to-deasserted transition of SLWR.

3.7.2.4PKTEND

PKTEND commits the current buffer to USB. To send a short IN packet (one which has not been filled to max packet size determined by the value of PL[X:0] in EPxPKTLENH/L), the external master strobes the PKTEND pin.

All these interface signals have a default polarity of low. In order to change the polarity of PKTEND pin, the master may write to the POLAR register anytime. In order to switch the polarity of the SLWR/SLRD/SLOE, the master must set the appropriate bits 2, 3 and 4 respectively in the FIFOPINPOLAR register located at XDATA space 0xE609. Please note that the SX2 powers up with the polarities set to low. Section 7.3 provides further information on how to access this register located at XDATA space.

3.7.3IFCLK

The IFCLK pin can be configured to be either an input (default) or an output interface clock. Bits IFCONFIG[7:4] define the behavior of the interface clock. To use the SX2’s internally-derived 30- or 48-MHz clock, set IFCONFIG.7 to 1 and set IFCONFIG.6 to 0 (30 MHz) or to 1 (48 MHz). To use an exter-nally supplied clock, set IFCONFIG.7=0 and drive the IFCLK pin (5 MHz – 50 MHz). The input or output IFCLK signal can be inverted by setting IFCONFIG.4=1.

3.7.4FIFO Access

An external master can access the slave FIFOs either asynchronously or synchronously:

?Asynchronous–SLRD, SLWR, and PKTEND pins are

strobes.

?Synchronous–SLRD, SLWR, and PKTEND pins are en-ables for the IFCLK clock pin.

An external master accesses the FIFOs through the data bus, FD [15:0]. This bus can be either 8- or 16-bits wide; the width is selected via the WORDWIDE bit in the EPxPKTLENH/L registers. The data bus is bidirectional, with its output drivers controlled by the SLOE pin. The FIFOADR[2:0] pins select which of the four FIFOs is connected to the FD [15:0] bus, or if the command interface is selected.

3.7.5FIFO Flag Pins Configuration

The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD. These FLAGx pins report the status of the FIFO selected by the FIFOADR[2:0] pins. At reset, these pins are configured to report the status of the following:

?FLAGA reports the status of the programmable flag.?FLAGB reports the status of the full flag.

?FLAGC reports the status of the empty flag.

?FLAGD defaults to the CS# function.

The FIFO flags can either be indexed or fixed. Fixed flags report the status of a particular FIFO regardless of the value on the FIFOADR [2:0] pins. Indexed flags report the status of the FIFO selected by the FIFOADR [2:0]pins.[4]

3.7.6Default FIFO Programmable Flag Set-up

By default, FLAGA is the Programmable Flag (PF) for the endpoint being pointed to by the FIFOADR[2:0] pins. For EP2 and EP4, the default endpoint configuration is BULK, OUT, 512, 2x, and the PF pin asserts when the entire FIFO has greater than/equal to 512 bytes. For EP6 and EP8, the default endpoint configuration is BULK, IN, 512, 2x, and the PF pin asserts when the entire FIFO has less than/equal to 512 bytes. In other words, EP6/8 report a half-empty state, and EP2/4 report a half-full state.

3.7.7FIFO Programmable Flag (PF) Set-up

Each FIFO’s programmable-level flag (PF) asserts when the FIFO reaches a user-defined fullness threshold. That threshold is configured as follows:

1.For OUT packets: The threshold is stored in PFC12:0. The

PF is asserted when the number of bytes in the entire FIFO is less than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold.

2.For IN packets, with PKTSTAT = 1: The threshold is stored

in PFC9:0. The PF is asserted when the number of bytes written into the current packet in the FIFO is less than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold.

3.For IN packets, with PKTSTAT = 0: The threshold is stored

in two parts: PKTS2:0 holds the number of committed pack-ets, and PFC9:0 holds the number of bytes in the current packet. The PF is asserted when the FIFO is at or less full than (DECIS = 0), or at or more full than (DECIS = 1), the threshold.

Note:

4.In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).

3.7.8

Command Protocol

An address of [1 0 0] on FIFOADR [2:0] will select the command interface. The command interface is used to write to and read from the SX2 registers and the Endpoint 0 buffer,as well as the descriptor RAM. Command read and write trans-actions occur over FD[7:0] only. Each byte written to the SX2is either an address or a data byte, as determined by bit7. If bit7 = 1, then the byte is considered an address byte. If bit7 =0, then the byte is considered a data byte. If bit7 = 1, then bit6determines whether the address byte is a read request or a write request. If bit6 = 1, then the byte is considered a read request. If bit6 = 0 then the byte is considered a write request.Bits [5:0] hold the register address of the request. The format of the command address byte is shown in Table 3-4.Each Write request is followed by two or more data bytes. If another address byte is received before both data bytes are received, the SX2 ignores the first address and any incomplete data transfers. The format for the data bytes is shown in Table 3-5 and Table 3-6. Some registers take a series of bytes.Each byte is transferred using the same protocol.The first command data byte contains the upper nibble of data,

and the second command byte contains the lower nibble of data.

3.7.8.1Write Request Example

Prior to writing to a register, two conditions must be met:FIFOADR[2:0] must hold [1 0 0], and the Ready line must be HIGH. The external master should not initiate a command if the READY pin is not in a HIgh state.

Example : to write the byte <10110000> into the IFCONFIG register (0x01), first send a command address byte as follows.?The first bit signifies an address transfer.

?The second bit signifies that this is a write command.?The next six bits represent the register address (000001 binary = 0x01 hex).

Once the byte has been received the SX2 pulls the READY pin low to inform the external master not to send any more information. When the SX2 is ready to receive the next byte,the SX2 pulls the READY pin high again. This next byte, the upper nibble of the data byte, is written to the SX2 as follows. ?The first bit signifies that this is a data transfer.?The next three are don’t care bits.

?The next four bits hold the upper nibble of the transferred byte.

Once the byte has been received the SX2 pulls the READY pin low to inform the external master not to send any more information. When the SX2 is ready to receive the next byte,the SX2 pulls the READY pin high again. This next byte, the lower nibble of the data byte is written to the SX2. At this point the entire byte <10110000> has been transferred to register 0x01 and the write sequence is complete.3.7.8.2Read Request Example

The Read cycle is simpler than the write cycle. The Read cycle consists of a read request from the external master to the SX2.For example, to read the contents of register 0x01, a command address byte is written to the SX2 as follows.When the data is ready to be read, the SX2 asserts the INT#pin to tell the external master that the data it requested is waiting on FD[7:0].[5]

Note:

5.An important note: Once the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources

described in Section 3.4 is asserted, the SX2 will buffer that interrupt until the read request completes.

Table 3-4. Command Address Byte

Address/Data#

Read/Write#

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Table 3-5. Command Data Byte One

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X X X D7D6D5D4

Table 3-6. Command Data Byte Two

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Table 3-7. Command Address Write Byte

Address/Data#

Read/Write#

10000001

Table 3-8. Command Data Write Byte One

Address/Data#

Don’t Care

0X X X 1011

Table 3-9. Command Data Write Byte Two

Address/Data#

Don’t Care

X X X 0000

Table 3-10. Command Address Read Byte

Address/Data#Read/Write#

11000001

4.0 Enumeration

The SX2 has two modes of enumeration. The first mode is automatic through EEPROM boot load, as described in Section 3.3. The second method is a manual load of the descriptor or VID, PID, and DID as described below.

4.1Standard Enumeration

The SX2 has 500 bytes of descriptor RAM into which the external master may write its descriptor. The descriptor RAM is accessed through register 0x30. To load a descriptor, the external master does the following:

?Initiate a Write Request to register 0x30.

?Write two bytes (four command data transfers) that define the length of the entire descriptor about to be transferred.

The LSB is written first, followed by the MSB.[6]

?Write the descriptor, one byte at a time until complete.[6] Note: the register address is only written once.

After the entire descriptor has been transferred, the SX2 will float the pull-up resistor connected to D+, and parse through the descriptor to locate the individual descriptors. After the SX2 has parsed the entire descriptor, the SX2 will connect the pull-up resistor and enumerate automatically. When enumer-ation is complete, the SX2 will notify the external master with an ENUMOK interrupt.

The format and order of the descriptor should be as follows (see Section 12.0 for an example):

?Device.

?Device qualifier.

?High-speed configuration, high-speed interface, high-

speed endpoints.

?Full-speed configuration, full-speed interface, full-speed endpoints.

?String.

The SX2 can be set to run in full speed only mode. To force full speed only enumeration write a 0x02 to the unindexed register CT1 at address 0xE6FB before downloading the descriptors. This disables the chirp mechanism forcing the SX2 to come up in full speed only mode after the descriptors are loaded. The CT1 register can be accessed using the unindexed register mechanism. Examples of writing to unindexed registers are shown in Section 5.1. Each write consists of a command write with the target register followed by the write of the upper nibble of the value followed by the write of the lower nibble of the value.

4.2Default Enumeration

The external master may simply load a VID, PID, and DID and use the default descriptor built into the SX2. To use the default descriptor, the descriptor length described above must equal 6. After the external master has written the length, the VID, PID, and DID must be written LSB, then MSB. For example, if the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001 respectively, then the external master does the following:?Initiates a Write Request to register 0x30.

?Writes two bytes (four command data transfers) that define the length of the entire descriptor about to be transferred.

In this case, the length is always six.

?Writes the VID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10, 0x01, 0x00 (in nibble format per the command protocol). The default descriptor is listed in Section 12.0. The default descriptor can be used as a starting point for a custom descriptor.

5.0 Endpoint 0

The SX2 will automatically respond to USB chapter 9 requests without any external master intervention. If the SX2 receives a request to which it cannot respond automatically, the SX2 will notify the external master. The external master then has the choice of responding to the request or stalling.

After the SX2 receives a set-up packet to which it cannot respond automatically, the SX2 will assert a SETUP interrupt. After the external master reads the Interrupt Status Byte to determine that the interrupt source was the SETUP interrupt, it can initiate a read request to the SETUP register, 0x32. When the SX2 sees a read request for the SETUP register, it will present the first byte of set-up data to the external master. Each additional read request will present the next byte of set-up data, until all eight bytes have been read.

The external master can stall this request at this or any other time. To stall a request, the external master initiates a write request for the SETUP register, 0x32, and writes any non-zero value to the register.

If this set-up request has a data phase, the SX2 will then interrupt the external master with an EP0BUF interrupt when the buffer becomes available. The SX2 determines the direction of the set-up request and interrupts when either:?IN: the Endpoint 0 buffer becomes available to write to, or ?OUT: the Endpoint 0 buffer receives a packet from the USB host.

For an IN set-up transaction, the external master can write up to 64 bytes at a time for the data phase. The steps to write a packet are as follows:

1.Wait for an EP0BUF interrupt, indicating that the buffer is

available.

2.Initiate a write request for register 0x31.

3.Write one data byte.

4.Repeat steps 2 and 3 until either all the data or 64 bytes

have been written, whichever is less.

5.Write the number of bytes in this packet to the byte count

T o send more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified in the wLength field (bytes 6,7) of the set-up packet. To send less than the requested amount of data, the external master writes a packet that is less than 64 bytes, or if a multiple of 64, the external master follows the data with a zero-length packet. When the SX2 sees a short or zero-length packet, it will complete the set-up transfer by automatically completing the handshake phase. The SX2 will not allow more data than the wLength field specified in the set-up packet. Note: the

Note:

6.These and all other data bytes must conform to the command protocol.

PKTEND pin does not apply to Endpoint 0. The only way to send a short or zero length packet is by writing to the byte count register with the appropriate value.

For an OUT set-up transaction, the external master can read each packet received from the USB host during the data phase. The steps to read a packet are as follows:

1.Wait for an EP0BUF interrupt, indicating that a packet was

received from the USB host into the buffer.

2.Initiate a read request for the byte count register, 0x3

3. This

indicates the amount of data received from the host.

3.Initiate a read request for register 0x31.

4.Read one byte.

5.Repeat steps 3 and 4 until the number of bytes specified in

the byte count register has been read.

To receive more than 64 bytes, the process is repeated. The SX2 internally stores the length of the data phase that was specified in the wLength field of the set-up packet (bytes 6,7). When the SX2 sees that the specified number of bytes have been received, it will complete the set-up transfer by automat-ically completing the handshake phase. If the external master does not wish to receive the entire transfer, it can stall the transfer.

If the SX2 receives another set-up packet before the current transfer has completed, it will interrupt the external master with another SETUP interrupt. If the SX2 receives a set-up packet with no data phase, the external master can accept the packet and complete the handshake phase by writing zero to the byte count register.

The SX2 automatically responds to all USB standard requests covered in chapter 9 of the USB 2.0 specification except the Set/Clear Feature Endpoint requests. When the host issues a Set Feature or a Clear feature request, the SX2 will trigger a SETUP interrupt to the external master. The USB spec requires that the device respond to the Set endpoint feature request by doing the following:

?Set the STALL condition on that endpoint.

The USB spec requires that the device respond to the Clear endpoint feature request by doing the following:

?Reset the Data Toggle for that endpoint

?Clear the STALL condition of that endpoint.

The register that is used to reset the data toggle TOGCTL (located at XDATA location 0xE683) is not an index register that can be addressed by the command protocol presented in Section 3.7.8. The following section provides further infor-mation on this register bits and how to reset the data toggle accordingly using a different set of command protocol sequence.

5.1Resetting Data Toggle

Following is the bit definition of the TOGCTL register:Bit 7: Q, Data Toggle Value

Q=0 indicates DATA0 and Q=1 indicates DATA1, for the endpoint selected by the I/O and EP3:0 bits. Write the endpoint select bits (IO and EP3:0), before reading this value.

Bit 6: S, Set Data Toggle to DATA1

After selecting the desired endpoint by writing the endpoint select bits (IO and EP3:0), set S=1 to set the data toggle to DATA1. The endpoint selection bits should not be changed while this bit is written.

Bit 5: R, Set Data Toggle to DATA0

Set R=1 to set the data toggle to DATA0. The endpoint selection bits should not be changed while this bit is written. Bit 4: IO, Select IN or OUT Endpoint

Set this bit to select an endpoint direction prior to setting its R or S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN endpoint.

Bit 3-0: EP3:0, Select Endpoint

Set these bits to select an endpoint prior to setting its R or S bit. Valid values are 0, 1, 2, , 6, and 8.

A two-step process is employed to clear an endpoint data toggle bit to 0. First, write to the TOGCTL register with an endpoint address (EP3:EP0) plus a direction bit (IO). Keeping the endpoint and direction bits the same, write a “1” to the R (reset) bit. For example, to clear the data toggle for EP6 configured as an “IN” endpoint, write the following values sequentially to TOGCTL:

00010110b

00110110b

Following is the sequence of events that the master should perform to set this register to 0x16:

1.Send Low Byte of the Register (0x83)

https://www.wendangku.net/doc/b58939530.html,mand address write of address 0x3A

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the Low Byte of

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the Low Byte of

2.Send High Byte of the Register (0xE6)

https://www.wendangku.net/doc/b58939530.html,mand address write of address 0x3B

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the High Byte of

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the High Byte of

3.Send the actual value to write to the register Register (in

this case 0x16)

https://www.wendangku.net/doc/b58939530.html,mand address write of address0x3C

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the register value

(0x01)

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the register value

(0x06)

The same command sequence needs to be followed to set TOGCTL register to 0x36. The same command protocol sequence can be used to reset the data toggle for the other endpoints.

TOGCTL0xE683 Bit #76543210 Bit Name Q S R I/O EP3EP2 EP1EP0 Read/Write R W W R/W R/W R/W R/W R/W Default00110010

In order to read the status of this register, the external master must do the following sequence of events:

1.Send Low Byte of the Register (0x83)

https://www.wendangku.net/doc/b58939530.html,mand address write of 0x3A

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the Low Byte of

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the Low Byte of

https://www.wendangku.net/doc/b58939530.html,mand address write of address 0x3B

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the High Byte of

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the High Byte of

3.Get the actual value from the TOGCTL register (0x16)

https://www.wendangku.net/doc/b58939530.html,mand address READ of 0x3C

6.0 Pin Assignments 6.156-pin SSOP

Note:

7. A * denotes programmable polarity.

FD13

FD14

FD15

GND

VCC

GND

*SLRD

*SLWR

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

*IFCLK

RESERVED

SCL

SDA

VCC

FD0

FD1

FD2

FD3

FD12

FD11

FD10

FD9

FD8

*WAKEUP

VCC

RESET#

GND

*FLAGD/CS#

*PKTEND

FIFOADR1

FIFOADR0

FIFOADR2

*SLOE

INT#

READY

VCC

*FLAGC

*FLAGB

*FLAGA

GND

VCC

GND

FD7

FD6

FD5

FD4

CY7C68001

56-pin SSOP

Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment[7]

6.256-pin QFN

6.3CY7C68001 Pin Definitions Table 6-1. SX2 Pin Definitions

QFN Pin SSOP

Pin Name Type Default Description

310AVCC Power N/A Analog V CC. This signal provides power to the analog section of the chip.

613AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.

916DMINUS I/O/Z Z USB D– Signal. Connect to the USB D– signal.

815DPLUS I/O/Z Z USB D+ Signal. Connect to the USB D+ signal.

4249RESET#Input N/A Active LOW Reset. Resets the entire chip. This pin is normally tied to V CC

through a 100K resistor, and to GND through a 0.1-μF capacitor.

512XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental

mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with

an external 24-MHz square wave derived from another clock source.

411XTALOUT Output N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental

mode crystal and 20-pF capacitor to GND. If an external clock is used to drive

XTALIN, leave this pin open.

545NC Output O No Connect.This pin must be left unconnected.

3340READY Output L READY is an output-only ready that gates external command reads and writes.

Active High.

3441INT#Output H INT# is an output-only external interrupt signal. Active Low.

3542SLOE Input I SLOE is an input-only output enable with programmable polarity (POLAR.4) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

3643FIFOADR2Input I FIFOADR2 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

3744FIFOADR0Input I FIFOADR0 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

3845FIFOADR1Input I FIFOADR1 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

3946PKTEND Input I PKTEND is an input-only packet end with programmable polarity (POLAR.5) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

4047FLAGD/C

CS#:I

FLAGD:O

I FLAGD is a programmable slave-FIFO output status flag signal. CS# is a master

chip select (default).

1825FD[0]I/O/Z I FD[0] is the bidirectional FIFO/Command data bus. 1926FD[1]I/O/Z I FD[1] is the bidirectional FIFO/Command data bus. 2027FD[2]I/O/Z I FD[2] is the bidirectional FIFO/Command data bus. 2128FD[3]I/O/Z I FD[3] is the bidirectional FIFO/Command data bus. 2229FD[4]I/O/Z I FD[4] is the bidirectional FIFO/Command data bus. 2330FD[5]I/O/Z I FD[5] is the bidirectional FIFO/Command data bus. 2431FD[6]I/O/Z I FD[6] is the bidirectional FIFO/Command data bus. 2532FD[7]I/O/Z I FD[7] is the bidirectional FIFO/Command data bus. 4552FD[8]I/O/Z I FD[8] is the bidirectional FIFO data bus.

4653FD[9]I/O/Z I FD[9] is the bidirectional FIFO data bus.

4754FD[10]I/O/Z I FD[10] is the bidirectional FIFO data bus.

4855FD[11]I/O/Z I FD[11] is the bidirectional FIFO data bus.

4956FD[12]I/O/Z I FD[12] is the bidirectional FIFO data bus.

501FD[13]I/O/Z I FD[13] is the bidirectional FIFO data bus.

512FD[14]I/O/Z I FD[14] is the bidirectional FIFO data bus.

523FD[15]I/O/Z I FD[15] is the bidirectional FIFO data bus.

18SLRD Input N/A SLRD is the input-only read strobe with programmable polarity (POLAR.3) for the

slave FIFOs connected to FD[7:0] or FD[15:0].

29SLWR Input N/A SLWR is the input-only write strobe with programmable polarity (POLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0].

2936FLAGA Output H FLAGA is a programmable slave-FIFO output status flag signal.Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.3037FLAGB Output H FLAGB is a programmable slave-FIFO output status flag signal.Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.3138FLAGC Output H FLAGC is a programmable slave-FIFO output status flag signal.Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.

IFCLK

I/O/Z

Interface Clock , used for synchronously clocking data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals. When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity.1421Reserved Input N/A Reserved . Must be connected to ground.

WAKEUP

Input

N/A

USB Wakeup . If the SX2 is in suspend, asserting this pin starts up the oscillator and interrupts the SX2 to allow it to exit the suspend mode. During normal

operation, holding WAKEUP asserted inhibits the SX2 chip from suspending. This pin has programmable polarity (POLAR.7).

1522SCL OD Z I 2C Clock . Connect to V CC with a 2.2K-10 KOhms resistor, even if no I 2C EEPROM is attached.

SDA

I 2C Data . Connect to V CC with a 2.2K-10 KOhms resistor, even if no I 2C EEPROM is attached.

556V CC Power N/A V CC . Connect to 3.3V power source.714V CC Power N/A V CC . Connect to 3.3V power source.1118V CC Power N/A V CC . Connect to 3.3V power source.1724V CC Power N/A V CC . Connect to 3.3V power source.2734V CC Power N/A V CC . Connect to 3.3V power source.3239V CC Power N/A V CC . Connect to 3.3V power source.4350V CC Power N/A V CC . Connect to 3.3V power source.534GND Ground N/A Connect to ground .567GND Ground N/A Connect to ground .1017GND Ground N/A Connect to ground .1219GND Ground N/A Connect to ground .2633GND Ground N/A Connect to ground .2835GND Ground N/A Connect to ground .41

GND

Ground

N/A

Connect to ground .

Table 6-1. SX2 Pin Definitions (continued)QFN Pin SSOP Pin Name Type Default Description

7.0 Register Summary

Table 7-1. SX2 Register Summary

Hex Size Name Description D7D6D5D4D3D2D1D0Default Access General Configuration

011IFCONFIG Interface Configuration IFCLKSRC3048MHZ IFCLKOE IFCLKPOL ASYNC STANDBY FLAGD/CS#DISCON11001001bbbbbbbb 021FLAGSAB FIFO FLAGA and FLAGB Assign-

ments

FLAGB3FLAGB2FLAGB1FLAGB0FLAGA3FLAGA2FLAGA1FLAGA000000000bbbbbbbb

031FLAGSCD FIFO FLAGC and FLAGD Assign-

ments

FLAGD3FLAGD2FLAGD1FLAGD0FLAGC3FLAGC2FLAGC1FLAGC000000000bbbbbbbb 041POLAR FIFO polarities WUPOL0PKTEND SLOE SLRD SLWR EF FF00000000bbbrrrbb 051REVID Chip Revision Major Major Major Major minor minor minor minor xxxxxxxx rrrrrrrr Endpoint Configuration[8]

061EP2CFG Endpoint 2 Configuration VALID dir TYPE1TYPE0SIZE STALL BUF1BUF010100010bbbbbbbb 071EP4CFG Endpoint 4 Configuration VALID dir TYPE1TYPE00STALL0010100000bbbbrbrr 081EP6CFG Endpoint 6 Configuration VALID dir TYPE1TYPE0SIZE STALL BUF1BUF011100010bbbbbbbb 091EP8CFG Endpoint 8 Configuration VALID dir TYPE1TYPE00STALL0011100000bbbbrbrr 0A1EP2PKTLENH Endpoint 2 Packet Length H INFM1OEP1ZEROLEN WORD-

WIDE

0PL10PL9PL800110010bbbbbbbb 0B1EP2PKTLENL Endpoint 2 Packet Length L (IN only)PL7PL6PL5PL4PL3PL2PL1PL000000000bbbbbbbb 0C1EP4PKTLENH Endpoint 4 Packet Length H INFM1OEP1ZEROLEN WORD-

WIDE

00PL9PL800110010bbbbbbbb 0D1EP4PKTLENL Endpoint 4 Packet Length L (IN only)PL7PL6PL5PL4PL3PL2PL1PL000000000bbbbbbbb 0E1EP6PKTLENH Endpoint 6 Packet Length H INFM1OEP1ZEROLEN WORD-

WIDE

0PL10PL9PL800110010bbbbbbbb 0F1EP6PKTLENL Endpoint 6 Packet Length L (IN only)PL7PL6PL5PL4PL3PL2PL1PL000000000bbbbbbbb 101EP8PKTLENH Endpoint 8 Packet Length H INFM1OEP1ZEROLEN WORD-

WIDE

00PL9PL800110010bbbbbbbb 111EP8PKTLENL Endpoint 8 Packet Length L (IN only)PL7PL6PL5PL4PL3PL2PL1PL000000000bbbbbbbb

121EP2PFH EP2 Programmable Flag H DECIS PKTSTAT IN: PKTS[2]

OUT:PFC12IN: PKTS[1]

OUT:PFC11

IN: PKTS[0]

OUT:PFC10

0PFC9PFC810001000bbbbbbbb

131EP2PFL EP2 Programmable Flag L PFC7PFC6PFC5PFC4PFC3PFC2PFC1PFC000000000bbbbbbbb

141EP4PFH EP4 Programmable Flag H DECIS PKTSTAT0IN: PKTS[1]

OUT:PFC10IN: PKTS[0]

OUT:PFC9

00PFC810001000bbbbbbbb

151EP4PFL EP4 Programmable Flag L PFC7PFC6PFC5PFC4PFC3PFC2PFC1PFC000000000bbbbbbbb

161EP6PFH EP6 Programmable Flag H DECIS PKTSTAT IN: PKTS[2]

OUT:PFC12IN: PKTS[1]

OUT:PFC11

IN: PKTS[0]

OUT:PFC10

0PFC9PFC800001000bbbbbbbb

171EP6PFL EP6 Programmable Flag L PFC7PFC6PFC5PFC4PFC3PFC2PFC1PFC000000000bbbbbbbb

181EP8PFH EP8 Programmable Flag H DECIS PKTSTAT0IN: PKTS[1]

OUT:PFC10IN: PKTS[0]

OUT:PFC9

00PFC800001000bbbbbbbb

191EP8PFL EP8 Programmable Flag L PFC7PFC6PFC5PFC4PFC3PFC2PFC1PFC000000000bbbbbbbb 1A1EP2ISOINPKTS EP2 (if ISO) IN Packets per frame (1-3)000000INPPF1INPPF000000001bbbbbbbb 1B1EP4ISOINPKTS EP4 (if ISO) IN Packets per frame (1-3)000000INPPF1INPPF000000001bbbbbbbb 1C1EP6ISOINPKTS EP6 (if ISO) IN Packets per frame (1-3)000000INPPF1INPPF000000001bbbbbbbb 1D1EP8ISOINPKTS EP8 (if ISO) IN Packets per frame (1-3)000000INPPF1INPPF000000001bbbbbbbb FLAGS

1E1EP24FLAGS Endpoints 2,4 FIFO Flags0EP4PF EP4EF EP4FF0EP2PF EP2EF EP2FF00100010rrrrrrrr 1F1EP68FLAGS Endpoints 6,8 FIFO Flags0EP8PF EP8EF EP8FF0EP6PF EP6EF EP6FF01100110rrrrrrrr INPKTEND/FLUSH[9]

201INPK-

TEND/FLUSH Force Packet End / Flush FIFOs FIFO8FIFO6FIFO4FIFO2EP3EP2EP1EP000000000wwwwww-

USB Configuration

2A1USBFRAMEH USB Frame count H00000FC10FC9FC8xxxxxxxx rrrrrrrr

2B1USBFRAMEL USB Frame count L FC7FC6FC5FC4FC3FC2FC1FC0xxxxxxxx rrrrrrrr

2C1MICROFRAME Microframe count, 0-700000MF2MF1MF0xxxxxxxx rrrrrrrr

2D1FNADDR USB Function address HSGRANT FA6FA5FA4FA3FA2FA1FA000000000rrrrrrrr Interrupts

2E1INTENABLE Interrupt Enable SETUP EP0BUF FLAGS11ENUMOK BUSACTIVITY READY11111111bbbbbbbb Descriptor

30500DESC Descriptor RAM d7d6d5d4d3d2d1d0xxxxxxxx wwwwww-

ww Endpoint 0

3164EP0BUF Endpoint 0 Buffer d7d6d5d4d3d2d1d0xxxxxxxx bbbbbbbb 328/1SETUP Endpoint 0 Set-up Data / Stall d7d6d5d4d3d2d1d0xxxxxxxx bbbbbbbb 331EP0BC Endpoint 0 Byte Count d7d6d5d4d3d2d1d0xxxxxxxx bbbbbbbb Un-Indexed Register control

3A1Un-Indexed Register Low Byte pointer a7a6a5a4a3a2a1a0

3B1Un-Indexed Register High Byte point-

a7a6a5a4a3a2a1a0

3C1Un-Indexed Register Data d7d6d5d4d3d2d1d0

Address Un-Indexed Registers in XDATA Space

0xE609FIFOPINPOLAR FIFO Interface Pins Polarity00PKTEND SLOE SLRD SLWR EF FF00000000rrbbbbbb 0xE683TOGCTL Data T oggle Control Q S R IO EP3EP2EP1EP0xxxxxxxx rbbbbbbb Notes:

8.Please note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your applications need the ability to

change endpoint configurations after the device has already enumerated with a specific configuration, please expect some delay in being able to access the FIFOs after changing the configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 μs measured from the time the READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic change of endpoint configuration registers.

9.Please note that the SX2 was not designed to support dynamic modification of the INPKTEND/FLUSH register. If your applications need the ability to change

endpoint configurations or access the INPKTEND register after the device has already enumerated with a specific configuration, please expect some delay in being able to access the FIFOs after changing this register. After writing to INPKTEND/FLUSH, you must wait for at least 85 μs measured from the time the READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic change of endpoint configuration registers

7.1IFCONFIG Register 0x01

7.1.1Bit 7: IFCLKSRC

This bit selects the clock source for the FIFOs. If IFCLKSRC = 0, the external clock on the IFCLK pin is selected. If IFCLKSRC =1 (default), an internal 30 or 48 MHz clock is used.

7.1.2Bit 6: 3048MHZ

This bit selects the internal FIFO clock frequency. If 3048MHZ = 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1 (default), the internal clock frequency is 48 MHz.

7.1.3Bit 5: IFCLKOE

This bit selects if the IFCLK pin is driven. If IFCLKOE = 0 (default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK pin is driven.

7.1.4Bit 4: IFCLKPOL

This bit controls the polarity of the IFCLK signal.

?When IFCLKPOL=0, the clock has the polarity shown in all the timing diagrams in this data sheet (rising edge is the activating edge).

?When IFCLKPOL=1, the clock is inverted (in some cases may help with satisfying data set-up times).

7.1.5Bit 3: ASYNC

This bit controls whether the FIFO interface is synchronous or asynchronous. When ASYNC = 0, the FIFOs operate synchro-nously. In synchronous mode, a clock is supplied either inter-nally or externally on the IFCLK pin, and the FIFO control signals function as read and write enable signals for the clock signal.When ASYNC = 1 (default), the FIFOs operate asynchro-nously. No clock signal input to IFCLK is required, and the FIFO control signals function directly as read and write strobes.

7.1.6Bit 2: STANDBY

This bit instructs the SX2 to enter a low-power mode. When STANDBY=1, the SX2 will enter a low-power mode by turning off its oscillator. The external master should write this bit after it receives a bus activity interrupt (indicating that the host has signaled a USB suspend condition). If SX2 is disconnected from the USB bus, the external master can write this bit at any time to save power. Once suspended, the SX2 is awakened either by resumption of USB bus activity or by assertion of its WAKEUP pin.

7.1.7Bit 1: FLAGD/CS#

This bit controls the function of the FLAGD/CS# pin. When FLAGD/CS# = 0 (default), the pin operates as a slave chip select. If FLAGD/CS# = 1, the pin operates as FLAGD.

7.1.8Bit 0: DISCON

This bit controls whether the internal pull-up resistor connected to D+ is pulled high or floating. When DISCON = 1 (default), the pull-up resistor is floating simulating a USB unplug. When DISCON=0, the pull-up resistor is pulled high signaling a USB connection.

7.2FLAGSAB/FLAGSCD Registers 0x02/0x03 The SX2 has four FIFO flags output pins: FLAGA, FLAGB, FLAGC, FLAGD.

IFCONFIG0x01 Bit #76543210

Bit Name IFCLKSRC3048MHZ IFCLKOE IFCLKPOL ASYNC STANDBY FLAGD/CS#DISCON Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default11001001

FLAGSAB0x02 Bit #76543210

Bit Name FLAGB3FLAGB2FLAGB1FLAGB0FLAGA3FLAGA2FLAGA1FLAGA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00000000

FLAGSCD0x03 Bit #76543210

Bit Name FLAGD3FLAGD2FLAGD1FLAGD0FLAGC3FLAGC2FLAGC1FLAGC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00000000

These flags can be programmed to represent various FIFO flags using four select bits for each FIFO. The 4-bit coding for all four flags is the same, as shown in Table7-2.

For the default (0000) selection, the four FIFO flags are fixed-function as shown in the first table entry; the input pins FIFOADR[2:0] select to which of the four FIFOs the flags correspond. These pins are decoded as shown in Table3-3. The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four flag outputs FLAGA-FLAGD to correspond to any flag-Programmable, Full, or Empty-from any of the four endpoint FIFOs. This allows each flag to be assigned to any of the four FIFOs, including those not currently selected by the FIFOADR [2:0] pins. For example, the external master could be filling the EP2IN FIFO with data while also checking the empty flag for the EP4OUT FIFO.

7.3POLAR Register 0x04

This register controls the polarities of FIFO pin signals and the WAKEUP pin.7.3.1Bit 7: WUPOL

This flag sets the polarity of the WAKEUP pin. If WUPOL = 0 (default), the polarity is active LOW. If WUPOL=1, the polarity is active HIGH.

7.3.2Bit 5: PKTEND

This flag selects the polarity of the PKTEND pin. If PKTEND = 0 (default), the polarity is active LOW. If PKTEND = 1, the polarity is active HIGH.

7.3.3Bit 4: SLOE

This flag selects the polarity of the SLOE pin. If SLOE = 0 (default), the polarity is active LOW. If SLOE = 1, the polarity is active HIGH. This bit can only be changed by using the EEPROM configuration load.

7.3.4Bit 3: SLRD

This flag selects the polarity of the SLRD pin. If SLRD = 0 (default), the polarity is active LOW. If SLRD = 1, the polarity is active HIGH. This bit can only be changed by using the EEPROM configuration load.

7.3.5SLWR Bit 2

This flag selects the polarity of the SLWR pin. If SLWR = 0 (default), the polarity is active LOW. If SLWR = 1, the polarity is active HIGH. This bit can only be changed by using the EEPROM configuration load.

7.3.6EF Bit 1

This flag selects the polarity of the EF pin (FLAGA/B/C/D). If EF = 0 (default), the EF pin is pulled low when the FIFO is empty. If EF = 1, the EF pin is pulled HIGH when the FIFO is empty.

7.3.7FF Bit 0

This flag selects the polarity of the FF pin (FLAGA/B/C/D). If FF = 0 (default), the FF pin is pulled low when the FIFO is full. If FF=1, the FF pin is pulled HIGH when the FIFO is full. Note that bits 2(SLWR), 3(SLRD) and 4 (SLOE) are READ only bits and cannot be set by the external master or the EEPROM. On power-up, these bits are set to active low polarity. In order to change the polarity after the device is powered-up, the external master must access the previously undocumented (un-indexed) SX2 register located at XDATA space at 0xE609. This register has exact same bit definition as the POLAR register except that bits 2, 3 and 4 defined as SLWR, SLRD and SLOE respectively are Read/Write bits. Following is the sequence of events that the master should perform for setting this register to 0x1C (setting bits 4, 3, and 2):

1.Send Low Byte of the Register (0x09)

https://www.wendangku.net/doc/b58939530.html,mand address write of address 0x3A

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the Low Byte of

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the Low Byte of

2.Send High Byte of the Register (0xE6)

https://www.wendangku.net/doc/b58939530.html,mand address write of address 0x3B

Table 7-2. FIFO Flag 4-bit Coding

FLAGx3FLAGx2FLAGx1FLAGx0Pin Function 0000FLAGA=PF,

FLAGB = FF,

FLAGC = EF,

FLAGD = CS#

(actual FIFO is

selected by

FIFOADR[2:0]

pins)

0001Reserved

0010Reserved

0011Reserved

0100EP2PF

0101EP4PF

0110EP6PF

0111EP8PF

1000EP2EF

1001EP4EF

1010EP6EF

1011EP8EF

1100EP2FF

1101EP4FF

1110EP6FF

1111EP8FF

POLAR0x04 Bit #76543210 Bit

Name

WUPOL0PKTEND SLOE SLRD SLWR EF FF

Read/W

rite

R/W R/W R/W R R R R/W R/W Default00000000

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the High Byte of

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the High Byte of

3.Send the actual value to write to the register Register (in

this case 0x1C)

https://www.wendangku.net/doc/b58939530.html,mand address write of address 0x3C

https://www.wendangku.net/doc/b58939530.html,mand data write of upper nibble of the register value

(0x01)

https://www.wendangku.net/doc/b58939530.html,mand data write of lower nibble of the register value

(0x0C)

In order to avoid altering any other bits of the FIFOPINPOLAR register (0xE609) inadvertently, the external master must do a read (from POLAR register), modify the value to set/clear appropriate bits and write the modified value to FIFOPIN-POLAR register. The external master may read from the POLAR register using the command read protocol as stated in Section 3.7.8. Modify the value with the appropriate bit set to change the polarity as needed and write this modified value to the FIFOPINPOLAR register.

7.4REVID Register 0x05

These register bits define the silicon revision.

The upper nibble is the major revision. The lower nibble is the minor revision. For example: if REVID = 0x11, then the silicon revision is 1.1.

7.5EPxCFG Register 0x06–0x09

These registers configure the large, data-handling SX2 endpoints, EP2, 4, 6, and 8. Figure3-1 shows the configu-ration choices for these endpoints. Shaded blocks group endpoint buffers for double-, triple-, or quad-buffering. The endpoint direction is set independently—any shaded block can have any direction.7.5.1Bit 7: VALID

The external master sets VALID = 1 to activate an endpoint, and VALID = 0 to deactivate it. All SX2 endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. (Note: when setting VALID=0, use default values for all other bits.)

7.5.2Bit 6: DIR

0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for EP6/8 are DIR = 1, IN.

7.5.3Bit [5,4]: TYPE1, TYPE0

These bits define the endpoint type, as shown in Table7-3. The TYPE bits apply to all of the endpoint configuration registers. All SX2 endpoints except EP0 default to BULK.

7.5.4Bit 3: SIZE

0 = 512 bytes (default), 1 = 1024 bytes.

Endpoints 4 and 8 can only be 512 bytes and is a read only bit. The size of endpoints 2 and 6 is selectable.

7.5.5Bit 2: STALL

Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the external master sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or NAK. The Get Status-Endpoint Request returns the STALL state for the endpoint indicated in byte 4 of the request. Note that bit 7 of the endpoint number EP (byte 4) specifies direction.

7.5.6Bit [1,0]: BUF1, BUF0

For EP2 and EP6 the depth of endpoint buffering is selected via BUF1:0, as shown in Table7-4. For EP4 and EP8 the buffer is internally set to double buffered and are read only bits.

7.6EPxPKTLENH/L Registers 0x0A–0x11

The external master can use these registers to set smaller packet sizes than the physical buffer size (refer to the previ-ously described EPxCFG registers). The default packet size is 512 bytes for all endpoints. Note that EP2 and EP6 can have maximum sizes of 1024 bytes, and EP4 and EP8 can have maximum sizes of 512 bytes, to be consistent with the endpoint structure.

REVID0x05 Bit #76543210

Bit

Name

Major Major Major Major Minor Minor Minor Minor

Read/

Write

R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X

EPxCFG0x06, 0x08 Bit #76543210

Bit

Name

VALID DIR TYPE1TYPE0 SIZE STALL BUF1BUF0

Read/

Write

R/W R/W R/W R/W R/W R/W R/W R/W Default10100010 EPxCFG 0x07, 0x09 Bit #76543210

Bit

Name

VALID DIR TYPE1TYPE0 SIZE STALL BUF1BUF0

Read/W

rite

R/W R/W R/W R/W R R/W R R Default10100010Table 7-3. Endpoint Type

TYPE1TYPE0Endpoint Type 00Invalid

01Isochronous

10Bulk (Default)

11Interrupt

Table 7-4. Endpoint Buffering

BUF1BUF0Buffering

00Quad

01Invalid[10]

10Double

11Triple

Note:

10.Setting the endpoint buffering to invalid causes improper buffer allocation

In addition, the EPxPKTLENH register has four other endpoint configuration bits.

7.6.1Bit 7: INFM1 EPxPKTLENH.7

When the external master sets INFM = 1 in an endpoint config-uration register, the FIFO flags for that endpoint become valid one sample earlier than when the full condition occurs. These bits take effect only when the FIFOs are operating synchro-nously according to an internally or externally supplied clock. Having the FIFO flag indications one sample early simplifies some synchronous interfaces. This applies only to IN endpoints. Default is INFM1 = 0.

7.6.2Bit 6: OEP1 EPxPKTLENH.6

When the external master sets an OEP = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid one sample earlier than when the empty condition occurs. These bits take effect only when the FIFOs are operating synchronously according to an internally or exter-nally supplied clock. Having the FIFO flag indications one sample early simplifies some synchronous interfaces. This applies only to OUT endpoints. Default is OEP1 = 0.

7.6.3Bit 5: ZEROLEN EPxPKTLENH.5

When ZEROLEN = 1 (default), a zero length packet will be sent when the PKTEND pin is asserted and there are no bytes in the current packet. If ZEROLEN = 0, then a zero length packet will not be sent under these conditions.

7.6.4Bit 4: WORDWIDE EPxPKTLENH.4

This bit controls whether the data interface is 8 or 16 bits wide. If WORDWIDE = 0, the data interface is eight bits wide, and FD[15:8] have no function. If WORDWIDE = 1 (default), the data interface is 16 bits wide.

7.6.5Bit [2..0]: PL[X:0] Packet Length Bits

The default packet size is 512 bytes for all endpoints.7.7EPxPFH/L Registers 0x12–0x19

The Programmable Flag registers control when the PF goes active for each of the four endpoint FIFOs: EP2, EP4, EP6, and EP8. The EPxPFH/L fields are interpreted differently for the high speed operation and full speed operation and for OUT and IN endpoints.

Following is the register bit definition for high speed operation and for full speed operation (when endpoint is configured as an isochronous endpoint).

Following is the bit definition for the same register when the device is operating at full speed and the endpoint is not configured as isochronous endpoint.

EPxPKTLENL0x0B, 0x0D,

0x0F, 0x11 Bit #76543210 Bit Name PL7PL6PL5PL4 PL3PL2 PL1PL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00000000 EP2PKTLENH,

EP6PKTLENH

0x0A, 0x0E Bit #76543210

Bit Name INFM1OEP1ZERO

LEN WORD

WIDE

0PL10 PL9PL8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00110010

EP4PKTLENH,

EP8PKTLENH

0x0C, 0x10 Bit #76543210

Bit Name INFM1OEP1ZERO

LEN WORD

WIDE

00PL9PL8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00110010Full Speed ISO and High Speed Mode: EP2PFL,

EP4PFL, EP6PFL, EP8PFL

0x13, 0x15,

0x17, 0x19 Bit #76543210 Bit Name PFC7PFC6PFC5PFC4PFC3PFC2PFC1PFC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00000000

Full Speed ISO and High Speed Mode:

EP4PFH, EP8PFH

0x14, 0x18 Bit #76543210

Bit Name DECIS PKTSTAT0IN:

PKTS[1]

OUT:

PFC10

IN:

PKTS[0]

OUT:

PFC9

00PFC8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00001000

Full Speed ISO and High Speed Mode:

EP2PFH, EP6PFH

0x12, 0x16

Bit #76543210 Bit Name DECIS PKTSTAT IN:

PKTS[2]

OUT:

PFC12

IN:

PKTS[1]

OUT:

PFC11

IN:

PKTS[0]

OUT:

PFC10

0PFC9PFC8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default10001000

Full Speed Non-ISO Mode: EP2PFL,

EP4PFL, EP6PFL, EP8PFL

0x13, 0x15,

0x17, 0x19 Bit #76543210 Bit Name IN:

PKTS[1]

OUT:

PFC7

IN:

PKTS[0]

OUT:

PFC6

PFC5PFC4PFC3PFC2PFC1PFC0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00000000

Full Speed Non-ISO Mode:

EP2PFH, EP6PFH

0x12, 0x16 Bit #76543210

Bit Name DECIS PKTSTAT OUT:

PFC12

OUT:

PFC11

OUT:

PFC10

0PFC9IN:

PKTS[2]

OUT:

PFC8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default10001000

7.7.1DECIS: EPxPFH.7

If DECIS = 0, then PF goes high when the byte count i is equal to or less than what is defined in the PF registers. If DECIS = 1 (default), then PF goes high when the byte count equal to or greater than what is set in the PF register. For OUT endpoints, the byte count is the total number of bytes in the FIFO that are available to the external master. For IN endpoints, the byte count is determined by the PKSTAT bit.

7.7.2PKSTAT: EPxPFH.6

For IN endpoints, the PF can apply to either the entire FIFO, comprising multiple packets, or only to the current packet being filled. If PKTSTAT = 0 (default), the PF refers to the entire IN endpoint FIFO. If PKTSTAT = 1, the PF refers to the number of bytes in the current packet.

7.7.3IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3] These three bits have a different meaning, depending on whether this is an IN or OUT endpoint.

7.7.3.1IN Endpoints

If IN endpoint, the meaning of this EPxPFH[5:3] bits depend on the PKTSTAT bit setting. When PKTSTAT = 0 (default), the PF considers when there are PKTS packets plus PFC bytes in the FIFO. PKTS[2:0] determines how many packets are considered, according to Table7-5.

When PKTSTAT = 1, the PF considers when there are PFC bytes in the FIFO, no matter how many packets are in the FIFO. The PKTS[2:0] bits are ignored.

7.7.3.2OUT Endpoints

The PF considers when there are PFC bytes in the FIFO regardless of the PKTSTAT bit setting.7.8EPxISOINPKTS Registers 0x1A–0x1D

For ISOCHRONOUS IN endpoints only, these registers determine the number of packets per frame (only one per frame for full-speed mode) or microframe (up to three per microframe for high-speed mode), according to the following table.

7.9EPxxFLAGS Registers 0x1E–0x1F

The EPxxFLAGS provide an alternate way of checking the status of the endpoint FIFO flags. If enabled, the SX2 can interrupt the external master when a flag is asserted, and the external master can read these two registers to determine the state of the FIFO flags. If the INFM1 and/or OEP1 bits are set, then the EPxEF and EPxFF bits are actually empty +1 and full –1.

7.9.1EPxPF Bit 6, Bit 2

This bit is the current state of endpoint x’s programmable flag.

7.9.2EPxEF Bit 5, Bit 1

This bit is the current state of endpoint x’s empty flag. EPxEF = 1 if the endpoint is empty.

7.9.3EPxFF Bit 4, Bit 0

This bit is the current state of endpoint x’s full flag. EPxFF = 1 if the endpoint is full.

Full Speed Non-ISO Mode:

EP4PFH, EP8PFH

0x14, 0x18 Bit #76543210

Bit Name DECIS PKT-

STAT 0OUT:

PFC10

OUT:

PFC9

00PFC8

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00001000

PKTSTAT PF applies to EPnPFH:L format 0Number of committed packets

+ current packet bytes

PKTS[] and PFC[] 1Current packet bytes only PFC[ ]

Table 7-5. PKTS Bits

PKTS2PKTS1PKTS0Number of Packets 0000

0011

0102

0113

1004

EP2ISOINOKTS, EP4ISOINPKTS,

EP6ISOINPKTS, EP8ISOINPKTS

0x1A, 0x1B,

0x1C, 0x1D Bit #76543210

Bit Name00000INPPF2INPPF1INPPF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00000001

Table 7-6. EPxISOINPKTS

INPPF1INPPF0Packets

00Invalid

01 1 (default)

102

113

EP24FLAGS0x1E Bit #76543210 Bit Name0EP4PF EP4EF EP4FF0EP2PF EP2EF EP2FF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00100010 EP68FLAGS0x1F Bit #76543210 Bit Name0EP8PF EP8EF EP8FF0EP6PF EP6EF EP6FF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default00100010

7.10INPKTEND/FLUSH Register 0x20

This register allows the external master to duplicate the function of the PKTEND pin. The register also allows the external master to selectively flush endpoint FIFO buffers.

Bit [4..7]: FIFOx

These bits allows the external master to selectively flush any or all of the endpoint FIFOs. By writing the desired endpoint FIFO bit, SX2 logic flushes the selected FIFO. For example setting bit 7 flushes endpoint 8 FIFO.

Bit [3..0]: EPx

These bits are is used only for IN transfers. By writing the desired endpoint number (2,4,6 or 8), SX2 logic automatically commits an IN buffer to the USB host. For example, for committing a packet through endpoint 6, set the lower nibble to 6: set bits 1 and 2 high.

7.11USBFRAMEH/L Registers 0x2A, 0x2B

Every millisecond, the USB host sends an SOF token indicating “Start Of Frame,” along with an 11-bit incrementing frame count. The SX2 copies the frame count into these registers at every SOF.

One use of the frame count is to respond to the USB SYNC_FRAME Request. If the SX2 detects a missing or garbled SOF, the SX2 generates an internal SOF and incre-ments USBFRAMEL–USBRAMEH.

7.12MICROFRAME Registers 0x2C MICROFRAME contains a count 0–7 that indicates which of

the 125 microsecond microframes last occurred.

This register is active only when SX2 is operating in high-speed mode (480 Mbits/sec).7.13FNADDR Register 0x2D

During the USB enumeration process, the host sends a device a unique 7-bit address that the SX2 copies into this register. There is normally no reason for the external master to know its USB device address because the SX2 automatically responds only to its assigned address.

Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high speed. Set to 0 if the SX2 enumerated at full speed.

Bit[6..0]: Address set by the host.

7.14INTENABLE Register 0x2E

This register is used to enable/disable the various interrupt sources, and by default all interrupts are enabled.

7.14.1SETUP Bit 7

Setting this bit to a 1 enables an interrupt when a set-up packet is received from the USB host.

7.14.2EP0BUF Bit 6

Setting this bit to a 1 enables an interrupt when the Endpoint 0 buffer becomes available.

7.14.3FLAGS Bit 5

Setting this bit to a 1 enables an interrupt when an OUT endpoint FIFO’s state transitions from empty to not-empty. 7.14.4ENUMOK Bit 2

Setting this bit to a 1 enables an interrupt when SX2 enumer-ation is complete.

7.14.5BUSACTIVITY Bit 1

Setting this bit to a 1 enables an interrupt when the SX2 detects an absence or presence of bus activity.

7.14.6READY Bit 0

Setting this bit to a 1 enables an interrupt when the SX2 has powered on and performed an internal self-test.

7.15DESC Register 0x30

This register address is used to write the 500-byte descriptor RAM. The external master writes two bytes (four command data transfers) to this address corresponding to the length of the descriptor or VID/PID/DID data to be written. The external master then consecutively writes that number of bytes into the

INPKTEND/FLUSH0x20

Bit #76543210 Bit Name FIFO8FIFO6FIFO4FIFO2EP3EP2EP1EP0 Read/Write W W W W W W W W Default00000000

USBFRAMEH0x2A Bit #76543210 Bit Name00000FC10FC9FC8 Read/Write R R R R R R R R Default X X X X X X X x

USBFRAMEL0x2B Bit #76543210 Bit Name FC7FC6FC5FC4FC3FC2FC1FC0 Read/Write R R R R R R R R Default X X X X X X X X

MICROFRAME0x2C Bit #76543210 Bit Name00000MF2MF1MF0 Read/Write R R R R R R R R Default X X X X X X X x FNADDR0x2D Bit #76543210 Bit Name HSGRANT FA6FA5FA4FA3FA2FA1FA0 Read/Write R R R R R R R R Default00000000

INTENABLE0x2E Bit #76543210

Bit Name SETUP EP0

BUF

FLAGS1 1ENUM

BUS

ACTIVITY

READY Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default11111111