CY7C1069BV33-10ZC中文资料

16-Mbit (2M x 8) Static RAM

CY7C1069BV33

Features

?High

speed —t AA = 10 ns ?Low active power —990 mW (max.)

?Operating voltages of 3.3 ± 0.3V ?2.0V data retention

?Automatic power-down when deselected ?TTL-compatible inputs and outputs

?Available in Pb-free and non Pb-free 54-pin TSOP II package

Functional Description

The CY7C1069BV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE LOW) and Write Enable (WE) inputs LOW.

Reading from the device is accomplished by enabling the chip (CE LOW) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes.

The input/output pins (I/O 0 through I/O 7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW and WE LOW).

The CY7C1069BV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout.

Logic Block Diagram

1516A 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODER

R O W D E C O D E R

S E N S E A M P S

INPUT BUFFER

2M x 8ARRAY

A 0A 12A 14A 13A A A 17A 18A 10A 11I/O 0–I/O 7

OE WE CE

A 9

A 19A 20

WE 12345678910111431323635343337403938121341434216152930A 5A 6A 7A 8A 0A 1OE V SS A 17I/O 7A 2I/O 0I/O 1A 3A 41817201927

28

252622212324I/O 2I/O 3A 16A 15V CC I/O 6NC I/O 5I/O 4A 14A 13A 12A 11A 9A 104446454750494851535254V SS V CC A 19A 18V CC V CC

V SS V SS

NC V CC V SS NC NC NC NC

NC

NC

NC NC A 20CE DNU/V CC

DNU/V SS

54-pin TSOP II (Top View)

Pin Configurations [1, 2]

Notes:

1.DNU/V CC Pin (#16) has to be left floating or connected to V CC and DNU/V SS Pin (#40) has to be left floating or connected to V SS to ensure proper application.

2.NC - No Connect Pins are not connected to the die.

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature .................................–65°C to +150°C Ambient Temperature with

Power Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[3]....–0.5V to +4.6V DC Voltage Applied to Outputs

in High-Z State[3]....................................–0.5V to V CC + 0.5V DC Input Voltage[3]................................–0.5V to V CC + 0.5V Current into Outputs (LOW).........................................20 mA

Selection Guide

–10–12Unit Maximum Access Time1012ns Maximum Operating Current Commercial275260mA

Industrial275260

Maximum CMOS Standby Current Commercial/Industrial5050mA

Operating Range

Range Ambient Temperature V CC

Commercial0°C to +70°C 3.3V ± 0.3V

Industrial–40°C to +85°C

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

–10–12

Unit Min.Max.Min.Max.

V OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.4 2.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA0.40.4V V IH Input HIGH Voltage 2.0V CC + 0.3 2.0V CC + 0.3V V IL Input LOW Voltage[3]–0.30.8–0.30.8V I IX Input Leakage Current GND < V I < V CC–1+1–1+1μA I OZ Output Leakage Current GND < V OUT < V CC, Output Disabled–1+1–1+1μA

I CC V CC Operating

Supply Current V CC = Max.,

f = f MAX = 1/t RC

Comm’l275260mA

Ind’l275260mA

I SB1Automatic CE

Power-down Current

—TTL Inputs Max. V CC, CE > V IH

V IN > V IH or

V IN < V IL, f = f MAX

7070mA

I SB2Automatic CE

Power-down Current

—CMOS Inputs Max. V CC,

CE > V CC – 0.3V,

V IN > V CC – 0.3V,

or V IN < 0.3V, f = 0

Comm’l/

Ind’l

5050mA

Capacitance[4]

Parameter Description Test Conditions Max.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V6pF

C OUT I/O Capacitance8pF Thermal Resistance[4]

Parameter Description Test Conditions TSOP-II Unit

ΘJA Thermal Resistance (Junction to Ambient)Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51.49.95°C/W

ΘJC Thermal Resistance (Junction to Case) 3.34°C/W Notes:

3.V IL (min.) = –2.0V and V IH(max) = V CC + 0.5V for pulse durations of less than 20 ns.

4.Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms [5]

AC Switching Characteristics Over the Operating Range [6]

Parameter Description

–10

–12

Unit

Min.

Max.

Min.

Max.

Read Cycle t power V CC (typical) to the First Access [7]11ms t RC Read Cycle Time 10

12

ns t AA Address to Data Valid

10

12

ns t OHA Data Hold from Address Change 3

3

ns t ACE CE LOW to Data Valid 1012ns t DOE OE LOW to Data Valid 5

6

ns t LZOE OE LOW to Low-Z [8]1

1

ns t HZOE OE HIGH to High-Z [8]5

6

ns t LZCE CE LOW to Low-Z [8]3

3

ns t HZCE CE to High-Z [8]5

6

ns t PU CE to Power-up [9]0

ns t PD

CE to Power-down [9]

10

12

ns

Write Cycle [10, 11]t WC Write Cycle Time 1012ns t SCE CE to Write End

78ns t AW Address Set-up to Write End 78ns t HA Address Hold from Write End 00ns t SA Address Set-up to Write Start 00ns t PWE WE Pulse Width 78ns t SD Data Set-up to Write End 5.56ns t HD Data Hold from Write End 00ns t LZWE WE HIGH to Low-Z [8]3

3

ns t HZWE

WE LOW to High-Z [8]

5

6

ns

Notes:

5.Valid SRAM operation does not occur until the power supplies have reached the minimum operating V DD (3.0V). As soon as 1ms (T power ) after reaching the minimum operating V DD , normal SRAM operation can begin including reduction in V DD to the data retention (V CCDR , 2.0V) voltage.

6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and transmission line loads. T est conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.

7.t POWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.

8.t HZOE , t HZSCE , t HZWE and t LZOE , t LZCE , and t LZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.

9.These parameters are guaranteed by design and are not tested.

10.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of

these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.11.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .

90%10%

3.3V

GND

90%10%

All input pulses 3.3V OUTPUT 5 pF*

*Including jig and scope

(a)

(b)

R1 317?

R2351?

Rise time > 1V/ns

Fall time: > 1V/ns

(c)

OUTPUT

50?

Z 0= 50?

V TH = 1.5V

30 pF**Capacitive Load consists of all

components of the test environment

Data Retention Waveform

Switching Waveforms

Read Cycle No. 1[12, 13]

Read Cycle No. 2 (OE Controlled)[13, 14]

Notes:

12.Device is continuously selected. CE = V IL .13.WE is HIGH for Read cycle.

14.Address valid prior to or coincident with CE transition LOW.

3.0V 3.0V t CDR

V DR >2V

DATA RETENTION MODE

t R

CE

V CC PREVIOUS DATA VALID

DATA VALID

t RC

t AA

t OHA

ADDRESS

DATA OUT

50%

50%

DATA VALID

t RC

t ASCE

t DOE t LZOE

t LZSCE t PU

HIGH IMPEDANCE

t HZOE

t PD

HIGH OE

CE

IMPEDANCE

ADDRESS

DATA OUT V CC SUPPLY t HZSCE

CURRENT

I CC I SB

Write Cycle No. 1 (CE Controlled)[15, 16]

Write Cycle No. 2 (WE Controlled, OE LOW)[15, 16]

Truth Table

CE OE WE I/O 0–I/O 7Mode

Power

H X X High-Z Power-down Standby (I SB )L L H Data Out Read Active (I CC )L X L Data In Write

Active (I CC )L

H

H

High-Z

Selected, Outputs Disabled

Active (I CC )

Notes:

15.Data I/O is high-impedance if OE = V IH .

16.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Switching Waveforms (continued)

t HD

t SD

t SCE

t SA t HA

t AW

t PWE

t WC

BW

DATAI/O

ADDRESS

CE

WE

t t HD

t SD

t SCE

t HA

t AW

t PWE

t WC

DATA I/O

ADDRESS

CE

WE

t SA

t LZWE

t HZWE

Document #: 38-05694 Rev. *B Page 6 of 7

Package Diagram

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Ordering Information

Speed (ns)Ordering Code Package Diagram Package Type

Operating Range 10

CY7C1069BV33-10ZC 51-85160

54-pin TSOP II

Commercial CY7C1069BV33-10ZXC 54-pin TSOP II (Pb-free)CY7C1069BV33-10ZI 54-pin TSOP II

Industrial CY7C1069BV33-10ZXI 54-pin TSOP II (Pb-free)12

CY7C1069BV33-12ZC 54-pin TSOP II

Commercial CY7C1069BV33-12ZXC 54-pin TSOP II (Pb-free)CY7C1069BV33-12ZI 54-pin TSOP II

Industrial

CY7C1069BV33-12ZXI

54-pin TSOP II (Pb-free)

51-85160-**

54-pin TSOP II (51-85160)

Document History Page

Document Title: CY7C1069BV33 16-Mbit (2M x 8) Static RAM Document Number: 38-05694

REV.ECN NO.Issue Date Orig. of

Change Description of Change

**283950See ECN RKF New data sheet

*A314014See ECN RKF Final data sheet

*B492137See ECN NXR Removed 8 ns speed bin

Changed the description of I IX from Input Load Current to Input Leakage

Current in DC Electrical Characteristics table

Updated the Ordering Information Table