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ISD8102SYI, 规格书,Datasheet 资料

ISD8102SYI, 规格书,Datasheet 资料
ISD8102SYI, 规格书,Datasheet 资料

ISD8102 / ISD8104

2W Class AB Audio Amplifier

with Chip Enable

i) ISD8102 - Earphone Sense IN (SE / Diff)

ii) ISD8104 - Differential Input pair

1 GENERAL DESCRIPTION

The ISD8102/ ISD8104 are a general purpose analog audio amplifier, capable of driving a 4? load with up to 2Wrms output power. This device includes output current limiting, chip enable, low standby current and excellent pop-and-click suppression.

Also included is the ability to configure the input as either single-ended or differential. Internal resistors set the device to have default 20dB gain (ISD8102/ISD8104), and with external resistors any gain less than this can be achieved. The device is unity gain stable, including use with external feedback resistors and external capacitors as may be optionally used for implementing simple filtering functions. ISD8102:

The ISD8102 output can be configured to drive either single ended or bridge tied loads (BTL). The Mode pin controls which configuration is active. This function is useful when using the IDS8102 to alternate between driving a speaker or a mono earpiece which is connected through a shorting phone jack. The Mode pin is connected to the normally closed pin of the shorting phone jack (see figure 3.1). When nothing is plugged into the jack, the external resistor holds the Mode pin low, enabling BTL mode. When a plug is inserted, the switch is opened and the mode pin goes to 1/2 VDD, as controlled by the resistor divider, putting the amplifier into single ended mode. Note that in this example, the speaker remains connected in both cases.

ISD8104:

The ISD8104 has differential inputs and can be configured to accept either single ended or differential signals.

2 FEATURES

?Wide power supply range and excellent

standby current

o 2.0Vdc - 6.8Vdc operation

o <1uA standby current

?High output power (capless BTL

configuration)

o Up to 2W output into 4? load (<10%

distortion) with 6.8Vdc supply voltage

o < 0.1% distortion at 600mW into 8-ohms

with 5Vdc supply voltage

?Excellent pop-and-click performance

o Low to inaudible pop/click using Chip

Enable

?Single-Ended or Differential signal inputs o > 75dB common mode rejection in

differential mode

o > 70dB power supply noise rejection

?Very fast start-up time

o Less than 1msec when using Chip Enable Applications:

? Toys

? Feature Phones

?Current limiting for over-current conditions ?Portable Game Consoles

?Package options: Pb-free SOP-8, SOP-8 (Ex-Pad) ? GPS

? Portable Speakers

?Less BOM cost / Easy PCB layout ? Boom Box ?Temperature Range: -40°C to +85°C ? White Goods

3 BLOCK DIAGRAM

3.1

ISD8102 WITH EARPIECE SENSE INPUT (P IN 3 = SE / BTL MODE )

ISD8102

VREF DC / Logic / Depop

Control

VDD

R1

R1

Shutdown VIN

VOUTP

VOUTN GND

420dB Gain

MODE

Current / Thermal

Protection

0.1uF

Figure 3-1 ISD8102 Earpiece Configuration Block Diagram

3.2 ISD8104 WITH DIFFERENTIAL INPUTS

Figure 3-2 ISD8104 Differential Input Pair Block Diagram

4 PINOUT CONFIGURATION: SOP- 8

Figure 4-1 ISD8102 8-Lead SOP Pin Configuration

Figure 4-2 ISD8104 8-Lead SOP Pin Configuration

5 PIN DESCRIPTION

Pin Name I/O Function

Pin

Number

1 Shutdown I Shutdown (Low = Chip Power Up / High = Chip Power Down)

2 VREF O Internal Reference Voltage (1/2 Vdd)

3 MODE I Single-Ended / Differential Output Logic Control

4 VIN I Inverting Signal Input

5 VOUTP O Non-Inverting Speaker Output

Voltage

6 VDD I Supply

7 GND I Ground

8 VOUTN O Inverting Speaker Output

9 Ex-Pad I Thermal Tab (must be connected to Vss, SOP-8 package, only)

Table 5-1 ISD8102 8-Lead SOP Pin Description Pin

Pin Name I/O Function

Number

Enable

1 CE I Chip

2 VREF O Internal Reference Voltage (1/2 Vdd)

3 VIP I Non-Inverting Signal Input

4 VIN I Inverting Signal Input

5 VOUTP O Non-Inverting Speaker Output

Voltage

6 VDD I Supply

7 GND I Ground

8 VOUTN O Inverting Speaker Output

9 Ex-Pad I Thermal Tab (must be connected to Vss, SOP-8 package, only)

Table 5-2 ISD8104 8-Lead SOP Pin Description

6 ELECTRICAL CHARACTERISTICS

6.1 O PERATING C ONDITIONS

OPERATING CONDITIONS (DIE)

CONDITIONS VALUES

Operating temperature range 1-40°C to +85°C

Supply voltage (V DD) +2.0V to +6.8V

Ground voltage (V SS) 0V Input voltage (V DD) Vss to V DD

Voltage applied to any pins (V SS – 0.3V) to (V DD + 0.3V)

OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS) CONDITIONS VALUES

Operating temperature range (Case temperature) 1-40°C to +85°C

Supply voltage (V DD) +2.0V to +6.8V

Ground voltage (V SS) 0V Input voltage (V DD) Vss to V DD

Voltage applied to any pins (V SS – 0.3V) to (V DD + 0.3V)

Notes: Conditions V DD=5V, T A=25°C unless otherwise stated. Die temperature must at all times be kept less than 125°C by appropriate thermal design of the system.

6.2 DC P ARAMETERS

PARAMETER SYMBOL MIN TYP [1]MAX UNITS CONDITIONS

Supply Voltage V DD 2.0 6.8 V

V DD= 5V, no load Operating Current I DD 2.6 mA

V DD= 5V

1 μA

Standby Current I SB0.1

CE input resistance 20k ?Internal pull-down @ 0dB CE input current 120 μA CE=2.3V, V DD= 5V

CE threshold enabled V ENL0.9 V All supply voltages

CE threshold standby V ENH 1.5 V All supply voltages

VREF Reference Voltage V DD/2 V

Notes: Conditions V DD=5V, T A=25°C unless otherwise stated. Die temperature must at all times be kept less than 125°C by appropriate thermal design of the system.

6.3 AC P ARAMETERS

6.3.1 Analog Characteristics; Cref = 1uF / Cvdd = 1uF

PARAMETER SYMBOL MIN TYP MAX UNITS CONDITIONS

0.3 - 6.5V Vdd = 6.8Vdc

Input Voltage Range

0.3 – 3.4V Vdd = 3.7Vdc

0.3 - 1.7V Vdd = 2.0Vdc

Inverting Input Impedance TBD Gain = 20dB

Non-Inverting Input Impedance TBD Gain = 20dB

Power Supply Rejection Ratio PSRR 75 dB Vdd = 5Vdc Common Mode Rejection Ratio CMRR 70 dB Signal at INP = INV Voltage Gain 20 dB Rinput = 0 ?Enable Time from Standby 0.5 msec Single-ended Enable Time from Standby 0.5 msec Differential

Ended Pop-and-Click from Standby 1 10 mV Single

Pop-and-Click from Standby 1 10 mV Differential Thermal Resistance 60 °C/W SOP-8 (with Ex-Pad) Thermal Resistance 150 °C/W SOP-8

Notes: [1] Impulse voltage that is potentially audible. After impulse, there is a slow ramp from standby

Vref to operating Vref, which is typically inaudible with Cref = 1uF

6.3.2 Speaker Outputs

PARAMETER SYMBOL MIN TYP[1]MAX UNITS CONDITIONS Signal-to-Noise Ratio SNR 100 dB 0dB gain, 5Vdc Load Impedance R L(SPK) 4 ?

Output Offset Voltage 8 mV

PARAMETER SYMBOL MIN TYP[1]MAX UNITS CONDITIONS (THD+N)

Output Power (BTL mode) P BTL600 mW <0.1% distortion Load 4?P BTL1600 mW <1% distortion Vdd=5Vdc / 0dB gain P BTL2000 mW <10% distortion

PARAMETER SYMBOL MIN TYP[1]MAX Units Conditions (THD+N) Output Power (BTL mode) P BTL600 mW <0.1% distortion Load 8?P BTL1200 mW <1% distortion Vdd=5Vdc / 0dB gain P BTL1400 mW <10% distortion

Notes: [1] Conditions V DD=5V, T A=25°C unless otherwise stated. Die temperature must at all times be kept less than 125°C by thermal design of the system.

6.3.3 Chip Enable Threshold Voltage

6.3.4 Output Noise Spectrum

Noise spectrum at Vdd = 5.0Vdc, Gain = 0dB, BW<22kHz

Noise Spectrum at Vdd = 5.0Vdc, Gain = 20dB, BW<22kHz

7 APPLICATION

7.1

G AIN S ETTING – ISD8102

VREF

DC / Logic / Depop

Control

VDD

Shutdown VOUTN GND

MODE

Current / Thermal

Protection

0.1uF

Differential Output Gain (VOUTP – VOUTN) =

By default: Rext = 0?, ISD8102 Differential Output Gain = 20

ISD8102 Differential Output Gain (in dB) = 20 x log (20) = 26dB

Example: Rext = 18k ? ISD8102 Differential Output Gain = 2

ISD8102 Differential Output Gain (in dB) = 20 x log (2) = 6dB

7.2 G AIN S ETTING –ISD8104

Differential Output Gain (VOUTP – VOUTN) =

By default: Rext = 0?,

ISD8104 Differential Output Gain = 20

ISD8104 Differential Output Gain (in dB) = 20 x log (20) = 26dB

Example: Rext = 18k?

ISD8104 Differential Output Gain = 2

ISD8104 Differential Output Gain (in dB) = 20 x log (2) = 6dB

8 PACKAGE SPECIFICATION 8.1 SOP-8

8.2 SOP-8(THERMAL EX-PAD)

9 ORDER INFORMATION

ISD8102 X Y I

10 REVISION HISTORY

Version Date Description

0.0 Aug, 2010 Initial draft

1.0 Jun, 2011 Updated the specifications

1.1 Oct, 2011 Added the ISD8104 Gain Setting Calculation

1.2 Oct, 2011 Updated the specifications

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.

道岔转辙部位框架尺寸表

43kg、50kg普通(AT型)1/9道岔转辙部分各部尺寸表

车站名: 道岔编号: 调查日期: 调查人: 43kg、50kg普通(AT型)1/12道岔转辙部分各部尺寸表

道岔查照间隔整修方案参考表

从此表可知:1、叉心轨轨距必须控制在1433?1438之间,最好是1436mm 2 、轮缘槽宽度较小时,轨距也要相应减小,最低轨距为-2mm护轨槽宽不能超过42mm翼轨槽宽不能超过45mm 3 、槽宽过大时,轨距也要相应增大。最大为+3mm护轨槽宽为44mm翼轨槽宽46?48mm

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GLC(07)02-18#道岔各部框架尺寸(直通线)

GLC(07)02—18#道岔各部框架尺寸(直通线) 一、尖轨尖端绝对位置:距岔前轨端1951mm。距4#枕中心向前120mm。 二、转辙部分框架尺寸:(±1.0mm)(两基本轨作用边测量) 1、尖轨尖端:1435,mm。 2、第一牵引点中心:距尖轨尖端470mm。1437.5mm。 3、12#--13#枕间:距尖轨尖端5168mm。1461.8mm。 4、第二牵引点中心:距第一牵引点中心4800mm。1462.1mm。 5、第三牵引点中心:距第二牵引点中心5400mm。1504.2mm。 6、21#--22#枕间:距尖轨尖端10847mm。1506mm。 7、35#枕中心:直股181mm。曲股181.2mm。(弹性可弯中心) 8、39#枕向后110mm:直股231.6mm。曲股231.9mm。 9、尖轨长度:21450mm。基本轨长度:24592mm。 三|辙岔部分框架尺寸:(两翼轨作用边测量) 1、岔趾:436.2mm。81#枕:423.9mm。82#枕:398.2mm。83#枕:372.1mm。84#枕:345.7mm。 85#枕:319mm。86#枕:291.9mm。87#枕:264.5mm。88#枕:236.8mm。89#枕:208.8mm。 2、第一间隔铁中心:194.4。 3、第二间隔铁中心:165.9。 4、第三间隔铁中心:132.7。 5、心轨理论尖端:119mm。(距92#枕中心向后100mm)(第一牵引点中心距92#枕中心 350mm) 四、长短心轨支距 1、第二牵引点中心:132.1mm。 2、第一间隔铁中心:157.4mm。 3、第二间隔铁中心:179.6mm。 4、第三间隔铁中心:213.3mm。 5、第一顶铁(短心轨)中心:233.8mm。 6、第二顶铁(短心轨)中心:257mm。 7、第三顶铁(短心轨)中心:291.2mm。 8、岔跟尖轨尖端:315mm。 9、最后间隔铁中心:567.8mm。 五、导曲线支距 尖跟垂直于基本轨位置向后2000mm开始向后每2000mm一点,共计15个点,支距如下:273.5mm、318.9mm、367.9mm、420.6mm、477mm、536.9mm、600.6mm、667.8mm、738.7mm、813.2mm、891.4mm、973.2mm、1058.7mm、1147.8mm、1240.5mm。

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