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V53C364405A中文资料

MOSEL VITELIC V53C364405A

3.3 VOLT 16M X 4 EDO PAGE MODE

CMOS DYNAMIC RAM

V53C364405A405060 Max. RAS Access Time, (t RAC)40 ns50 ns60 ns Max. Column Address Access Time, (t CAA)20 ns25 ns30 ns Min. Extended Data Out Page Mode Cycle Time, (t PC)16 ns20 ns25 ns Min. Read/Write Cycle Time, (t RC)69 ns84 ns104 ns

s16M x 4-bit organization

s EDO Page Mode for a sustained data rate of 63 MHz

s RAS access time: 40, 50, 60 ns

s Low power dissipation

s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Self Refresh (L-version only)

s Refresh Interval: 8192 cycles/128 ms

s Available in 32-pin 400 mil SOJ,

and 32-pin 400 mil TSOP-II

s Single +3.3 V ±0.3 V Power Supply

s LV-TTL Interface Description

The V53C364405A is a 16,777,216 x 4 bit high-performance CMOS dynamic random access mem-ory. The V53C364405A offers Page mode opera-tion with Extended Data Output. The V53C364405A has an address, 13-bit row and 11-bit column.

All inputs are LV-TTL compatible. EDO Page Mode operation allows random access up to 2048 x 4 bits, within a page, with cycle times as short as 16 ns.

These features make the V53C364405A ideally suited for a wide variety of high performance computer systems and peripheral applications.

Device Usage Chart

Operating Temperature Range Package Outline Access Time (ns)Power

Temperature

Mark K T405060Std.L

0°C to 70°C???????Blank 元器件交易网https://www.wendangku.net/doc/b210922457.html,

MOSEL VITELIC V53C364405A

Pin Names

A0–A12Row, Column Address Inputs

RAS Row Address Strobe

CAS Column Address Strobe

WE Write Enable

OE Output Enable

I/O1–I/O4Data Input, Output

V CC+3.3V Supply

V SS0V Supply

NC No Connect

Description Pkg.Pin Count

SOJ K32

TSOP-II T32

32 Pin Plastic SOJ /TSOP-II

PIN CONFIGURATION

Top View

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MOSEL VITELIC

V53C364405A

Absolute Maximum Ratings*

Operating temperature range..................0 to 70 ° C Storage temperature range ...............-55 to 150 ° C Soldering temperature..................................260 ° C Soldering time...................................................10 s Input/output voltage....-0.5 to min (V CC +0.5, 4.6) V Power supply voltage ........................-0.5V to 4.6 V Power dissipation ..........................................1.0 W Data out current (short circuit)......................50 mA

* Note: Operation above Absolute Maximum Ratings can

adversely affect device reliability.

Capacitance*

T A = 25 ° C, V CC = 3.3 V ± 0.3 V, V SS = 0 V, f = 1 Mhz

* Note: Capacitance is sampled and not 100% tested.

Symbol Parameter Min.Max.Unit C IN1 Address Input —5pF C IN2 RAS, CAS, WE, OE —7pF C OUT

Data Input/Output

—

Block Diagram

16M x 4

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MOSEL VITELIC V53C364405A DC and Operating Characteristics(1, 2)

T A = 0°C to 70°C, V CC = 3.3 V ± 0.3 V, V SS = 0 V, unless otherwise specified.

Symbol Parameter Access

Time

V53C364405A

Unit Test Conditions Notes Min.Typ.Max.

I LI Input Leakage Current

(any input pin)

–22m A V SS￡ V IN￡ V CC

I LO Output Leakage Current

(for High-Z State)–22m A V SS￡ V OUT￡ V CC

RAS, CAS at V IH

I CC1V CC Supply Current,

Operating 40125mA t RC = t RC (min.)2, 3, 4 50100

6084

I CC2V CC Supply Current,

TTL Standby 1mA RAS, CAS at V IH

other inputs 3 V SS

I CC3V CC Supply Current,

RAS-Only Refresh 40125mA t RC = t RC (min.)2, 4 50100

6084

I CC4V CC Supply Current,

EDO Page Mode

Operation 40140mA Minimum Cycle2, 3, 4 50105

6085

I CC5V CC Supply Current,

CMOS Standby 500m A RAS 3 V CC – 0.2 V,

CAS 3 V CC – 0.2 V

I CC5V CC Supply Current,

CMOS Standby

(L-Version)120m A RAS 3 V CC – 0.2 V,

CAS 3 V CC – 0.2 V

I CC6Average Self Refresh

Current CBR cycle with

t RAS > t RASS min.,

(L-version)

CAS held low, WE =

V CC – 0.2V, Address

and D IN = V CC – 0.2V

or 0.2V

400m A

I CC7V CC Supply Current,

during CAS-before-RAS

Refresh 40170mA2, 4 50140

60115

V IL Input Low Voltage –0.30.8V1

V IH Input High Voltage 2.0V CC+0.3V1

V OL Output Low Voltage0.4V I OL = 2 mA1

V OH Output High Voltage 2.4V I OH = –2 mA1元器件交易网https://www.wendangku.net/doc/b210922457.html,

MOSEL VITELIC V53C364405A TRUTH TABLE

FUNCTION RAS CAS WE OE ROW

ADDR

COL

ADDR I/O1-I/O4

Standby H H ? X X X X X High Impedance Read L L H L ROW COL Data Out

Early-Write L L L X ROW COL Data In

Delayed-Write L L H

? L H ROW COL Data In

Read-Modify-Write L L H ?L L? H ROW COL Data Out, Data In EDO Page Mode Read1st Cycle L H ? L H L ROW COL Data Out

2nd Cycle L H ? L H L N/A COL Data Out

EDO Page Mode Write1st Cycle L H ? L L X ROW COL Data In

2nd Cycle L H ? L L X N/A COL Data In

EDO Page Mode RMW1st Cycle L H ?L H?L L? H ROW COL Data Out, Data In 2nd Cycle L H ?L H?L L? H N/A COL Data Out, Data In RAS only refresh L H X X ROW N/A High Impedance CAS-before-RAS refresh H ? L L H X X N/A High Impedance Test Mode Entry H ? L L L X X N/A High Impedance Hidden Refresh READ L?H?L L H L ROW COL Data Out

WRITE L?H?L L L X ROW COL Data In

Self Refresh (L-version only)H ? L L H X X X High Impedance

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AC Characteristics (5,6)

T A = 0 to 70 ?C,V CC = 3.3 V±0.3V , t T = 2 ns

#Symbol Parameter

-40- 50- 60

Unit Note min.max.min.max.min.max.

Common Parameters

1t RC Random read or write cycle time69–84–104–ns

2t RAS RAS pulse width40100k50100k60100k ns

3t CAS CAS pulse width610k810k1010k ns

4t RP RAS precharge time25–30–40–ns

5t CP CAS precharge time6–8–10–ns

6t ASR Row address setup time0–0–0–ns

7t RAH Row address hold time5–7–10–ns

8t ASC Column address setup time0–0–0–ns

9t CAH Column address hold time5–7–10–ns

10t RCD RAS to CAS delay time 93011371445ns

11t RAD RAS to column address delay time 7209251230ns

12t RSH RAS hold time6–810–ns

13t CSH CAS hold time32–4048–ns

14t CRP CAS to RAS precharge time5–5–5–ns

15t T Transition time (rise and fall) 150150150ns7 16t REF Refresh period–128–128–128ms

17t REF Refresh period for L-versions–256–256–256ms

Read Cycle

18t RAC Access time from RAS–40–50–60ns8,9 19t CAC Access time from CAS–10–13–15ns8,9 20t CAA Access time from column address –20–25–30ns8,10 21t OEA OE access time–10–13–15ns

22t RAL Column address to RAS lead time20–25–30–ns

23t RCS Read command setup time0–0–0–ns

24t RCH Read command hold time 0–0–0–ns11 25t RRH Read command hold time referenced to RAS 0–0–0–ns11 26t CLZ CAS to output in low-Z 0–0–0–ns8 27t OFF Output buffer turn-off delay 010013015ns12 28t DZ Output buffer turn-off delay from OE010013015ns12 29t DZC Data to CAS low delay 0–0–0–ns13 30t DZO Data to OE low delay0–0–0–ns13

31t CDD CAS high to data delay 10–13–15–ns 1432

t ODD

OE high to data delay

–

Write Cycle

33t WCH Write command hold time 5–7–10–ns 34t WP Write command pulse width 5–7–10–ns 35t WCS Write command setup time 0–0–0–ns 15

36t RWL Write command to RAS lead time 6–8–10–ns 37t CWL Write command to CAS lead time 6–8–10–ns 38t DS Data setup time 0–0–0–ns 1639

t DH

Data hold time

–

16Read-modify-Write Cycle

40t RWC Read-write cycle time 89–109–133–ns 41t RWD RAS to WE delay time 52–65–77–ns 1542t CWD CAS to WE delay time

22–28–32–ns 1543t AWD Column address to WE delay time 32–40–47–ns 15

t OEH

OE command hold time

–

EDO Page Mode Cycle

45t HPC EDO Page Mode cycle time 16–20–24–ns 46t CPA Access time from CAS precharge –22–28–34ns 7

47t COH Output data hold time

5–5–5–ns 48t RAS RAS pulse width in EDO page mode 40200k 50200k 60200k ns 49t RHPC CAS precharge to RAS Delay 22–28–34–ns 50t OEP OE pulse width

5–5–5–ns 51t OEHC OE hold time from CAS high 5–5–5–ns 52

t WEZ

Output buffer turn-off delay from WE

EDO Page Mode Read-modify-Write Cycle

53t PRWC EDO page mode read-write cycle time 42–54–63–ns 54

t CPWD

CAS precharge to WE

–

AC Characteristics (5,6) (Continued)

T A = 0 to 70 ?C,V CC = 3.3 V ±0.3V , t T = 2 ns

Symbol

Parameter

-40

- 50- 60

Unit Note

min.max.min.max.min.max.

CAS before RAS Refresh Cycle

55t CSR CAS setup time 5–5–5–ns 56t CHR CAS hold time

5–5–10–ns 57t RPC RAS to CAS precharge time 5–5–5–ns 58t WRP Write to RAS precharge time 5–5–10–ns 59

t WRH

Write hold time referenced to RAS

–

Self Refresh Cycle (L-versions only)

60t RASS RAS pulse width 100k 100k _100k _ns 1761t RPS RAS precharge time 69–84–104–ns 1762

t CHS

CAS hold time

-50

–

-50

–

-50

–

Test Mode Cycle

63t WTS Write command setup time 5–5–5–ns 1864

t WTH

Write command hold time

–

AC Characteristics (5,6) (Continued)

T A = 0 to 70 ?C,V CC = 3.3 V ±0.3V , t T = 2 ns

Symbol

Parameter

-40

- 50

- 60

Unit Note

min.max.min.max.min.max.

Notes:

1)All voltages are referenced to VSS.

V IH may overshoot to V CC + 0.2V for pulse widths of < 4ns with 3.3V. V IL may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.

2)I CC1, I CC3, I CC4 and I CC6 and I CC7 depend on cycle rate.

3)I CC1 and I CC4 depend on output loading. Specified values are measured with the output open.

4)Address can be changed once or less while RAS = V IL. In the case of I CC4 it can be changed once or less during a

EDO page mode cycle (t PC).

5)An initial pause of 100 m s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device

operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cy-cles instead of 8 RAS cycles are required.

6)AC measurements assume t T = 2 ns.

7)V IH (min.) and V IL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured

between V IH and V IL.

8) Measured with the specified current load and 100 pF at V OH = 2.0 V and V OL = 0.8 V.

9) Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point

only: If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by t CAC.

10) Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point

only: If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t CAA.

11) Either t RCH or t RRH must be satisfied for a read cycle.

12) t OFF (max.) and t OEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not

referenced to output voltage levels.

13) Either t DZC or t DZO must be satisfied.

14) Either t CDD or t ODD must be satisfied.

15) t WCS, t RWD, t CWD, t AWD and t CPWD are not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If t WCS > t WCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if t RWD > t RWD (min.), t CWD > t CWD (min.), t AWD > t AWD (min.) and t CPWD > t CPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.

16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-

Modify-Write cycles.

17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM

operation:

If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.

If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh

18)In a Test Mode Read Cycle, the value of trac, t RAC, t CAC and t CPA are delayed by 5 ns from the specified value.

These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns.

Waveforms of Read Cycle

RAS

CAS

Address

I/O

(Inputs)

I/O

(Outputs)

WL1

Waveforms of Write Cycle (Early Write)

CAS

Address

I/O

(Inputs)

I/O

(Outputs)

WL2

Waveforms of Write Cycle (OE Controlled Write)

RAS

CAS

Address

I/O

(Inputs)

I/O

(Outputs)

V IH

V IL

V V V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V IH V IL

Waveforms of Read-Write (Read-Modify-Write) Cycle

I/O

(Outputs)

I/O

(Inputs)

RAS

CAS

Address

V IH V IL

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V OL

Waveforms of EDO Page Mode Read Cycle

RAS

I/O WE

Address

CAS

V IH

V IL

(Output)

V IH

V IL

V IH

V IL

V IH

V IL

V OH

V OL

V IH V IL

Waveforms of EDO Page Mode Read Cycle (OE Control)

RAS

I/O WE

Address

CAS

(Output)

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V V V IH V IL

Waveforms of EDO Page Mode Read Cycle (WE Control)

RAS

I/O WE

Address

CAS

(Output)

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V V V IH V IL

Waveforms of EDO Page Mode Early Write Cycle

RAS

I/O (Input)

Address

CAS

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V V V IH

V IL

Waveforms of EDO Page Mode Late Write Cycle

RAS

I/O WE

Address

CAS

(Input)

V IH

V IL

V IH

V IL

V IH

V IL

V IH

V IL

V V V IH V IL

Waveforms of RAS Only Refresh Cycle

Address

RAS

CAS

I/O

(Outputs)

V IH V IL

V IH

V IL

V IH

V IL

V V OL