当前位置：文档库 › tas5711

tas5711

TAS5711

https://www.wendangku.net/doc/bd16485461.html, SLOS600A–DECEMBER2009–REVISED AUGUST2010 20-W DIGITAL AUDIO-POWER AMPLIFIER WITH EQ,DRC,AND2.1MODE

Check for Samples:TAS5711

FEATURES

?Audio Input/Output?Benefits

–20-W Into an8-?Load From an18-V Supply–Up to90%Efficient

–Wide PVDD Range,From8V to26V–AD and BD Filter Mode Support

–Efficient Class-D Operation Eliminates–SNR:106dB,A-Weighted Need for Heatsinks–EQ:Speaker Equalization Improves Audio –One Serial Audio Input(Two Audio Performance

Channels)–DRC:Dynamic Range Compression.Can – 2.1Mode(2SE+1BTL)Be Used As Power Limiter.Enables

Speaker Protection,Easy Listening,– 2.0Mode(2BTL)

Night-Mode Listening.

–Single-Filter PBTL Mode Support

–Separate DRC for Satellite and –I2C Address Selection Pin(Chip Select)

Subchannels

–Supports8-kHz to48-kHz Sample Rate

–Autobank Switching:Preload Coefficients (LJ/RJ/I2S)

for Different Sample Rates.No Need to ?Audio/PWM Processing Write new Coefficients to the Part When

–Independent Channel Volume Controls With Sample Rate Changes.

24-dB to Mute–Autodetect:Automatically Detects –Separate Dynamic Range Control for Sample-Rate Changes.No Need for Satellite and Subchannels External Microprocessor Intervention –21Programmable Biquads for Speaker EQ?Requires Only3.3V and PVDD and Other Audio Processing Features

–Programmable Coefficients for DRC Filters APPLICATIONS

?Television

–DC Blocking Filters

?iPod?Dock

–Support for3D Effects

?Sound Bar

?General Features

–Serial Control Interface Operational Without DESCRIPTION

MCLK

The TAS5711is a20-W,efficient,digital audio power –Factory-Trimmed Internal Oscillator for

amplifier for driving stereo bridge-tied speakers.One Automatic Rate Detection

serial data input allows processing of up to two –Surface Mount,48-Pin,7-mm×7-mm discrete audio channels and seamless integration to HTQFP Package most digital audio processors and MPEG decoders.

The device accepts a wide range of input data and –Thermal and Short-Circuit Protection

data rates.A fully programmable data path routes –Support for AD or BD Mode

these channels to the internal speaker drivers.

The TAS5711is an I2S slave-only device receiving all

clocks from external sources.The TAS5711operates

with a PWM carrier between384-kHz switching rate

and352-KHz switching rate depending on the input

sample rate.Oversampling combined with a

fourth-order noise shaper provides a flat noise floor

and excellent dynamic range from20Hz to20kHz.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

iPod is a trademark of Apple Inc.

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

B0264-09

TAS5711

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

https://www.wendangku.net/doc/bd16485461.html,

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SIMPLIFIED APPLICATION DIAGRAM

(1)See TAS5711EVM User's Guide (SLOU280)for loop filter values.

2Submit Documentation Feedback

Product Folder Link(s):TAS5711

SDIN

MCLK SCLK LRCLK

SDA

SCL

OUT_A

OUT_B

OUT_C

OUT_D

B0262-06 TAS5711

https://www.wendangku.net/doc/bd16485461.html, SLOS600A–DECEMBER2009–REVISED AUGUST2010 FUNCTIONAL VIEW

Product Folder Link(s):TAS5711

TAS5711

SLOS600A–DECEMBER2009–REVISED https://www.wendangku.net/doc/bd16485461.html,

Figure1.Power Stage Functional Block Diagram

4Submit Documentation Feedback Copyright?2009–2010,Texas Instruments Incorporated

Product Folder Link(s):TAS5711

B 0321-08

TAS5711

https://www.wendangku.net/doc/bd16485461.html,

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

DAP Process Structure

Submit Documentation Feedback

Product Folder Link(s):TAS5711

V O S C D A L S T _B

V D D _B

V D D _C

U T _C

G N D _A B

U T _B

G N D _C D

G N D _A B

V D D _B

G N D _C D

S T _C

V D D _C

P0075-08

PHP Package (Top View)

TAS5711

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

https://www.wendangku.net/doc/bd16485461.html,

DEVICE INFORMATION

PIN ASSIGNMENT

PIN FUNCTIONS

PIN 5-V TYPE (1)

TERMINATION (2)

DESCRIPTION

TOLERANT

NAME NO.AGND 30P Analog ground for power stage

A_SEL

DIO

A value of 0(15-k Ωpulldown)makes the I 2C device address 0x34,and a value of 1(15-k Ωpullup)makes it 0x36.This pin can be

programmed after RESET to be an output by writing 1to bit 0of I 2C register 0x05.In that mode,the A_SEL pin is redefined as FAULT (see ERROR REPORTING for details).AVDD 13P 3.3-V analog power supply AVSS 9P Analog 3.3-V supply ground

BST_A 4P High-side bootstrap supply for half-bridge A BST_B 43P High-side bootstrap supply for half-bridge B BST_C 42P High-side bootstrap supply for half-bridge C BST_D 33P High-side bootstrap supply for half-bridge D DVDD 27P 3.3-V digital power supply DVSSO 17

Oscillator ground

(1)TYPE:A =analog;D =3.3-V digital;P =power/ground/decoupling;I =input;O =output

(2)All pullups are weak pullups and all pulldowns are weak pulldowns.The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups →logic 1input;pulldowns →logic 0input).

Submit Documentation Feedback

Product Folder Link(s):TAS5711

TAS5711 https://www.wendangku.net/doc/bd16485461.html, SLOS600A–DECEMBER2009–REVISED AUGUST2010

PIN FUNCTIONS(continued)

PIN5-V

TYPE(1)TERMINATION(2)DESCRIPTION

TOLERANT

NAME NO.

DVSS28P Digital ground

GND29P Analog ground for power stage

GVDD_OUT5,32P Gate drive internal regulator output.This pin must not be used to

drive external devices.

LRCLK20DI5-V Pulldown Input serial audio data left/right clock(sample rate clock)

MCLK15DI5-V Pulldown Master clock input

OC_ADJ7AO Analog overcurrent programming.Requires resistor to ground.

OSC_RES16AO Oscillator trim resistor.Connect an18.2-k?1%resistor to DVSSO. OUT_A1O Output,half-bridge A

OUT_B46O Output,half-bridge B

OUT_C39O Output,half-bridge C

OUT_D36O Output,half-bridge D

PBTL8DI Low means BTL or SE mode;high means PBTL https://www.wendangku.net/doc/bd16485461.html,rmation

goes directly to power stage.

PDN19DI5-V Pullup Power down,active-low.PDN prepares the device for loss of power

supplies by shutting down the Noise Shaper and initiating PWM stop

sequence.

PGND_AB47,48P Power ground for half-bridges A and B

PGND_CD37,38P Power ground for half-bridges C and D

PLL_FLTM10AO PLL negative loop filter terminal

PLL_FLTP11AO PLL positive loop filter terminal

PVDD_A2,3P Power supply input for half-bridge output A

PVDD_B44,45P Power supply input for half-bridge output B

PVDD_C40,41P Power supply input for half-bridge output C

PVDD_D34,35P Power supply input for half-bridge output D

RESET25DI5-V Pullup Reset,active-low.A system reset is generated by applying a logic

low to this pin.RESET is an asynchronous control signal that

restores the DAP to its default conditions,and places the PWM in

the hard mute state(tristated).

SCL24DI5-V I2C serial control clock input

SCLK21DI5-V Pulldown Serial audio data clock(shift clock).SCLK is the serial audio port

input data bit clock.

SDA23DIO5-V I2C serial control data interface input/output

SDIN22DI5-V Pulldown Serial audio data input.SDIN supports three discrete(stereo)data

formats.

SSTIMER6AI Controls ramp time of OUT_x to minimize pop.Leave this pin

floating for BD mode.Requires capacitor of2.2nF to GND in AD

mode.The capacitor determines the ramp time.

STEST26DI Factory test pin.Connect directly to DVSS.

VR_ANA12P Internally regulated1.8-V analog supply voltage.This pin must not

be used to power external devices.

VR_DIG18P Internally regulated1.8-V digital supply voltage.This pin must not be

used to power external devices.

VREG31P Digital regulator output.Not to be used for powering external

circuitry.

Product Folder Link(s):TAS5711

TAS5711

SLOS600A–DECEMBER2009–REVISED https://www.wendangku.net/doc/bd16485461.html,

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range(unless otherwise noted)(1)

VALUE UNIT DVDD,AVDD–0.3to3.6V Supply voltage

PVDD_x–0.3to30V

OC_ADJ–0.3to4.2V

3.3-V digital input–0.5to DVDD+0.5V

Input voltage

5-V tolerant(2)digital input(except MCLK)–0.5to DVDD+2.5(3)V

5-V tolerant MCLK input–0.5to AVDD+2.5(3)V

OUT_x to PGND_x32(4)V

BST_x to PGND_x43(4)V

Input clamp current,I IK±20mA Output clamp current,I OK±20mA Operating free-air temperature0to85°C Operating junction temperature range0to150°C Storage temperature range,T stg–40to125°C (1)Stresses beyond those listed under absolute ratings may cause permanent damage to the device.These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied.Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2)5-V tolerant inputs are PDN,RESET,SCLK,LRCLK,MCLK,SDIN,SDA,and SCL.

(3)Maximum pin voltage should not exceed6.0V

(4)DC voltage+peak ac waveform measured at the pin should be below the allowed limit for all conditions.

THERMAL INFORMATION

TAS5711

THERMAL METRIC(1)(2)UNITS

PHP(48PIN)

q JA Junction-to-ambient thermal resistance29.9

q JCtop Junction-to-case(top)thermal resistance20.5

q JB Junction-to-board thermal resistance12.5

°C/W

y JT Junction-to-top characterization parameter0.3

y JB Junction-to-board characterization parameter7.3

q JCbot Junction-to-case(bottom)thermal resistance0.7

(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.

(2)For thermal estimates of this device based on PCB copper area,see the TI PCB Thermal Calculator.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT Digital/analog supply voltage DVDD,AVDD3 3.3 3.6V

Half-bridge supply voltage PVDD_x826V

V IH High-level input voltage5-V tolerant2V

V IL Low-level input voltage5-V tolerant0.8V

T A Operating ambient temperature range085°C

T J(1)Operating junction temperature range0125°C

R L(BTL)Load impedance Output filter:L=15m H,C=680nF.68?

Minimum output inductance under10

L O(BTL)Output-filter inductance m H

short-circuit condition

(1)Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

8Submit Documentation Feedback Copyright?2009–2010,Texas Instruments Incorporated

Product Folder Link(s):TAS5711

TAS5711 https://www.wendangku.net/doc/bd16485461.html, SLOS600A–DECEMBER2009–REVISED AUGUST2010

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS VALUE UNIT

11.025/22.05/44.1-kHz data rate±2%352.8kHz Output sample rate

48/24/12/8/16/32-kHz data rate±2%384

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f MCLKI MCLK Frequency 2.822424.576MHz

MCLK duty cycle40%50%60%

tr/

Rise/fall time for MCLK5ns

tf(MCLK)

LRCLK allowable drift before LRCLK reset4MCLKs External PLL filter capacitor C1SMD0603X7R47nF

External PLL filter capacitor C2SMD0603X7R 4.7nF

External PLL filter resistor R SMD0603,metal film470?ELECTRICAL CHARACTERISTICS

DC Characteristics

TA=25°,PVCC_x=18V,DVDD=AVDD=3.3V,R L=8?,BTL AD Mode,FS=48KHz(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V OH High-level output voltage A_SEL and SDA I OH=–4mA 2.4V

DVDD=AVDD=3V

V OL Low-level output voltage A_SEL and SDA I OL=4mA0.5V

DVDD=AVDD=3V

V I

I IL Low-level input current m A

=3.6V

V I>V IH;DVDD=75(1)

I IH High-level input current m A

AVDD=3.6V

Normal Mode4870

3.3V supply voltage(DVDD,

I DD 3.3V supply current mA

Reset(RESET=low,2432

AVDD)

PDN=high)

Normal Mode3055

I PVDD Half-bridge supply current No load(PVDD_x)mA

Reset(RESET=low,513

PDN=high)

Drain-to-source resistance,LS T J=25°C,includes metallization resistance180

r DS(on)(2)m?Drain-to-source resistance,

T J=25°C,includes metallization resistance180

I/O Protection

V uvp Undervoltage protection limit PVDD falling7.2V

V uvp,hyst Undervoltage protection limit PVDD rising7.6V OTE(3)Overtemperature error150°C

Extra temperature drop

OTE HYST(3)30°C required to recover from error

OLPC Overload protection counter f PWM=384kHz0.63ms

I OC Overcurrent limit protection Resistor—programmable,max.current,R OCP=22k? 4.5A

I OCT Overcurrent response time150ns

OC programming resistor Resistor tolerance=5%for typical value;the minimum

R OCP2022k?range resistance should not be less than20k?.

Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap

R PD3k?the output of each half-bridge capacitor charge.

(1)I IH for the PBTL pin has a maximum limit of200μA due to an intenal pulldown on the pin.

(2)This does not include bond-wire or pin resistance.

(3)Specified by design

Product Folder Link(s):TAS5711

TAS5711

SLOS600A–DECEMBER2009–REVISED https://www.wendangku.net/doc/bd16485461.html,

AC Characteristics(BTL)

PVDD_x=18V,BTL AD mode,FS=48KHz,R L=8?,R OCP=22K?,C BST=33nF,audio frequency=1kHz,AES17filter, f PWM=384kHz,T A=25°C(unless otherwise specified).All performance is in accordance with recommended operating conditions(unless otherwise specified).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PVDD=18V,10%THD,1-kHz input signal21

PVDD=18V,7%THD,1-kHz input signal20

PVDD=12V,10%THD,1-kHz input signal9.5

PVDD=12V,7%THD,1-kHz input signal9

PVDD=8V,10%THD,1-kHz input signal 4.1

PVDD=8V,7%THD,1-kHz input signal 3.9

PBTL mode,PVDD=12V,R L=4Ω,

19.2

10%THD,1-kHz input signal

PBTL mode,PVDD=12V,R L=4Ω,

7%THD,1-kHz input signal

P O Power output per channel W

PBTL mode,PVDD=18V,R L=4Ω,

42.8

10%THD,1-kHz input signal

PBTL mode,PVDD=18V,R L=4Ω,

7%THD,1-kHz input signal

SE mode,PVDD=12V,R L=4Ω,

4.6

10%THD,1-kHz input signal

SE mode,PVDD=12V,R L=4Ω,

4.3

7%THD,1-kHz input signal

SE mode,PVDD=24V,R L=4Ω,

17.8

10%THD,1-kHz input signal

SE mode,PVDD=24V,R L=4Ω,

7%THD,1-kHz input signal

PVDD=18V,P O=1W0.06%

THD+N Total harmonic distortion+noise PVDD=12V,P O=1W0.08%

PVDD=8V,P O=1W0.2%

V n Output integrated noise(rms)A-weighted44m V

P O=0.25W,f=1kHz(BD Mode)–82dB Crosstalk

P O=0.25W,f=1kHz(AD Mode)–69dB

A-weighted,f=1kHz,maximum power at

SNR Signal-to-noise ratio(1)106dB

THD<1%

(1)SNR is calculated relative to0-dBFS input level.

10Submit Documentation Feedback Copyright?2009–2010,Texas Instruments Incorporated

Product Folder Link(s):TAS5711

SCLK (Input)

LRCLK (Input)

SDIN

T0026-04

TAS5711

https://www.wendangku.net/doc/bd16485461.html,

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)

TEST PARAMETER

MIN TYP MAX UNIT CONDITIONS f SCLKIN Frequency,SCLK 32×f S ,48×f S ,64×f S C L =30pF

1.0241

2.288

MHz t su1Setup time,LRCLK to SCLK rising edge 10ns t h1Hold time,LRCLK from SCLK rising edge 10ns t su2Setup time,SDIN to SCLK rising edge 10ns t h2

Hold time,SDIN from SCLK rising edge 10ns

LRCLK frequency 84848kHz

SCLK duty cycle 40%50%60%LRCLK duty cycle

40%50%

60%SCLK SCLK rising edges between LRCLK rising edges

3264edges t (edge)SCLK LRCLK clock edge with respect to the falling edge of SCLK –1/4

1/4period t r /t f

Rise/fall time for SCLK/LRCLK

Figure 2.Slave Mode Serial Data Interface Timing

Product Folder Link(s):TAS5711

SCL

SDA

T0027-01 SCL

SDA

Start Condition

Stop

Condition

T0028-01

TAS5711

SLOS600A–DECEMBER2009–REVISED https://www.wendangku.net/doc/bd16485461.html,

I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f SCL Frequency,SCL No wait states400kHz

t w(H)Pulse duration,SCL high0.6m s

t w(L)Pulse duration,SCL low 1.3m s

t r Rise time,SCL and SDA300ns

t f Fall time,SCL and SDA300ns

t su1Setup time,SDA to SCL100ns

t h1Hold time,SCL to SDA0ns

t(buf)Bus free time between stop and start condition 1.3m s

t su2Setup time,SCL to start condition0.6m s

t h2Hold time,start condition to SCL0.6m s

t su3Setup time,SCL to stop condition0.6m s

C L Load capacitance for each bus line400pF

Figure3.SCL and SDA Timing

Figure4.Start and Stop Conditions Timing

12Submit Documentation Feedback Copyright?2009–2010,Texas Instruments Incorporated

Product Folder Link(s):TAS5711

RESET

System Initialization.Enable via I C.

T0421-01

TAS5711

https://www.wendangku.net/doc/bd16485461.html,

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

RESET TIMING Control signal parameters over recommended operating conditions (unless otherwise noted).Please refer to Recommended Use Model section on usage of all terminals.

PARAMETER

MIN TYP MAX UNIT t w(RESET)Pulse duration,RESET active 100

μs t d(I2C_ready)

Time to enable I 2

12.0

NOTES:On power up,it is recommended that the TAS5711RESET be held LOW for at least 100m s after DVDD has

reached 3V.

If the RESET is asserted LOW while PDN is LOW,then the RESET must continue to be held LOW for at least 100m s after PDN is deasserted (HIGH).

Figure 5.Reset Timing

Product Folder Link(s):TAS5711

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.11

100

10k 20k

G001

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k

20k

G002

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k

20k

G003

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

110

100

10k

20k

G004

TAS5711

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

https://www.wendangku.net/doc/bd16485461.html,

TYPICAL CHARACTERISTICS,BTL CONFIGURATION

Figure 6.

Figure 7.

Figure 8.Figure 9.

14Submit Documentation Feedback

Product Folder Link(s):TAS5711

Output Power (W)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

0.01

0.1

1050

G005

Output Power (W)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

0.01

0.1

1050

G006

Output Power (W)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

0.01

0.1

1050

G007

Output Power (W)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

0.01

0.1

1050

G008

TAS5711

https://www.wendangku.net/doc/bd16485461.html,

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS,BTL CONFIGURATION (continued)

Figure 10.

Figure 11.

Figure 12.Figure 13.

Product Folder Link(s):TAS5711

Supply Voltage (V)

O u t p u t P o w e r (W )

OUTPUT POWER

SUPPLY VOLTAGE

1416182022

0510

152025

3540

G009

Total Output Power (W)

E f f i c i e n c y (%)

EFFICIENCY

TOTAL OUTPUT POWER

10152025

G010

Frequency (Hz)

C r o s s t a l k (d B )

CROSSTALK

FREQUENCY

-100

-90-80-70-60-50-40-30-20-10020

100

10k

20k

G011

Frequency (Hz)

C r o s s t a l k (d B )

CROSSTALK

FREQUENCY

-100

-90-80

-70

-60-50-40-30-20-10020

100

10k 20k

G012

TAS5711

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

https://www.wendangku.net/doc/bd16485461.html,

TYPICAL CHARACTERISTICS,BTL CONFIGURATION (continued)

NOTE:Dashed lines represent thermally limited region.

Figure 14.

Figure 15.

Figure 16.Figure 17.

16Submit Documentation Feedback

Product Folder Link(s):TAS5711

Frequency (Hz)

C r o s s t a l k (d B )

CROSSTALK

FREQUENCY

-100

-90-80-70-60-50-40-30-20-10020

100

10k

20k

G013

Frequency (Hz)

C r o s s t a l k (d B )

CROSSTALK

FREQUENCY

-100

-90

-80-70-60-50-40-30-20-10020

100

10k 20k

G014

TAS5711

https://www.wendangku.net/doc/bd16485461.html,

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS,BTL CONFIGURATION (continued)

Figure 18.Figure 19.

Product Folder Link(s):TAS5711

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k 20k

G015

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k

20k

G016

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k

20k

G017

Output Power (W)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

0.01

0.1

1050

G018

TAS5711

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

https://www.wendangku.net/doc/bd16485461.html,

TYPICAL CHARACTERISTICS,SE CONFIGURATION

Figure 20.

Figure 21.

Figure 22.Figure 23.

18Submit Documentation Feedback

Product Folder Link(s):TAS5711

Supply Voltage (V)

O u t p u t P o w e r (W )

OUTPUT POWER

SUPPLY VOLTAGE

1416182022

0246

8101214

16182022

G019

Total Output Power (W)

E f f i c i e n c y (%)

EFFICIENCY

TOTAL OUTPUT POWER

G020

TAS5711

https://www.wendangku.net/doc/bd16485461.html,

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS,SE CONFIGURATION (continued)

NOTE:Dashed lines represent thermally limited region.

Figure 24.

Figure 25.

Product Folder Link(s):TAS5711

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.010.11

100

10k 20k

G021

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k 20k

G022

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

100

10k

20k

G023

Frequency (Hz)

T H D +N (%)

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.01

0.1

110

100

10k 20k

G024

TAS5711

SLOS600A –DECEMBER 2009–REVISED AUGUST 2010

https://www.wendangku.net/doc/bd16485461.html,

TYPICAL CHARACTERISTICS,PBTL CONFIGURATION

Figure 26.

Figure 27.

Figure 28.Figure 29.

20Submit Documentation Feedback

Product Folder Link(s):TAS5711