512Mb_Mobile_SDRAM_TwinDie_x32
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512Mb Mobile SDRAM_TwinDie_x32.fm -Rev. C 6/05 EN
?2004 Micron Technology, Inc. All rights reserved.
Mobile SDRAM
MT48LC16M32L2 – 4 Meg x 32 x 4 Banks MT48V16M32L2 – 4 Meg x 32 x 4 Banks MT48H16M32L2 – 4 Meg x 32 x 4 Banks Features
?Low voltage power supply
?Partial array self refresh power-saving mode ?Temperature compensated self refresh (TCSR)?Deep power-down mode
?Programmable output drive strength
?Fully synchronous; all signals registered on positive edge of system clock
?Internal pipelined operation; column address can be changed every clock cycle
?Internal banks for hiding row access/precharge ?Programmable burst lengths: 1, 2, 4, 8, or full page ?Auto precharge, includes concurrent auto precharge, and auto refresh modes
?Self refresh mode; standard and low power ?64ms, 8,192-cycle refresh
?LVTTL-compatible inputs and outputs ?Operating temperature range ?Industrial (-40°C to +85°C)
?
Supports CAS latency of 1, 2, 3
Options
Marking
?V DD /V DD Q 3.3V/3.3V LC 2.5V/2.5V V 1.8V/1.8V H ?Configuration
16M32 stacked die L2?Package/ballout
Plastic package 90-ball FBGA (8mm x 13mm) (standard)
F5Plastic package 90-ball FBGA (8mm x 13mm) (lead-free)B5
?Timing (cycle time)8ns at CL3 (125 MHz)-810ns at CL3 (100 MHz)-10?Temperature
Commercial (0°C to +70°C)No Marking
Industrial (-40°C to +85°C)
IT
Addendum Changes
The standard 256Mb SDRAM Mobile x32 data sheets should be referenced for a complete description of SDRAM functionality and operating modes. This addendum data sheet will concentrate on the key dif-ferences required to support the enhanced options of the TwinDie configuration.
The Micron 256Mb Mobile X32 data sheet provides full specifications and functionality unless specified herein.Table 1:
Key Timing Parameters
Speed Grade Clock Frequency Access Time at CL = 3Access Time at CL = 2
-8125 MHz 7.5ns 8.5ns -10
100 MHz
7.5ns
8.5ns
Table 2: Configuration
Architecture 16 Meg x 32Configuration 4 Meg x 32 x 4 banks
Refresh Count 8K
Row Addressing 8K (A0–A12)Bank Addressing 4 (BA0, BA1)Column Addressing
512 (A0–A8)
General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured by stacking two 256Mb, 8 Meg x 32 devices.
Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous
interface. They are organized with 32 DQs with 4 banks of 67,108,864 bits, comprising of
8,192 rows by 512 columns by 32 bits wide.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0-A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-speed, random-access opera-
tion.
The 512Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V memory systems. An
auto refresh mode is provided, along with a power-saving, power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the abil-
ity to synchronously burst data at a high data rate with automatic column-address gen-
eration, the ability to interleave between internal banks to hide precharge time, and the
capability to randomly change column addresses on each clock cycle during a burst
access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering die intitialization, register definition, command
descriptions, and device operation on a per die basis unless otherwise noted.
This addendum documents any variances for the 512Mb: x32 Mobile SDRAM from the
256Mb: x32 Mobile SDRAM specification. Please refer to the 256Mb: x32 Mobile SDRAM
data sheet on Micron’s Web site for additional details on the part functionality. Commands
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is non-
persistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing a AUTO REFRESH command. The AUTO REFRESH com-
mand should not be issued until the minimum t RP has been met after the PRECHARGE
command as shown in the operations section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb TwinDie? Mobile
SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (t REF). Providing a distributed
AUTO REFRESH command every 7.81μs will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (t RC), once every 64ms.
Figure 1:
Ball Assignment
Figure 2: 90-Ball FBGA Assignment
Electrical Specifications
Table 3: DC Electrical Characteristics and Operating Conditions (LC version)
V DD/V DD Q = +3.3V ±0.3V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition Symbol MIN MAX Units Notes Supply Voltage V DD/V DD Q3 3.6V
Input High Voltage: Logic 1; All inputs V IH0.8 x V DD Q V DD + 0.3V22 Input Low Voltage: Logic 0; All inputs V IL-0.30.3V22
I I-55μA
Input Leakage Current:
Any input 0V ≤ V IN≤ V DD
(All other balls not under test = 0V)
I OZ-55μA
Output Leakage Current: DQs are disabled; 0V ≤ V OUT≤
V DD Q
V OH V DD Q - 0.2–V
Output Levels:
Output High Voltage (I OUT = -4mA)
Output Low Voltage (I OUT = 4mA)V OL–0.2V
Table 4: DC Electrical Characteristics and Operating Conditions (V version)
V DD = +2.5V ±0.2V V DD Q = +2.5V ±0.2V or V DD Q = +1.8V ±0.15V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition Symbol MIN MAX Units Notes Supply Voltage V DD/V DD Q 2.3 2.7V
Input High Voltage: Logic 1; All inputs V IH0.8 x V DD Q V DD Q + 0.3V22 Input Low Voltage: Logic 0; All inputs V IL-0.30.3V22
I I-3.0 3.0μA
Input Leakage Current:
Any input 0V ≤ V IN≤ V DD
(All other balls not under test = 0V)
I OZ-3.0 3.0μA
Output Leakage Current: DQs are disabled; 0V ≤ V OUT≤
V DD Q
V OH 0.9 x VDDQ–V
Output Levels:
Output High Voltage (I OUT = -4mA)
Output Low Voltage (I OUT = 4mA)V OL–0.2V
Table 5: DC Electrical Characteristics and Operating Conditions (H version)
V DD = +1.8V ±0.1V V DD Q = +1.8V ±0.1V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition Symbol MIN MAX Units Notes Supply Voltage V DD/V DD Q 1.7 1.9V
Input High Voltage: Logic 1; All inputs V IH
0.8 x V DD Q
V DD Q + 0.3V22
Input Low Voltage: Logic 0; All inputs V IL-0.30.3V22 Input Leakage Current:
Any input 0V ≤ V IN≤ V DD
(All other balls not under test = 0V)
I I-1.0 1.0μA
Output Leakage Current: DQs are disabled; 0V ≤ V OUT≤
V DD Q
I OZ-1.5 1.55μA
Output Levels:
Output High Voltage (I OUT = -4mA)
V OH 0.9 x VDDQ–V
Output Low Voltage (I OUT = 4mA)V OL–0.2V
Table 6: I DD Specifications and Conditions (LC version)
V DD = +3.3V ±0.3V, V DD Q = +3.3V ±0.3V
Notes: 1, 5, 6, 11, 13; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
MAX
Parameter/Condition Symbol-8-10Units Notes Operating Current: Active Mode; Burst = 2; READ or
WRITE;
t RC = t RC (MIN)
I DD1210185mA3, 18, 19, 28
Standby Current: Power-Down Mode; All banks idle; CKE
= LOW
I DD2N800800μA32
Standby Current: Power-Down Mode; All banks idle; CKE
= HIGH
I DD2NS6060mA
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after t RCD met; No accesses in progress
I DD3NS8080mA3, 12, 19, 28
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
I DD3N6060mA
Operating Current: Burst Mode; Continuous burst; READ
or WRITE; All banks active, half DQs toggling every cycle.
I DD4165140mA3, 18, 19, 28
Auto Refresh Current CKE = HIGH; CS# = HIGH t RFC = t RFC
(MIN)
I DD5300250mA3, 12, 18, 19,
28, 29
t RFC = 7.8μs I DD6 5.0 5.0mA
Deep power down I ZZ2020μA
Table 7: I DD Specifications and Conditions (V version)
V DD = +2.5 ±0.2V, V DD Q = +2.5 ±0.2V
Notes: 1, 5, 6, 11, 13; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
MAX
Parameter/Condition Symbol-8-10Units Notes Operating Current: Active Mode; Burst = 2; READ or
WRITE;
t RC = t RC (MIN)
I DD1210185mA3, 18, 19, 28
Standby Current: Power-Down Mode; All banks idle;
CKE = LOW
I DD2N800800μA32
Standby Current: Power-Down Mode; All banks idle;
CKE = HIGH
I DD2NS6060mA
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after t RCD met; No accesses in progress
I DD3NS8080mA3, 12, 19, 28
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
I DD3N6060mA
Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active, half DQs toggling
every cycle.
I DD4165140mA3, 18, 19, 28
Auto Refresh Current CKE = HIGH; CS# = HIGH t RFC = t RFC
(MIN)
I DD5300250mA3, 12, 18, 19,
28, 29
t RFC = 7.8μs I DD6 5.0 5.0mA
Deep power down I ZZ2020μA
Table 8: I DD Specifications and Conditions (H version)
V DD = 1.8 ±0.1V, V DD Q = 1.8V ±0.1V
Notes: 1, 5, 6, 11, 13; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
MAX
Parameter/Condition Symbol-8-10Units Notes Operating Current: Active Mode; Burst = 2; READ or
WRITE;
t RC = t RC (MIN)
I DD1155130mA3, 18, 19, 28
Standby Current: Power-Down Mode; All banks idle;
CKE = LOW
I DD2N600600μA32
Standby Current: Power-Down Mode; All banks idle;
CKE = HIGH
I DD2NS4040mA
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after t RCD met; No accesses in progress
I DD3NS6060mA3, 12, 19, 28
Standby Current: Active Mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
I DD3N4040mA
Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active, half DQs toggling
every cycle.
I DD411595mA3, 18, 19, 28
Auto Refresh Current CKE = HIGH; CS# = HIGH t RFC = t RFC
(MIN)
I DD5245205mA3, 12, 18, 19,
28, 29
t RFC = 7.8μs I DD6 5.0 5.0mA
Deep power down I ZZ2020μA
I DD 7 Curves
Figure 3:
Typical Self Refresh Current vs. Temperature – 3.3V Part
Table 9:
I DD 7 - Self Refresh Current Options
Note: 4; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes. Values for I DD 7 for 85oC are 100 percent tested. Values for 70oC, 45oC, and 15oC are sampled only.
Temperature Compensated Self Refresh Parameter/Condition MAX Temperature
V DD = 3.3 V DD = 2.5 V DD = 1.8Units Notes Self Refresh Current:
CKE = LOW – 4 Bank Refresh
85oC 160016001200μA 470oC 130********μA 445oC 10001000740μA 415oC 864864630μA 4Self Refresh Current:
CKE = LOW – 2 Bank Refresh
85oC 12001200900μA 470oC 10251025760μA 445oC 875875640μA 415oC 800
800580μA 4Self Refresh Current:
CKE = LOW – 1 Bank Refresh
85oC 10001000750μA 470oC 900900660μA 445oC 800800590μA 415oC 760760560μA 4Self Refresh Current:
CKE = LOW – Half Bank Refresh
85oC 900900680μA 470oC 825825610μA 445oC 780780566μA 415oC 750750540μA 4Self Refresh Current:
CKE = LOW – Quarter Bank Refresh
85oC 850850640μA 470oC 800800590μA 445oC 760760550μA 415oC
740
740
536
μA
4
Figure 4: Typical Self Refresh Current vs. Temperature – 2.5V Part
Figure 5: Typical Self Refresh Current vs. Temperature – 1.8V Part
Table 10: Capacitance
Parameter – FBGA “S2” Package Symbol MIN MAX Units Input Capacitance: CLK C I158pF Input Capacitance: All other input-only balls C I258pF Input/Output Capacitance: DQs C IO812pF
?
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All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
512Mb : x32 TwinDie Mobile SDRAM Addendum
Package Dimensions
Package Dimensions
Figure 6:
90-Ball FBGA (8mm x 13mm)
Notes:1.All dimensions in millimeters.
2.Recommended pad size for PCB is 0.4mm ±0.025mm.