当前位置：文档库 › Automatic translation of behavioral testbench for fully accelerated simulation

Automatic translation of behavioral testbench for fully accelerated simulation

Automatic Translation of Behavioral Testbench for Fully

Accelerated Simulation

Young-Il Kim zerone@vslab.kaist.ac.kr Chong-Min Kyung kyung@ee.kaist.ac.kr

Department of Electrical Engineering and Computer Science Korea Advanced Institute of Science and Technology

Daejeon305-701,Korea

Abstract

This paper presents the automated process of translat-ing behavioral testbench into synthesizable one for the hardware-accelerated simulation.Testbench is mainly implemented in unsynthesizable HDL description such as time delay,event control,non-static loops and se-quential statements.Nonetheless,FPGA-based accel-erator is limited to synthesizable design.To apply hard-ware acceleration to behavioral testbench,the proposed method automatically translates testbench into equiv-alent hardware by emulating the standard simulation reference model.By mapping testbench into hardware accelerator to be merged with the design under veri?-cation,we can accelerate behavioral testbench and re-move the communication overhead between the software simulator and hardware accelerator.Our experiments demonstrated that the simulation time is reduced by a factor of about1000as compared to the conventional hardware accelerated simulation.

INTRODUCTION

FPGA-based simulation acceleration increases simulation speed by of?oading time-consuming part of design from software simulator.Most commonly,only the design be-ing veri?ed is running on the hardware accelerator,while the testbench remains running in software simulator as shown in Figure1(a).In this con?guration,there are two factors that degrades the effect of hardware acceleration.First,according to the Amdahl’s law,the overall performance improvement to be gained from hardware acceleration is limited by the fraction of the time that the acceleration can be applied[1]. For instance,assume that synthesizable DUT and behav-ioral testbench occupies90%and10%time,respectively. Even though hardware accelerator would simulate design more than1000times faster than software simulator does, the overall speedup can not be over10.Second,another fac-tor to be considered is the communication overhead between software simulator and hardware accelerator.As shown in Figure1(a),software simulator communicates with hardware accelerator through communication channel in which many components are connected in serial fashion.Due to its inher-ited long path,communication overhead is becoming a new critical bottleneck in hardware accelerated simulation.

To fully accelerate design without above two factors,we should put testbench into the hardware accelerator.Al-though all of the testbench cannot be moved to the accel-erator,moving some part of testbench into accelerator gives more chances for communication-ef?cient partition between software simulator and accelerator,i.e.partition can be per-formed to minimize the number of interconnections between

(a) Conventional Simulation Acceleration

(b) Simulation Acceleration with

Communication-Efficient Testbench Partition

testbench and DUT as shown in Figure1(b).Needless to say,when all of testbench is moved into the accelerator,we can achieve high speedup.Figure1(c)shows the fully ac-celerated simulation where whole testbench is executed in hardware accelerator.

Testbench is commonly not synthesizable,thus it can not be directly mapped on hardware accelerator using common logic synthesis tools.The goal of this work is automatic translation of behavioral testbench into synthesizable one. We mainly focused on behavioral HDL description such as time control,event control,non-static loops and sequential statements.These are mainly used for testbench description. Note that this process is different from high-level behavioral synthesis in that behavioral synthesis is used for behavioral design that were intended to be implemented in hardware. Nonetheless the proposed method is for the design that were intended to apply stimulus and check responses in the soft-ware simulator.

RELATED WORKS

There are several methods to accelerate testbenches and re-duce communication overhead.In[2],a time-consuming part of the testbench is moved to hardware accelerator while the rest of behavioral testbench is running on software sim-ulator.Furthermore,the entire behavioral testbench is trans-ferred to hardware accelerator[3][4].However,these meth-ods use high-abstract message for communication.Designer need to describe message decoder in synthesizable way and rewrite testbench message by message.In[5],the system analyzes HDL code and classi?es HDL components into two parts.One part is running in software kernel and the

HDL Code

Figure2.Translation of statement into equivalent hard-ware

other part is executed in hardware.This method applies hardware acceleration to some part of testbench,which is however limited to synthesizable HDL components.In other works,multiple processor-based engine is used to accelerate simulation.However,in[6],applicable design is limited to gate-level netlist.In[7],although behavioral HDL syntax be-comes applicable,it has performance limitation.To exploit parallelism,multiple processors are used.As the number

of processor increases,the communication overhead among processors becomes bottleneck.

MAKING TESTBENCH SYNTHESIZABLE

Basic Idea

Operation sequence of HDL simulator is de?ned in simulation reference model of IEEE1364-2001Verilog HDL standard[8]. Our approach is also based on this standard model to sup-port all possible HDL syntaxes for testbench.According

to simulation reference model,the execution of a state-ment is composed of two phases.At the beginning of a simulation time step,the right-hand-side(RHS)of the as-signment is‘evaluated’and then the left-hand-side(LHS) variable is‘updated’.The updated LHS variable may cause additional‘evaluate’events for the statements sensitive to this variable.In this way,the‘evaluate’and‘update’phases are alternatively iterated until all events are executed and no more processes are left within the current time step.In the following example,there are two statements in Verilog:

always@(clk)begin

a=a+1;//statement1

b=a;//statement2

end

In each statement,the simulator performs operations in two phases.‘1E’denotes‘evaluate’operation of statement1and ‘1U’denotes‘update’operation of statement1.When value

of‘clk’is changed,‘1E’is executed and then LHS of state-ment1is updated(‘1U’).‘2E’is executed after‘1U’since statement1is blocking assignment statement.Similarly,‘2U’is executed right after‘2E’.When no more events are left,simulation time is advanced to execute next pending events.In this operation sequence,we introduced emulation clock denoted as‘eclk’.At every positive edge of‘eclk’,each operation is performed one after the other.There are several ‘eclk’cycles within a simulation time step.To implement these operations on FPGA-based accelerator,we translate assignment‘=’of a HDL statement into2-bit shift registers called equivalent assignment hardware in which two enabled registers are connected in cascade.As shown in Figure2,the left register is used for‘evaluate’operation and the right register is in charge for‘update’operation. The evaluate register and update register are enabled by evaluate trigger and update trigger signal,respectively.Equivalent Assignment Hardware

Each statement is translated into a equivalent assignment hardware.As an example,in lower left side of Figure3, there are three grey boxes called equivalent assignment hardware,which is composed of several functional blocks.‘Evaluate logic’is in charge of producing RHS value.‘Evalu-ate trigger’determines the time to enable evaluate register.‘Update trigger’determines the time to enable update register. For blocking assignment,the update trigger signal is one emulation clock delay of evaluate trigger signal.On the other hand,in the case of the nonblocking assignment, the trigger signal is delayed until no more events are left in the current time step.In addition,in case where time control‘#’is used(i.e.a=#3b;),the update time is sched-uled to the3nsec later.‘Event detector’generates‘event’signals from‘value’of signals.The‘event’trigger signal is high only for one‘eclk’cycle duration.We can imple-ment this block using XOR gate with two inputs:signal and the inversion of one clock delayed the same signal.‘Local interconnection’routes signals from evaluate registers to update register.When a LHS variable is driven by multiple statements,equivalent assignment hardwares share one update register.Whenever any of update trigger signals is activated,update registers should be updated.

Inter-Statement Event Relation

The execution sequence of every statement is implemented by the event signals interconnecting between equivalent assignment hardwares.For instance,in Figure3,state-ment4is executed followed by statement5.This is imple-mented by the signal‘EOE4’which noti?es that statement 4?nishes its operation and let statement5start. AUTOMATIC TRANSLATION PROCESS

This section shows how to automatically translate HDL into the equivalent hardware described in previous section.

At?rst,HDL constructs are analyzed and classi?ed into the following types.These are used as a basic unit of translation.?Assignment Statement(AS)

–Blocking Assignment Statement(BAS)

–Nonblocking Assignment Statement(NAS)?Time Control Statement(TC)

?Event Control Statement(EC)

Statement Translation Table

From each statement,we can extract a row of the statement information table that is composed of four main?elds, which are STID,PRE STID,ST type and contents.STID (statement ID)is unique ID to identify every basic unit. This is integer number starting from1and is increased by one for each basic unit.PRE STID(preceding statement ID)is STID of previous blocking statement that is executed right before the current statement.This information noti?es when the current statement could start to operate.Note that this?eld is?lled by STID of blocking statement such as BAS,TC and EC,while NAS is not blocking statement. ST type(statement type)?eld shows the type of basic unit. There three types,i.e.AS,TC and EC.Contents(contents of statement)?eld includes actual information of each state-ment.According to‘ST type’?eld,it contains different information.

Figure3.Example of automatic translation of testbench into synthesizable equivalent hardware

Equivalent Hardware Generation

Figure3shows automatic translation process.From a given HDL code,statement information table is built by HDL parser-based program.And then,this table is split into three tables,which are assignment table,time control table and event control table by the‘ST type’?eld.The followings are the special signals in the translated hardware:

?start(start of simulation):At simulation start-up,this signal is active for a‘eclk’cycle

?no active event:This noti?es that there are no more event at current time slot.It is used as update trigger

signal in the case of nonblocking assignment statement.?EOE(end of execution):This noti?es that execu-tion of a blocking statement is?nished.Note that

nonblocking assignment statement does not gener-

ate this signal.

Equivalent Assignment Hardware Generation Assignment table is composed of information for assign-ment statements.This table is implemented in hash table that has LHS as a key.Each row of assignment table is translated into equivalent assignment hardware as shown

in the lower left of Figure3.Each?eld of assignment table is mapped to the internal block of equivalent assign-ment hardware,i.e.‘PRE STID’,‘assign type’and‘RHS’within the‘contents’?eld are mapped to evaluate trigger, update trigger and evaluate logic,respectively.

Time Control Hardware Generation

T ime control table is composed of information for time control statements(TC).Each TC plays a role of blocking next statement until simulation time arrives target time, which is calculated by current simulation time plus its‘de-lay’value.In statement1of Figure3,when we assume that this statement starts to be executed at simulation time0, then target time becomes‘0+1nsec’.When simulation time arrives1n sec,statement1?nally releases blocking and lets statement2start execution.This operation is imple-mented in time control hardware depicted in the middle bottom of Figure3.This is a state machine that has three states such as‘idle’,‘wait’and‘end’.‘t1’signal represents target time.Initially state is set to‘idle’.When current TC is started to wait,state is moved to‘wait’.Eventually when current simulation time arrives target time,state is moved to‘end’state where‘EOE’signal becomes active to start execution of the next statement.

Event Control Hardware Generation

Event control table is composed of information for event control statements(EC).Similar to TC,EC keeps blocking next statement until the expected signal event occurs,i.e.

a signal changes its value.Event control hardware is implemented using state machine that has three states in it. When the event of the expected signal occurs,‘EOE’signal becomes active to initiate execution of next statement.

FINE-GRAINED PARALLELISM

Although our approach is based on sequential operation of simulation reference model.We can exploit parallelism for the precedence-relation-independent jobs.Figure4shows

Time

Verilog S o urce Code Delta Delay Graph

Figure4.Emulation cycle consumption:An example

delta delay graph

(b)

Figure5.(a)Simulation speed in terms of cycle per sec-

ond(CPS),(b)hardware resource for testbench

the example of delta delay graph,which is used for counting

the worst case emulation clock cycles within a simulation

time step.We can build delta delay tree by starting from

‘clk’as a root node.Statement1,4,and7are sensitive to‘clk’

change.Therefore,‘clk’node is connected to‘1E’,‘4E’and

‘7E’.As the statement1is blocking assignment,there are no

delta delay between‘1E’and‘1U’.However,as the statement

2is nonblocking assignment,there is a delta delay between

‘2E’and‘2U’.In short,we use a horizontal edge for each

nonblocking assignment,while we use a vertical edge for

each blocking assignment.The leaf nodes in the same level

can be executed in parallel because there are no precedence

relations.For example,at the time of?1,‘1E’,‘4E’and‘7E’

can be executed simultaneously.And then,‘1U’and‘2E’

are executed sequentially.Therefore,three emulation clock

cycles are required for the time?1.Finally,the worst case

number of emulation clock cycles is de?ned as follows:

max

m n

(OP(m n))

where n denotes the level number of tree and m n denotes the

leaf nodes in the n-th level.OP(m n)represents the number

of operations in node m n.In this example,the number of

emulation clock cycles for simulation time‘#0’is

max(3,1,1)+max(2,2,2)+max(1,2,1)+max(1)

=3+2+2+1=8

EXPERIMENTAL RESULTS

The automated translation described in the previous section

was implemented in Objective Caml language that is one

of functional language,which is suitable to implement HDL

parser based program.For conventional simulation accelera-

tion,Mentor Modelsim simulator is running on Intel Pentium

2.8GHz processor.Hardware accelerator is implemented as

an PCI card featuring8-million gate Xilinx Virtex-II FPGA.

Experiments of simple and typical testbenches have been

conducted to investigate improvement of the proposed fully

accelerated simulation as compared to the conventional hard-

ware accelerated simulation.

Figure5(a)shows the simulation speed of the conventional

hardware accelerated simulation and proposed acceleration

simulation.We apply?ve cases each of which has vari-

ous testbench complexity and bit-width between testbench

and DUT.As complexity and bit-width increases,the speed

of conventional method decreases,whereas the proposed

method almost remains the same.Moreover,the proposed

methods is about1000times faster than the conventional

simulation acceleration.The required hardware resource for

implementing testbench is depicted in Figure5(b).

CONCLUSIONS

In this paper,we have discussed that the performance en-

hancement of hardware accelerated simulation is critically

limited by the testbench and communication overhead.Our

approach accelerates testbench execution by exploiting?ne-

grained parallelism and removes communication overhead

by putting testbench into hardware accelerator to be merged

with hardwired design unit.Testbench is commonly im-

plemented in unsynthesizable HDL description such as time

delay,event control,non-static loops and sequential state-

ments.We propose the automated process of translating

behavioral testbench into equivalent hardware by emulating

the standard simulation reference model,which makes exist-

ing HDL testbench synthesizable without remodeling effort

and losing compatibility with original testbench.Our ex-

periments demonstrated that simulation time is reduced by a

factor of about1000as compared to the conventional hard-

ware accelerated simulation.

REFERENCES

[1]“Validity of the single-processor approach to achieving

large scale computing capabilities”,AFIPS,April1967.

[2]M.Bauer,W.Ecker,R.Henftling,and A.Zinn,“A

method for accelerating test environments”,

EUROMICRO Conference,September1999.

[3]“Synthesizable veri?cation solutions”,Duolog

Technologies,2002.

https://www.wendangku.net/doc/cc2942409.html,/veri?cationproducts.html.

[4]R.Henftling,A.Zinn,M.Bauer,M.Zambaldi,and

W.Ecker,“Re-use-centric architecture for a fully

accelerated testbench environment”,Design Automation

Conference,June2003.

[5]S.S.-P.Lin,P.-S.Tseng,“Coveri?cation system and

method”,United States Patent US6,389,379B1,May

2002.

[6]S.Cadamdi,C.S.Mulpuri,and P.N.Ashar,“A Fast,

Inexpensive and Scalable Hardware Acceleration

Technique for Functional Simulation”,Design

Automation Conference,June1998.

[7]J.Bauer,M.Bershteyn,I.Kaplan,and P.Vyedin,“A

Recon?gurable Logic Machine for Fast Event-Driven

Simulation”,Design Automation Conference,June1998.

[8]“IEEE1364standard Verilog hardware description

language”,IEEE Computer Society,September2001.

四种翻译方法,十种翻译技巧

四种翻译方法 1.直译和意译所谓直译，就是在译文语言条件许可时，在译文中既保持原文的内容，又保持原文的形式——特别指保持原文的比喻、形象和民族、地方色彩等。每一个民族语言都有它自己的词汇、句法结构和表达方法。当原文的思想内容与译文的表达形式有矛盾不宜采用直译法处理时，就应采用意译法。意译要求译文能正确表达原文的内容，但可以不拘泥与原文的形式。（张培基）应当指出，在再能确切的表达原作思想内容和不违背译文语言规范的条件下，直译有其可取之处，一方面有助于保存原著的格调，另一方面可以进新鲜的表达方法。 Literal translation refers to an adequate representation of the original. When the original coincides or almost tallies with the Chinese language in the sequence of vocabulary, in grammatical structure and rhetorical device, literal translation must be used. Free translation is also called liberal translation, which does not adhere strictly to the form or word order of the original.（郭著章）直译法是指在不违背英语文化的前提下，在英译文中完全保留汉语词语的指称意义，求得内容和形式相符的方法。

时代周刊翻译

…Back to Sleep?: Why Are 2,500 U.S. Babies Still Dying of SIDS Each Year? ‘用背部睡觉’：为什么美国每年都有2500个婴儿死于婴儿猝死综合症 Putting babies on their back to sleep has dramatically reduced the number of SIDS deaths, but thousands of babies still die each year. A look at the key risk factors. 让婴儿用背部睡觉戏剧性的减少了婴儿猝死综合症的死亡数量，但每年还是有上千数量的婴儿死亡。这有一种对于关键的风险因素的看法。 There?s no doubt that the Back to Sleep campaign launched in 1994 to get parents to stop putting babies to sleep on their tummies has been a success. In the 1970s and 1980s, the rate of infant deaths per 1,000 live births was 1.5; it?s now 0.5. 无需置疑的是，1994年发起的用背部睡觉的运动，旨在阻止父母让婴儿用肚子睡觉是成功的。在20世纪70到80年代，婴儿死亡率为每一千名安全出生婴儿中有1.5，现在是0.5。 Within a generation, most babies are now put to bed on their backs, and yet 2,500 U.S. infants still die each year in the U.S. Researchers trying to understand why have noticed a curious byproduct of the trend toward back-sleeping: as fewer babies were being put to sleep on their bellies, more babies were documented engaging in other pediatric no-nos — sleeping with their parents, for example — which is another risk factor for SIDS. 在一代人中，大部分婴儿现在都用背部放在床上，但美国每年依然有2500个婴儿死亡。研究员正试图弄明白为什么人们会注意到用背部睡觉这种趋势的奇怪的副产品：越来越少的婴儿用腹部睡觉，越来越多的婴儿被证明参与到了一些儿科禁止的事情中——例如，和父母一起睡——这是婴儿猝死综合症的另一个风险因素。 A study published Monday in the journal Pediatrics takes a look at how risk factors for SIDS have evolved over the years. In an analysis of the 954 babies who died suddenly and unexpectedly in San Diego County between 1991 and 2008 — 568 of these deaths were attributed to SIDS — researchers found that

浅析翻译的创造性

浅析翻译的创造性人们常把翻译定义为把一种语言的意思用另一种语言表达出来，所以一般人总容易将翻译看成是一种语言上的机械对应活动，丝毫谈不上有什么创意，甚至有人认为翻译就是“模仿”或“拷贝”的同义词。不仅如此，在传统观念中，作者和译者是全然不同的两种角色，作者是自由的，可以根据自己的喜好随意处置自己的作品，而译者在这方面没有任何权利，他只能跟在作者的脚步后面亦步亦趋，不敢越雷池半步，他只能如实地反映原作的思想和风格，不能有自己的主观意志，更没有发挥创造性的自由。近些年来，认为翻译缺乏创造性的看法在理论界开始受到系统而有力的挑战。当代翻译研究已经证明，翻译不仅是一个很崇高的职业，而且还是一个充满巨大创造性的职业。这对于广大的翻译工作者来说是一种鼓舞，因为这犹如打开了一扇长期关闭着的窗户，使翻译者一下子获得了一种前所未有的视野，由此对自己从事的工作性质的认识产生了一种新的飞跃。译者的创造性体现在翻译过程中的方方面面。英国翻译理论家彼得·纽马克曾列举了翻译中对译者创造性要求最高的七种情况，包括文化词语、特殊的句法结构、具有文化内涵的暗喻、习语、谚语、双关语和新造词、特殊的语音联觉效果等等。其中，最突出的是对原文中遇到的语言和文化障碍所做的出色而灵活的处理。请看例子：狄更斯的小说《大卫·科波菲尔》第22章，有这样一段近乎文字游戏的表达，幽默而不失词趣，可是，多年来成为了一个翻译难题，各路高手屡试不爽。 I love my love with an E，because she’s enticing;I hate her with an E，because she’s engaged.I took her to the sign of the exquisite，and treated her with an elopement，her name’s Emily，and she lives in the east. （David Copperfield，XXII）这段文字其实是英语中的一种嵌字顺口溜，也是一种文字游戏，说的人一般要讲六句话，每句话最后一个字的头一个字母都要一样（如上述文字都是以字母E打头的单词），如果作不上来便要受罚。此类文字游戏的翻译通常对译者都是一种挑战，因为这种文字上的特点在汉语里似乎是不可能再造的。且看以下两种译文：译1：……我爱我的爱人为了一个E，因为她是Enticing（迷人的）;我恨我的爱人为了一个E，因为她是Engaged（订了婚的）。我用我的爱人象征Exquisite （美妙），我劝我的爱人从事Elopement（私奔），她的名字是Emily（爱弥丽），她的住处在East（东方）。（转引自《英美名著翻译比较》，第271页）翻译家董秋斯是以上译文的译者。在这段译文中，英语和汉语夹杂。对于不懂英语的读者来说，那就构成了遗

科普版英语六年级下册课文及翻译 (直接打印版)

Lesson 1 I’m not feeling well. Let’s talk （M=Mom, T= Tom） M: What,'s the matter, Tom T: I'm not feeling well, Mom M: Do you have a cold T: Yes, I think so. Could you give me some water, please M: Here you are. T: Thank you, Mom. M: Tom, you must go and see a doctor. T: OK, Mom. M: It's cold outside. You must wear your coat. T: OK, Mom. Could you pass me my coat,please M: Here you are. T: Thank you, Mom M: Tell me your teacher's number. I'll call him and tell him you are sick. T: OK. Here it is. 译文 (M=妈妈,T=汤姆) 妈妈:怎么了,汤姆汤姆:我感觉不舒服,妈妈。妈妈:你感冒了吗汤姆:是的,我想是这样的。您能给我一些水吗妈妈:给你。汤姆:谢谢您,妈妈。妈妈:汤姆,你必须去看医生. 汤姆:好的,妈妈。妈妈:外面很冷。你必须穿你的外套。汤姆:好的,妈妈。您能把我的外套递给我吗妈妈:给你。汤姆:谢谢您,妈妈。妈妈:告诉我你老师的电话号码。我将给他打电话告诉他你生病了。

Unit 1 A Class Act 课文翻译

Unit 1 A CLASS ACT Florence Cartlidge 1. Growing up in bomb-blitzed Manchester during the Second World War meant times were tough, money was short, anxiety was rife and the pawnshop was a familiar destination for many families, including mine. 2. Yet I could not have asked for more enterprising and optimistic parents. They held our family together with hard work, dignity and bucketloads of cheer. My sturdy and ingenious father could turn his hand to almost anything and was never short of carpentry and handyman work. He even participated in the odd bout of backstreet boxing to make ends meet. For her part, our mum was thrifty and meticulously clean, and her five children were always sent to school well fed, very clean, and attired spotlessly, despite the hard conditions. 3. The trouble was, although my clothes were ironed to a knife-edge, and shoes polished to a gleam, not every item was standard school uniform issue. While Mum had scrimped and saved to obtain most of the gear, I still didn’t have the pres cribed blue blazer and hatband. 4. Because of the war, rationing was in place and most schools had relaxed their attitude towards proper uniforms, knowing how hard it was to obtain clothes. Nevertheless, the girls’ school I attended made it strict policy that each of its students was properly attired, and the deputy headmistress who ran the daily assembly made it her mission to teach me a lesson. 5. Despite my attempts at explaining why I couldn’t comply, and despite the fact that I was making slow progress towards the full uniform, every day I would be pulled out of line and made to stand on the stage as a shining example of what not to wear to school. 6. Every day I would battle back tears as I stood in front of my peers, embarrassed and, most often, alone. My punishment also extended to being barred from the gym team or to not taking part in the weekly ballroom dancing classes, which I adored. I desperately

新时代英语传统文化翻译

英语翻译 Unit 1Book 3. 中国传统节日以中国的农历为依据。农历年的岁首称为春节，俗称“过年”，有祈年等多种习俗，是中国人民最隆重的传统节日，象征团结兴旺。其他主要的节日有元宵节、清明节、端午节、七夕节、中秋节、重阳节、冬至节、腊八节等等。各个节日都有其来源讲究和风俗习惯。农历节日与农历中的二十四节气不同。农历节日是中华民族凝聚力和生命力的体现 Traditional Chinese festivals are usually fixed to the Lunar calendar. January 1st on the lu Seventh Festival, the Mid-Autumn Festival, the Double- Ninth Festival, the Winter Solstice, and the Eight Day of the Twelfth Lunar Month, etc. Ea Lunar calendar. They embody China's cohesion and vitality. Unit 3Book3. 中国古代四大艺术“琴棋书画” 的画特指国画。其绘画形式是用毛笔蘸水、墨、颜料作画于绢、帛、宣纸之上，古代称之为水墨丹青。为区别于西方的油画而称之为“中国画”，简称“国画”。其题材有人物、山水、花鸟等。技法可分为工笔和写意。国画的艺术特质在于“笔墨”，强调以形写神，画尽意在。国画在艺术创作上反映了中化民族的审美意识和情趣。 The four art forms in ancient China are guqin, chess, penmanship, and painting. And paint painting.” In order to distinguish it from Western oil-paintings, the Chinese people term their works “traditional Chinese painting” ( hand brushwork. The artistic characteristics lie in “the writing brush and ink.” Chinese pai 5. 中国石窟中国石窟组要反映的是佛教文化艺术。敦煌莫高窟、大同云冈石窟、洛阳龙门石窟、天水麦积山石窟，号称中国四大石窟艺术景观。佛教石窟随山雕凿、彩绘，形象生动自然，将崇尚美与世俗情融为一体，把天然造化与人工创造有机结合，是由建筑、绘画、雕塑等组成的博大精深、绚丽夺目的综合艺术殿堂。其艺术成就为世界瞩目，已成为重要的世界文化遗产。 Chinese Grottoes Chinese grottoes mainly reflect the art of Buddhist culture. In China， there are four major art landscape of grottoes:the Mogao Grottoes at Dunhuang, the Yungang Grottoes at Datong, the Longmen Grottoes at Luoyang, and the Maijishan Grottoes at Tianshui. Carved and painted on mountains, the Buddhist grottoes mingle both sublimity and secular feelings together, presenting us a vivid and natural appearance. They embody the systematic combination of both the exceptional artistry of great nature and the extremely fine craftsmanship of mankind. The Chinese Buddhist Grottoes are regarded

谈古诗翻译中译者的创造性

谈古诗翻译中译者的创造性 [摘要]古诗翻译要求译者根据需要发挥自身的创造性，对诗歌进行形式和意义的变通，最大限度地把原诗的情、韵、意完好地再现出来，从而达到译文和原文在意境、文化背景和情感上的和谐统一。标签：古诗翻译；创造性；译者 [一、概论在古诗翻译中，关于译者能不能进行创造性翻译的问题，许渊冲提出了另一种创造性的翻译理论，那就是译诗与原诗的创优似竞赛论。他认为，“文学翻译是两种语言甚至是两种文化之间的竞赛，看哪种文字能更好地表达原作的内容。”(许渊冲，2003)他主张译者应该充分发挥创作精神，译出“青出于蓝而胜于蓝”的好诗，译者作为翻译的主体在翻译过程中尽量忠实于原作的同时又具有极大的自主性。作品中留有许多空白与不定点等待着读者去补充，而读者的思想中又存在不同的先行结构与前理解，所以读者不同，补充的图景也各异。译者不仅是原作的读者，还是译作的创作者。他们以理解的主动性、阐释的能动性以及重构的创造性把一个全新的译作呈现在译语读者面前，但同时译者不能完全脱离原文文本随意发挥，因为原作作为一个独立的审美客体具有相对固定的审美意蕴，寄寓了原作者的某种情感。译者的责任应该是把它们尽量完美地再现出来，在译语读者面前呈现出一个忠实的译语文本。二、译者的创造性发挥达到与意境的和谐译文是原文的代替物，而不是译者随心所欲地改变原文的意思、风格，按照自己的意图重新创造出译文。诗歌有它比较固定的模式或内涵，翻译时，我们有时需要把诗歌原文中的意境传达出来，充分发掘出蕴涵于其中的美的因素。明朝的朱承爵说：“作诗之妙，全在意境融彻，出声音之外，乃得真味。”(陈伟，1997)这说明了意境的重要性，也说明了译者需要在翻译过程中既要在考虑到源语的语言特征的同时，还要充分考虑到译语的特点，进行创造性的语言转化，使译文符合目的语的语言习惯特征。根据语境的需要还需进行必要的增减词，进行整体的变通。如：刘方平的《月野》中有：更深月色半人家，北斗阑干南斗斜。今夜偏知春气暖，虫声新透绿窗纱。 Winter Bynner的译文为： When the moon has colored half the house， With the North Star at its height and the South starsertting，

outofstep课文全文翻译.doc

Unit 3 Out of Step Bill Bryson 1 After living in England for 20 years, my wife and I decided to move back to the United States. We wanted to live in a town small enough that we could walk to the business district, and settled on Hanover, N.H., a typical New England town—pleasant, sedate and compact. It has a broad central green surrounded by the venerable buildings of Dartmouth College, an old-fashioned Main Street and leafy residential neighborhoods. 2 It is, in short, an agreeable, easy place to go about one’ s business on foot, and ye far as I can tell, virtually no one does. 3 Nearly every day, I walk to the post office or library or bookstore, and sometimes, if I am feeling particu larly debonair, I stop at Rosey Jekes Caféa cappuccino. Occasionally, in the evenings, my wife and I stroll up to the Nugget Theatre for a movie or to Murphy’ s on the Green for a beer, I wouldn’ t dream of going to any of these places by car. People ha ve gotten used to my eccentric behavior, but in the early days acquaintances would often pull up to the curb and ask if I wanted a ride. 4“ I’ m going your way,” they would insist when I politely declined. no bother.”

高一英语翻译技巧和方法完整版及练习题及解析

高一英语翻译技巧和方法完整版及练习题及解析一、高中英语翻译 1．高中英语翻译题：Translation: Translate the following sentences into English, using the words given in the brackets. 1．究竟是什么激发小王学习电子工程的积极性？(motivate) 2．网上支付方便了客户，但是牺牲了他们的隐私。(at the cost of) 3．让我的父母非常满意的是，从这个公寓的餐厅可以俯视街对面的世纪公园，从起居室也可以。(so) 4．博物馆疏于管理，展品积灰，门厅冷落，急需改善。(whose) 【答案】 1．What on earth has motivated Xiao Wang’s enthusiasm/ initiative to major in electronic engineering? 2．Online payment brings convenience to consumers at the cost of their privacy. 3．To my parents’ satisfaction, the dining room of this apartment overlooks the Century Park opposite the street and so it is with the sitting room. 或者What makes my parents really satisfy is that they can see the Century Park from the dining room of this apartment, so can they from the living room. 4．This museum is not well managed, whose exhibits are covered with dust, and there are few visitors, so everything is badly in need of improvement. 或The museum whose management is reckless, whose exhibits are piled with dust and whose lobby is deserted, requires immediate improvement. 【解析】 1．motivate sb to do sth 激发某人做某事，on earth究竟，major in 以…为专业，enthusiasm/ initiative热情/积极性，故翻译为What on earth has motivated Xiao Wang’s enthusiasm/ initiative to major in electronic engineering? 2．online payment网上支付，brings convenience to给…带来方便，at the cost of以…为代价，privacy隐私，故翻译为Online payment brings convenience to consumers at the cost of their privacy. 3．To my parents’ satisfaction令我父母满意的是，后者也那样so it is with。也可以用主语从句What makes my parents really satisfy 表语从句thatthey can see the Century Park from the dining room of this apartment。overlooks俯视，opposite the street街对面，living room 起居室。故翻译为To my parents’ satisfaction, the dining room of this apartment overlooks the Century Park opposite the street and so it is with the sitting room.或者What makes my parents really satisfy is that they can see the Century Park from the dining room of this apartment, so can they from the living room. 4．not well managed/ management is reckless疏于管理，be covered with dust/ be piled with dust被灰尘覆盖，few visitors游客稀少，be badly in need of improvement/ requires immediate improvement亟需改善。故翻译为his museum is not well managed, whose exhibits

地层时代中英文对照

圭亚那盆地地层时代中英文对照 Cainozoic 新生界 Tertiary 第三纪 Pleistocene 第三纪更新世 Miocene 第三纪中新世 Lower Miocene 第三纪下中新世 Oligocene 第三纪渐新世 Eocene 第三纪始新世 Middle Eocene第三纪中始新世 Lower Eocene第三纪下始新世 Paleocene 第三纪古新世、古近系 Cretaceous 白垩纪 Senonian 森诺阶 Campanian 坎帕阶 Santonian 桑托阶 Coniacian 科尼亚克阶（晚白垩纪第三期）Turonian 白垩纪土仑阶（晚白垩纪第二期）Cenomanian 森诺曼阶 Albian 阿尔比阶 Aptian 阿普第阶 Barremian 巴列姆阶 Precambrian 前寒武纪地层

Cainozoic 新生界 Quaternary 第四系Quaternary period 第四纪Paleocene 第三纪古新世、古近系 Mesozoic中生界 Cretaceous 白垩系 Jurassic 侏罗系 Triassic 三叠系 LateTriassicepoch 晚三叠世 Paleozoic 古生界 Permian 二叠系 LatePermianepoch Early Permian 早二叠世 Carboniferous 石炭系石炭纪 Late Carboniferous Devonian 泥盆系泥盆纪upperDevonionseries 上泥盆统 siluric 志留系Silurian 志留纪 Ordovician 奥陶系奥陶纪 Cambrian 寒武系寒武纪 Proterozoic era 元古代

翻译的创造性

翻译的创造性翻译因为通常被定义为把一种语言的意思用另一种语言表达出来，所以一般人总容易将翻译看成是一种语言上的机械对应活动，根本谈不上有什么创意。但是近些年来，这种看法开始受到系统而有力的挑战。这对于翻译工作者来说是一种鼓舞，因为这犹如打开了一扇长期关闭着的窗户，使翻译者一下子获得了一种前所未有的视野，由此对自己从事的工作性质的认识产生了一种新的飞跃。当代翻译研究已经证明，翻译不仅是一个很崇高的职业，而且还是一个充满巨大创造性的职业。在由Ann Beylard-Ozerfoff等大主编的题为《翻译者的策略与创造性》一书中，就有专门文章来讨论翻译与创造性的问题。在谈论翻译的创造性之前，我们必须要清楚地界定什么是创造性。该书中有关文章对创造性行为的认定可以概括成以下几个方面: 1.创造性指一个人产生新的或原创思想、艺术创造的能力O。一个创造性的构想一般定义为这样一种构想，它是"有新意的，而且在某种程度上对于其所出现于其中的情景有用或合适"。 2.创造性还可以有另外一种定义，它指把原先存在的一些构想以新奇的方式加以组合。 3.一种学科的规则与约束，不仅不与创造性对立，而且还使创造性成为可能。每一件音乐作品的创作都不能超出音符系统的范畴。一个文学作品，即使它是标新立异之作，也总是要符合它所成文语言的语法规则。但须在掌握了某一学科规则之后，方有可能来打破这种规则，这又是一种体现，创意的方式。 4.创造性行为还可以界定为一种解决问题能力的形式。 5.翻译的过程是将源语转变成为目的语的过程。这一转换过程导致一个新的文本的产生，这个新文本在内容上虽与原作相同，但却是一个崭新的作品。从这一点上说，这就是一件创造性的作品。它是在词、句、语义三个层面上重构信息的结果。语言结构重组的程度越高，这个转换过程的创意便越大。

(完整版)大学英语精读3课文(第三版)_中英文对照

课文翻译 Unit 1 Text A young man finds that strolling along the streets without an obvious purpose can lead to trouble with the law. One misunderstanding leads to another until eventually he must appear in court for trial…… 一个青年发现，在大街上毫无明显目的地游逛会招致警方的责罚。误会一个接一个发生，最终他只得出庭受审…… A Brush with the Law 与警察的一场小冲突 I have only once been in trouble with the law. 我平生只有一次跟警方发生纠葛。 The whole process of being arrested and taken to court was a rather unpleasant experience at the time, but it makes a good story now. 被捕和出庭的整个过程在当时是一件非常不愉快的事，但现在倒成了一篇很好的故事。 What makes it rather disturbing was the arbitrary circumstances both of my arrest and my subsequent fate in court. 这次经历令人可恼之处在于围绕着我的被捕以及随后庭上审讯而出现的种种武断专横的情况。It happened in February about twelve years ago. 事情发生在大约12年前，其时正是2月。 I had left school a couple of months before that and was not due to go to

文言文翻译技巧和方法

文言文翻译技巧和方法一、基本方法：直译和意译文言文翻译的基本方法有直译和意译两种。所谓直译，是指用现代汉语的词对原文进行逐字逐句地对应翻译，做到实词、虚词尽可能文意相对。直译的好处是字字落实;其不足之处是有时译句文意难懂，语言也不够通顺。所谓意译，则是根据语句的意思进行翻译，做到尽量符合原文意思，语句尽可能照顾原文词义。意译有一定的灵活性，文字可增可减，词语的位置可以变化，句式也可以变化。意译的好处是文意连贯，译文符合现代语言的表达习惯，比较通顺、流畅、好懂。其不足之处是有时原文不能字字落实。这两种翻译方法当以直译为主，意译为辅。二、具体方法：留、删、补、换、调、变。 “留”：就是保留。凡是古今意义相同的词，以及古代的人名、地名、物名、官名、国号、年号、度量衡单位等，翻译时可保留不变。例如：《晏子使楚》中的“楚王”、“晏婴”、“晏子”等不用翻译。 “删”，就是删除。删掉无须译出的文言虚词。例如：“寡人反取病焉”的“焉”是语气助词，可不译，本句的意思就是“我反而自讨没趣。”(《晏子使楚》)又如：“子猷、子敬俱病笃，而子敬先亡”中的“而”是连词，可不译，整句意思是“子猷与子敬都病重，子敬先死去。” “补”，就是增补。(1)变单音词为双音词，如《桃花源记》中“率妻子邑人来此绝境”，“妻子”一词是“妻子、儿女”的意思;(2)补出省略句中的省略成分，如《人琴俱亡》中“语时了不悲”，翻译为：(子猷)说话时候完全不悲伤。 “换”，就是替换。用现代词汇替换古代词汇。如把“吾、余、予”等换成“我”，把“尔、汝”等换成“你”。“调”就是调整。把古汉语倒装句调整为现代汉语句式。例如《人琴俱亡》中“何以都不闻消息”，“何以”是“以何”的倒装，宾语前置句，意思是“为什么”。“变”，就是变通。在忠实于原文的基础上，活译有关文字。“子猷问左右”(人琴俱亡))中的“左右”指的是“手下的人”，“左右对曰”(《晏子使楚》中的“左右”指的是“近臣”。古文翻译口诀古文翻译，自有顺序，首览全篇，掌握大意；先明主题，搜集信息，由段到句，从句到词，全都理解，连贯一起，对待难句，则需心细，照顾前文，联系后句，

大数据时代英文翻译

Era of Big Data is a woman's age; women in the gene can accumulate and deal with big data/ women are born to accumulate and deal with big data. Many men and children, in fact, have been wondering about this special ability of women. Like, as a child, just as soon as you entered the house your Mother said immediately in a suspicious tone: “Liu zhijun, you didn’t do well in the exam today, did you.” Another example, you just have a glance at the mobile phone, your wife laughs: “Does Er gou the next door ask you to play games?” One more ex ample, when you close the door and make a phone call, your girlfriend will cry: “Who are shot in bed?” They are sometimes right, sometimes wrong. However, On the whole, the accuracy rate is higher than chance level. When they are wrong, men would sneer women always give way to foolish fancies; when they are right, men would say women are sensitive animal maybe with more acute sensory organs. Anyway, that is a guess. It has already scared man that overall accuracy rate is higher than the random level. In order to adapt to this point, the male also developed a very strong skills against reconnaissance. This part is beyond the scope of this article, so no more details about it. Some studies, such as Hanna Holmes’s paper, have indi cated that the white matter of the female’s brain is higher than that of the male. So they have very strong imagination of connecting things together. Some recent studies have shown that women are better than men in the "date" memory. That is the reason why they are able to remember all the birthdays, anniversaries, and even some of the great day of unimportant friends. No matter whether these results are true or not, I am afraid that this is not women's most outstanding ability. Women's most remarkable ability is a long-term tracking of some seemingly unimportant data to form their own baseline and pattern. Once the patterns of these data points are significantly different from the baseline she is familiar with, she knows something unusual. In their daily life, women do not consider the difference between causality and correlation. They believe in the principle: "There must be something wrong out of something unusual." People who talk about big data often take Lin Biao as an example. Lin Biao recorded some detailed and unimportant data after a battle. Such as seized guns, the proportion of rifles and pistols, the age levels of war prisoners, seized grain, whether they are sorghum or millet, etc., all of which were unavoidably recorded in the book. Others laughed at him. But later, he determined where the enemy headquarters were according to these data. What women do is almost the same. A girl A has a secret crush on boy B, but she usually doesn’t contact him directly. Two days later, I asked her if she wanted to ask him to have dinner together. She said he was playing. I wondered “how do you know that?” She said that boy B usually is on the line Gmail at 8:00 am, away status at8:30am, for he goes out to buy coffee and breakfast, on line again at 9:00am, busy status, for he is at work, away again at12:30am for lunch, on line for whole evenings, maybe for reading or playing games. His buddy C is on line at10:00 am, still online till 2:00am next day. He is a boy who gets up late and stays up late. His buddy D is on line for the most of the day. However, the most important pattern is that there are 2-3 days per week, during which they would be offline or away for 3-4 hours together. Conclusion: they are playing together.