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74ALVCF322835中文资料

? 2002 Fairchild Semiconductor Corporation DS500741

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May 2002Revised May 2002

74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26? Series Resistors in Outputs

74ALVCF322835

Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs

and 26? Series Resistors in Outputs

General Description

The 74ALVCF322835 low voltage 36-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is tog-gled. Data transfers from the Inputs (I n ) to Outputs (O n ) on a Positive Edge Transition of the Clock. When OE is LOW,the output data is enabled. When OE is HIGH the output port is in a high impedance state.

The 74ALVCF322835 is designed with 26? series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The 74ALVCF322835 is designed for low voltage (1.65V to 3.6V) V CC applications with I/O capability up to 3.6V.The 74ALVCF322835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.Features

s Compatible with PC133 DIMM module specifications s 1.65V to 3.6V V CC specifications provided s 3.6V tolerant outputs

s 26? series resistors in outputs s t PD (CLK to O n )

3.7 ns max for 3.0V to 3.6V V CC

4.6 ns max for 2.3V to 2.7V V CC 7.4 ns max for 1.65V to 1.95V V CC s Power-down high impedance outputs s Latchup conforms to JEDEC JED78s ESD performance:

Human body model > 2000V Machine model >200V

Ordering Code:

Note 1: Ordering Code “G” indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number Package Number Package Description

74ALVCF322835G (Note 1) (Note 2)

BGA114A

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

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74A L V C F 322835

Connection Diagram (Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Truth Table

H = Logic HIGH L = Logic LOW

X = Don ’t Care, but not floating Z = High Impedance

↑ = LOW-to-HIGH Clock Transition

Note 3: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW.Note 4: Output level before the indicated steady-state input conditions were established.

Pin Names Description

OE n Output Enable Input (Active LOW)LE n Latch Enable Input CLK n Clock Input 1I 1 - 1I 18Data Inputs 2I 1 - 2I 18Data Inputs 1O 1 - 1O 183-STATE Outputs 2O 1 - 2O 18

3-STATE Outputs

23456A 1O 21O 1NC NC 1I 11I 2B 1O 41O 3NC GND 1I 31I 4C 1O 61O 5GND GND 1I 51I 6D 1O 81O 7V CC V CC 1I 71I 8E 1O 101O 9GND GND 1I 91I 10F 1I 121O 11GND GND 1I 111I 12G 1O 141O 13V CC V CC 1I 131I 14H 1O 151O 16GND GND 1I 161I 15J 1O 171O 18OE 1CLK 11I 181I 17K NC NC LE 1GND NC NC L 2O 22O 1NC GND 2I 12I 2M 2O 42O 3GND GND 2I 32I 4N 2O 62O 5V CC V CC 2I 52I 6P 2O 82O 7GND GND 2O 72I 8R 2O 102O 9GND GND 2I 92I 10T 2O 122O 11V CC V CC 2I 112I 12U 2O 142O 13GND GND 2I 132I 14V 2O 152O 16OE 2CLK 22I 162I 15W

2O 17

2O 18

LE 2

GND

2I 18

2I 17

Inputs

Outputs OE n LE n CLK n I n O n H X X X Z L H X L L L H X

H H L L ↑L L L L ↑H H L L H X O 0 (Note 3)L

O 0 (Note 4)

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Logic Diagram

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74A L V C F 322835

Absolute Maximum Ratings (Note 5)

Recommended Operating Conditions (Note 7)

Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat-ings. The “Recommended Operating Conditions ” table will define the condi-tions for actual device operation.

Note 6: I O Absolute Maximum Rating must be observed.

Note 7: Floating or unused control inputs must be held HIGH or LOW.

DC Electrical Characteristics

Supply Voltage (V CC )?0.5V to +4.6V DC Input Voltage (V I )?0.5V to 4.6V Output Voltage (V O ) (Note 6)?0.5V to V CC +0.5V

DC Input Diode Current (I IK ) V I < 0V

?50 mA DC Output Diode Current (I OK )V O < 0V

?50 mA DC Output Source/Sink Current (I OH /I OL )

±50 mA DC V CC or GND Current per Supply Pin (I CC or GND)

±100 mA

Storage Temperature Range (T STG )

?65°C to +150°C

Power Supply

Operating 1.65V to 3.6V Input Voltage 0V to V CC Output Voltage (V O )

0V to V CC

Free Air Operating Temperature (T A )?40°C to +85°C

Minimum Input Edge Rate (?t/?V)V IN = 0.8V to 2.0V, V CC = 3.0V

10 ns/V

Symbol Parameter

Conditions

V CC Min Max

Units

(V)V IH

HIGH Level Input Voltage

1.65 - 1.950.65 x V CC

2.3 - 2.7 1.72.7 -

3.6

2.0

V IL

LOW Level Input Voltage

1.65 - 1.950.35 x V CC

V 2.3 - 2.70.72.7 - 3.6

0.8

V OH

HIGH Level Output Voltage

I OH = ?100 μA 1.65 - 3.6V CC - 0.2V

I OH = ?2 mA 1.65 1.2I OH = ?4 mA 2.3 1.9I OH = ?6 mA 2.3 1.73.0 2.4I OH = ?8 mA 2.72I OH = ?12 mA

3.02

V OL

LOW Level Output Voltage

I OL = 100 μA 1.65 - 3.60.2V I OL = 2 mA 1.650.45I OL = 4 mA 2.30.4I OL = 6 mA 2.30.553.00.55I OL = 8 mA 2.70.6I OL = 12 mA

3.00.8I OH

High Level Output Current

1.65?2mA

2.3?62.7?8

3.0

?12I OL

Low Level Output Current

1.652mA

2.362.78

3.0

12I I Input Leakage Current 0 ≤ V I ≤ 3.6V

1.65 - 3.6±5.0μA I OZ 3-STATE Output Leakage 0 ≤ V O ≤ 3.6V, V I = V IH or V IL 1.65 - 3.6

±10μA I OFF Power Off Leakage Current 0V ≤ (V I , V O ) ≤ 3.6V 010mA I CC Quiescent Supply Current V I = V CC or GND, I O = 0 3.640μA ?I CC

Increase in I CC per Input

V IH = V CC ? 0.6V

2.7 -

3.6

750

μA

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74ALVCF322835

AC Electrical Characteristics

Capacitance

Symbol

Parameter

T A = ?40°C to +85°C, R L = 500?

Units

C L = 50 pF

C L = 30 pF

V CC = 3.3V ± 0.3V

V CC = 2.7V V CC = 2.5 ± 0.2V V CC = 1.8V ± 0.15V Min

Max

Min Max

f MAX Maximum Clock Frequency 250200200100MHz t PHL , t PLH

Propagation Delay 1.1

3.6

1.3

4.50.8

4.0 1.5

7.2ns Bus-to-Bus

t PHL , t PLH

Propagation Delay 1.5 3.7 2.0 4.6 1.5 4.1 2.07.4ns

Clock to Bus

t PHL , t PLH

Propagation Delay 1.1 4.2 1.3 5.20.8 4.7 1.58.5ns LE to Bus

t PZL , t PZH Output Enable Time 1.1 4.8 1.3 6.40.8 5.9 1.59.8ns t PLZ , t PHZ Output Disable Time 1.1 4.7

1.3 5.2

0.8 4.7

1.57.9

ns t S Setup Time 1.5 1.5 1.5 2.5ns t H Hold Time 0.70.70.7 1.0ns t W

Pulse Width

1.5

4.0

Symbol Parameter

Conditions

T A = +25°C Units V CC Typical C IN Input Capacitance V I = 0V or V CC 3.3 3.5pF C OUT Output Capacitance

V I = 0V or V CC

3.3 5.5pF C PD

Power Dissipation Capacitance

Outputs Enabled f = 10 MHz, C L = 0 pF

3.313pF

2.5

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74A L V C F 322835

OUT - V OUT Characteristics

I OH versus V OH

FIGURE 1. Characteristics for Output - Pull Up Drive

I OL versus V OL

FIGURE 2. Characteristics for Output - Pull Down Driver

74ALVCF322835

AC Loading and Waveforms

FIGURE 3. AC Test Circuit

Table 1: Values for Figure 1

Table 2: Variable Matrix

(Input Characteristics: f = 1MHz; t r = t f = 2ns; Z0 = 50?)

FIGURE 4. Waveform for Inverting and

Non-inverting Functions

FIGURE 5. 3-STATE Output High Enable and

Disable Times for Low Voltage Logic FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

TEST SWITCH

t PLH, t PHL Open

t PZL, t PLZ V L

t PZH, t PHZ GND

Symbol

V CC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V

V mi 1.5V 1.5V V CC/2V CC/2

V mo 1.5V 1.5V V CC/2V CC/2

V X V OL+ 0.3V V OL+ 0.3V V OL+ 0.15V V OL+ 0.15V

V Y V OH? 0.3V V OH? 0.3V V OH? 0.15V V OH? 0.15V

V L6V6V V CC*2V CC*2

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74A L V C F 322835 L o w V o l t a g e 36-B i t U n i v e r s a l B u s D r i v e r w i t h 3.6V T o l e r a n t O u t p u t s a n d 26? S e r i e s R e s i s t o r s i n O u t p u t s

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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